From 553335bb10428db37d815a5b2dd46edf9aba19c7 Mon Sep 17 00:00:00 2001
From: Robert Ghilduta <robert.ghilduta@nuand.com>
Date: Tue, 20 Aug 2019 03:10:15 -0700
Subject: [PATCH 3/4] bladeRF2: update RX parameters

To align RX1 and RX2, flip RX2 phase inversion
---
 fpga_common/src/ad936x_params.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpga_common/src/ad936x_params.c b/fpga_common/src/ad936x_params.c
index b1e1234a..7606074a 100644
--- a/fpga_common/src/ad936x_params.c
+++ b/fpga_common/src/ad936x_params.c
@@ -242,7 +242,7 @@ AD9361_InitParam bladerf2_rfic_init_params = {
     5,              // TX_DATA/TX_FRAME delay = 1.5 ns                                  // tx_data_delay *** adi,tx-data-delay
     300,            // LVDS driver bias 300 mV                                          // lvds_bias_mV *** adi,lvds-bias-mV
     1,              // Enable LVDS on-chip termination                                  // lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable
-    0,              // RX1 and RX2 are not phase-aligned                                // rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable
+    1,              // RX1 and RX2 are not phase-aligned                                // rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable
     0xFF,           // Default signal inversion mappings                                // lvds_invert1_control *** adi,lvds-invert1-control
     0x0F,           // Default signal inversion mappings                                // lvds_invert2_control *** adi,lvds-invert2-control
     1,              // CLK_OUT drive increased by ~20%                                  // clk_out_drive
-- 
2.20.1

