<EDKSYSTEM EDKVERSION="14.4" EDWVERSION="1.2" TIMESTAMP="Fri Sep 27 16:55:17 2013">

  <SYSTEMINFO ARCH="zynq" DEVICE="xc7z020" PACKAGE="clg484" PART="xc7z020clg484-1" SOURCE="D:/AD/GitHub/no-OS/Pmods/PmodDA1/cf_ad7303_zed/system.xmp" SPEEDGRADE="-1"/>

  <EXTERNALPORTS>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="53" LSB="0" MHS_INDEX="0" MSB="53" NAME="processing_system7_0_MIO" RIGHT="0" SIGNAME="processing_system7_0_MIO">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="MIO"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="1" NAME="processing_system7_0_PS_SRSTB" SIGNAME="processing_system7_0_PS_SRSTB">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_SRSTB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="2" NAME="processing_system7_0_PS_CLK" SIGIS="CLK" SIGNAME="processing_system7_0_PS_CLK">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_CLK"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="3" NAME="processing_system7_0_PS_PORB" SIGNAME="processing_system7_0_PS_PORB">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[PS_REQUIRED_EXTERNAL_IO]" INSTANCE="processing_system7_0" PORT="PS_PORB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="4" NAME="processing_system7_0_DDR_Clk" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Clk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="5" NAME="processing_system7_0_DDR_Clk_n" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk_n">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Clk_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="6" NAME="processing_system7_0_DDR_CKE" SIGNAME="processing_system7_0_DDR_CKE">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CKE"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="7" NAME="processing_system7_0_DDR_CS_n" SIGNAME="processing_system7_0_DDR_CS_n">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="8" NAME="processing_system7_0_DDR_RAS_n" SIGNAME="processing_system7_0_DDR_RAS_n">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_RAS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="9" NAME="processing_system7_0_DDR_CAS_n" SIGNAME="processing_system7_0_DDR_CAS_n">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_CAS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="10" NAME="processing_system7_0_DDR_WEB_pin" SIGNAME="processing_system7_0_DDR_WEB">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_WEB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="11" MSB="2" NAME="processing_system7_0_DDR_BankAddr" RIGHT="0" SIGNAME="processing_system7_0_DDR_BankAddr">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_BankAddr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="14" LSB="0" MHS_INDEX="12" MSB="14" NAME="processing_system7_0_DDR_Addr" RIGHT="0" SIGNAME="processing_system7_0_DDR_Addr">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_Addr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="13" NAME="processing_system7_0_DDR_ODT" SIGNAME="processing_system7_0_DDR_ODT">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_ODT"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="14" NAME="processing_system7_0_DDR_DRSTB" SIGIS="RST" SIGNAME="processing_system7_0_DDR_DRSTB">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DRSTB"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="31" LSB="0" MHS_INDEX="15" MSB="31" NAME="processing_system7_0_DDR_DQ" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQ">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQ"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="16" MSB="3" NAME="processing_system7_0_DDR_DM" RIGHT="0" SIGNAME="processing_system7_0_DDR_DM">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DM"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="17" MSB="3" NAME="processing_system7_0_DDR_DQS" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQS"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="3" LSB="0" MHS_INDEX="18" MSB="3" NAME="processing_system7_0_DDR_DQS_n" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS_n">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_DQS_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="19" NAME="processing_system7_0_DDR_VRN" SIGNAME="processing_system7_0_DDR_VRN">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_VRN"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="20" NAME="processing_system7_0_DDR_VRP" SIGNAME="processing_system7_0_DDR_VRP">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[MEMORY_0]" INSTANCE="processing_system7_0" PORT="DDR_VRP"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="21" NAME="hdmi_clk" SIGNAME="axi_hdmi_tx_16b_0_hdmi_clk">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="hdmi_clk"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="22" MSB="15" NAME="hdmi_data" RIGHT="0" SIGNAME="axi_hdmi_tx_16b_0_hdmi_data">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="hdmi_data"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="23" NAME="hdmi_hsync" SIGNAME="axi_hdmi_tx_16b_0_hdmi_hsync">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="hdmi_hsync"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="24" NAME="hdmi_vsync" SIGNAME="axi_hdmi_tx_16b_0_hdmi_vsync">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="hdmi_vsync"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="25" NAME="hdmi_data_e" SIGNAME="axi_hdmi_tx_16b_0_hdmi_data_e">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="hdmi_data_e"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="26" NAME="hdmi_spdif" SIGNAME="axi_spdif_tx_0_spdif_tx_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_spdif_tx_0" PORT="spdif_tx_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="27" NAME="hdmi_int" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="hdmi_int">
      <CONNECTIONS/>
    </PORT>
    <PORT DIR="O" MHS_INDEX="28" NAME="otg_reset" SIGNAME="net_vcc">
      <CONNECTIONS>
        <CONNECTION INSTANCE="net_vcc"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="29" NAME="otg_vbusoc" SIGNAME="net_otg_oc">
      <CONNECTIONS>
        <CONNECTION INSTANCE="util_vector_logic_0" PORT="Op1"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="0" MHS_INDEX="30" MSB="0" NAME="util_vector_logic_0_Op1_pin" RIGHT="0" SIGNAME="net_util_vector_logic_0_Op1_pin">
      <CONNECTIONS/>
    </PORT>
    <PORT DIR="O" MHS_INDEX="31" NAME="axi_i2s_adi_0_BCLK_O_pin" SIGIS="CLK" SIGNAME="axi_i2s_adi_0_BCLK_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[I2S]" INSTANCE="axi_i2s_adi_0" PORT="BCLK_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="32" NAME="axi_i2s_adi_0_LRCLK_O_pin" SIGIS="CLK" SIGNAME="axi_i2s_adi_0_LRCLK_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[I2S]" INSTANCE="axi_i2s_adi_0" PORT="LRCLK_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="33" NAME="axi_i2s_adi_0_SDATA_I_pin" SIGNAME="axi_i2s_adi_0_SDATA_I">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[I2S]" INSTANCE="axi_i2s_adi_0" PORT="SDATA_I"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="34" NAME="axi_i2s_adi_0_SDATA_O_pin" SIGNAME="axi_i2s_adi_0_SDATA_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[I2S]" INSTANCE="axi_i2s_adi_0" PORT="SDATA_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="35" NAME="axi_i2s_adi_0_MCLK_pin" SIGNAME="clock_generator_0_CLKOUT0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="1" LSB="0" MHS_INDEX="36" MSB="1" NAME="util_i2c_mixer_0_downstream_scl_pin" RIGHT="0" SIGNAME="util_i2c_mixer_0_downstream_scl">
      <CONNECTIONS>
        <CONNECTION INSTANCE="util_i2c_mixer_0" PORT="downstream_scl"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="1" LSB="0" MHS_INDEX="37" MSB="1" NAME="util_i2c_mixer_0_downstream_sda_pin" RIGHT="0" SIGNAME="util_i2c_mixer_0_downstream_sda">
      <CONNECTIONS>
        <CONNECTION INSTANCE="util_i2c_mixer_0" PORT="downstream_sda"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" ENDIAN="LITTLE" LEFT="30" LSB="0" MHS_INDEX="38" MSB="30" NAME="processing_system7_0_GPIO_pin" RIGHT="0" SIGNAME="processing_system7_0_GPIO_0">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[GPIO_0]" INSTANCE="processing_system7_0" PORT="GPIO"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="39" NAME="axi_iic_1_Sda_pin" SIGNAME="axi_iic_1_Sda">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_1" PORT="Sda"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" MHS_INDEX="40" NAME="axi_iic_1_Scl_pin" SIGNAME="axi_iic_1_Scl">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_1" PORT="Scl"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="41" NAME="int_1_pin" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="int_1">
      <CONNECTIONS>
        <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="42" NAME="int_2_pin" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="int_2">
      <CONNECTIONS>
        <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="43" NAME="int_3_pin" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="int_3">
      <CONNECTIONS>
        <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="44" NAME="int_4_pin" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="int_4">
      <CONNECTIONS>
        <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="45" NAME="processing_system7_0_SPI0_SCLK_O_pin" SIGIS="CLK" SIGNAME="processing_system7_0_SPI0_SCLK_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[SPI_0]" INSTANCE="processing_system7_0" PORT="SPI0_SCLK_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="46" NAME="processing_system7_0_SPI0_MOSI_O_pin" SIGNAME="processing_system7_0_SPI0_MOSI_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[SPI_0]" INSTANCE="processing_system7_0" PORT="SPI0_MOSI_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="47" NAME="processing_system7_0_SPI0_MISO_I_pin" SIGNAME="processing_system7_0_SPI0_MISO_I">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[SPI_0]" INSTANCE="processing_system7_0" PORT="SPI0_MISO_I"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="48" NAME="processing_system7_0_SPI0_SS_O_pin" SIGNAME="processing_system7_0_SPI0_SS_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[SPI_0]" INSTANCE="processing_system7_0" PORT="SPI0_SS_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="49" NAME="processing_system7_0_SPI1_SCLK_O_pin" SIGIS="CLK" SIGNAME="processing_system7_0_SPI1_SCLK_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[SPI_1]" INSTANCE="processing_system7_0" PORT="SPI1_SCLK_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="50" NAME="processing_system7_0_SPI1_MOSI_O_pin" SIGNAME="processing_system7_0_SPI1_MOSI_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[SPI_1]" INSTANCE="processing_system7_0" PORT="SPI1_MOSI_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" MHS_INDEX="51" NAME="processing_system7_0_SPI1_MISO_I_pin" SIGNAME="processing_system7_0_SPI1_MISO_I">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[SPI_1]" INSTANCE="processing_system7_0" PORT="SPI1_MISO_I"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="52" NAME="processing_system7_0_SPI1_SS_O_pin" SIGNAME="processing_system7_0_SPI1_SS_O">
      <CONNECTIONS>
        <CONNECTION BUSINTERFACE="[SPI_1]" INSTANCE="processing_system7_0" PORT="SPI1_SS_O"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="53" NAME="axi_ad7303_0_cs_o_pin" SIGNAME="axi_ad7303_0_cs_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_ad7303_0" PORT="cs_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="54" NAME="axi_ad7303_0_data0_o_pin" SIGNAME="axi_ad7303_0_data0_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_ad7303_0" PORT="data0_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="55" NAME="axi_ad7303_0_data1_o_pin" SIGNAME="axi_ad7303_0_data1_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_ad7303_0" PORT="data1_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" MHS_INDEX="56" NAME="axi_ad7303_0_sclk_o_pin" SIGNAME="axi_ad7303_0_sclk_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="axi_ad7303_0" PORT="sclk_o"/>
      </CONNECTIONS>
    </PORT>
  </EXTERNALPORTS>

  <MODULES>
    <MODULE HWVERSION="4.02.a" INSTANCE="processing_system7_0" IPTYPE="PROCESSOR" MHS_INDEX="0" MODCLASS="PROCESSOR" MODTYPE="processing_system7" PROCTYPE="ARM">
      <DESCRIPTION TYPE="SHORT">Processing System</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Processing System wrapper for Series 7</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="D:/Xilinx/14.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_02_a/doc/pg082-processing_system7.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="C_EN_EMIO_CAN0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_EN_EMIO_CAN1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_EN_EMIO_ENET0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="3" NAME="C_EN_EMIO_ENET1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="64" MPD_INDEX="4" NAME="C_EN_EMIO_GPIO" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="5" NAME="C_EN_EMIO_I2C0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="6" NAME="C_EN_EMIO_I2C1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="7" NAME="C_EN_EMIO_PJTAG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="8" NAME="C_EN_EMIO_SDIO0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="56" MPD_INDEX="9" NAME="C_EN_EMIO_CD_SDIO0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="57" MPD_INDEX="10" NAME="C_EN_EMIO_WP_SDIO0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="11" NAME="C_EN_EMIO_SDIO1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="58" MPD_INDEX="12" NAME="C_EN_EMIO_CD_SDIO1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="59" MPD_INDEX="13" NAME="C_EN_EMIO_WP_SDIO1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="14" NAME="C_EN_EMIO_SPI0" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="15" NAME="C_EN_EMIO_SPI1" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="16" NAME="C_EN_EMIO_UART0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="17" NAME="C_EN_EMIO_UART1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="18" NAME="C_EN_EMIO_MODEM_UART0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="19" NAME="C_EN_EMIO_MODEM_UART1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="20" NAME="C_EN_EMIO_TTC0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="21" NAME="C_EN_EMIO_TTC1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="22" NAME="C_EN_EMIO_WDT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="23" NAME="C_EN_EMIO_TRACE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="51" MPD_INDEX="24" NAME="C_USE_M_AXI_GP0" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="25" NAME="C_USE_M_AXI_GP1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="26" NAME="C_USE_S_AXI_GP0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="27" NAME="C_USE_S_AXI_GP1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_USE_S_AXI_ACP" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="52" MPD_INDEX="29" NAME="C_USE_S_AXI_HP0" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="63" MPD_INDEX="30" NAME="C_USE_S_AXI_HP1" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="53" MPD_INDEX="31" NAME="C_USE_S_AXI_HP2" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="32" NAME="C_USE_S_AXI_HP3" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="33" NAME="C_S_AXI_GP0_ENABLE_LOWOCM_DDR" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="34" NAME="C_S_AXI_GP1_ENABLE_LOWOCM_DDR" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="35" NAME="C_S_AXI_ACP_ENABLE_HIGHOCM" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="36" NAME="C_S_AXI_HP0_ENABLE_HIGHOCM" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="37" NAME="C_S_AXI_HP1_ENABLE_HIGHOCM" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="38" NAME="C_S_AXI_HP2_ENABLE_HIGHOCM" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="39" NAME="C_S_AXI_HP3_ENABLE_HIGHOCM" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="60" MPD_INDEX="40" NAME="C_USE_DMA0" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="61" MPD_INDEX="41" NAME="C_USE_DMA1" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="62" MPD_INDEX="42" NAME="C_USE_DMA2" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="43" NAME="C_USE_DMA3" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="44" NAME="C_USE_TRACE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="45" NAME="C_INCLUDE_TRACE_BUFFER" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="46" NAME="C_TRACE_BUFFER_FIFO_SIZE" TYPE="INTEGER" VALUE="128"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="47" NAME="USE_TRACE_DATA_EDGE_DETECTOR" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="48" NAME="C_TRACE_BUFFER_CLOCK_DELAY" TYPE="INTEGER" VALUE="12"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="49" NAME="C_USE_CROSS_TRIGGER" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="50" NAME="C_USE_CR_FABRIC" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="51" NAME="C_USE_AXI_FABRIC_IDLE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="52" NAME="C_USE_DDR_BYPASS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="53" NAME="C_USE_FABRIC_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="54" NAME="C_USE_PROC_EVENT_BUS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="55" NAME="C_EN_EMIO_SRAM_INT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="65" MPD_INDEX="56" NAME="C_EMIO_GPIO_WIDTH" TYPE="INTEGER" VALUE="31"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="57" NAME="C_INCLUDE_ACP_TRANS_CHECK" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="58" NAME="C_USE_DEFAULT_ACP_USER_VAL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="59" NAME="C_S_AXI_ACP_ARUSER_VAL" TYPE="INTEGER" VALUE="31"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="60" NAME="C_S_AXI_ACP_AWUSER_VAL" TYPE="INTEGER" VALUE="31"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="61" NAME="C_DQ_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="62" NAME="C_DQS_WIDTH" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="63" NAME="C_DM_WIDTH" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="64" NAME="C_MIO_PRIMITIVE" TYPE="INTEGER" VALUE="54"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="65" NAME="C_PACKAGE_NAME" TYPE="STRING" VALUE="clg484"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="66" NAME="C_PS7_SI_REV" TYPE="STRING" VALUE="PRODUCTION"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="67" NAME="C_UART_BAUD_RATE" TYPE="STRING" VALUE="115200"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" ASSIGNMENT="CONSTANT" MPD_INDEX="68" NAME="C_DDR_RAM_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="69" NAME="C_DDR_RAM_HIGHADDR" TYPE="std_logic_vector" VALUE="0x1FFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_UART0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_UART0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0000FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="72" NAME="C_UART1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0001000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="73" NAME="C_UART1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0001FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="74" NAME="C_I2C0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0004000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="75" NAME="C_I2C0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0004FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="76" NAME="C_I2C1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0005000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="77" NAME="C_I2C1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0005FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="78" NAME="C_SPI0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0006000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="79" NAME="C_SPI0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0006FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="80" NAME="C_SPI1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0007000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="81" NAME="C_SPI1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0007FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="82" NAME="C_CAN0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0008000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="83" NAME="C_CAN0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0008FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="84" NAME="C_CAN1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0009000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="85" NAME="C_CAN1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0009FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="86" NAME="C_GPIO_BASEADDR" TYPE="std_logic_vector" VALUE="0xE000A000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="87" NAME="C_GPIO_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE000AFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="88" NAME="C_ENET0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE000B000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="89" NAME="C_ENET0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE000BFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="90" NAME="C_ENET1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE000C000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="91" NAME="C_ENET1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE000CFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="92" NAME="C_SDIO0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0100000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="93" NAME="C_SDIO0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0100FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="94" NAME="C_SDIO1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0101000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="95" NAME="C_SDIO1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0101FFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="96" NAME="C_USB0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0102000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="97" NAME="C_USB0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0102fff"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="98" NAME="C_USB1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0103000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="99" NAME="C_USB1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0103fff"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="100" NAME="C_TTC0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0104000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="101" NAME="C_TTC0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0104fff"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="102" NAME="C_TTC1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0105000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="103" NAME="C_TTC1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xE0105fff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="104" NAME="C_M_AXI_GP0_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="105" NAME="C_M_AXI_GP0_ID_WIDTH" TYPE="INTEGER" VALUE="12"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="106" NAME="C_M_AXI_GP0_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="107" NAME="C_M_AXI_GP0_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="108" NAME="C_M_AXI_GP0_ENABLE_STATIC_REMAP" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="109" NAME="C_M_AXI_GP0_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="110" NAME="C_M_AXI_GP0_SUPPORTS_REORDERING" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="111" NAME="C_INTERCONNECT_M_AXI_GP0_WRITE_ISSUING" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="112" NAME="C_INTERCONNECT_M_AXI_GP0_READ_ISSUING" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="113" NAME="C_M_AXI_GP1_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="114" NAME="C_M_AXI_GP1_ID_WIDTH" TYPE="INTEGER" VALUE="12"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="115" NAME="C_M_AXI_GP1_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="116" NAME="C_M_AXI_GP1_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="117" NAME="C_M_AXI_GP1_ENABLE_STATIC_REMAP" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="118" NAME="C_M_AXI_GP1_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="119" NAME="C_M_AXI_GP1_SUPPORTS_REORDERING" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="120" NAME="C_INTERCONNECT_M_AXI_GP1_WRITE_ISSUING" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="121" NAME="C_INTERCONNECT_M_AXI_GP1_READ_ISSUING" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="122" NAME="C_S_AXI_GP0_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="123" NAME="C_S_AXI_GP0_ID_WIDTH" TYPE="INTEGER" VALUE="6"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="124" NAME="C_S_AXI_GP0_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="125" NAME="C_S_AXI_GP0_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="126" NAME="C_INTERCONNECT_S_AXI_GP0_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="127" NAME="C_INTERCONNECT_S_AXI_GP0_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="128" NAME="C_S_AXI_GP1_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="129" NAME="C_S_AXI_GP1_ID_WIDTH" TYPE="INTEGER" VALUE="6"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="130" NAME="C_S_AXI_GP1_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="131" NAME="C_S_AXI_GP1_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="132" NAME="C_INTERCONNECT_S_AXI_GP1_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="133" NAME="C_INTERCONNECT_S_AXI_GP1_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="134" NAME="C_S_AXI_ACP_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="135" NAME="C_S_AXI_ACP_ID_WIDTH" TYPE="INTEGER" VALUE="3"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="136" NAME="C_S_AXI_ACP_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="137" NAME="C_S_AXI_ACP_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="138" NAME="C_S_AXI_ACP_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="139" NAME="C_S_AXI_ACP_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="140" NAME="C_S_AXI_ACP_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="141" NAME="C_INTERCONNECT_S_AXI_ACP_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="142" NAME="C_INTERCONNECT_S_AXI_ACP_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="143" NAME="C_S_AXI_HP0_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_S_AXI_HP0_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="145" NAME="C_S_AXI_HP0_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="146" NAME="C_S_AXI_HP0_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="147" NAME="C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="148" NAME="C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="149" NAME="C_S_AXI_HP1_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="150" NAME="C_S_AXI_HP1_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="151" NAME="C_S_AXI_HP1_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="152" NAME="C_S_AXI_HP1_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="153" NAME="C_INTERCONNECT_S_AXI_HP1_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="154" NAME="C_INTERCONNECT_S_AXI_HP1_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="155" NAME="C_S_AXI_HP2_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="156" NAME="C_S_AXI_HP2_ID_WIDTH" TYPE="INTEGER" VALUE="6"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="157" NAME="C_S_AXI_HP2_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="158" NAME="C_S_AXI_HP2_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="159" NAME="C_INTERCONNECT_S_AXI_HP2_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="160" NAME="C_INTERCONNECT_S_AXI_HP2_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="161" NAME="C_S_AXI_HP3_PROTOCOL" TYPE="STRING" VALUE="AXI3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="162" NAME="C_S_AXI_HP3_ID_WIDTH" TYPE="INTEGER" VALUE="6"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="163" NAME="C_S_AXI_HP3_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="164" NAME="C_S_AXI_HP3_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="165" NAME="C_INTERCONNECT_S_AXI_HP3_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="166" NAME="C_INTERCONNECT_S_AXI_HP3_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="167" NAME="C_S_AXI_GP0_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="168" NAME="C_S_AXI_GP0_HIGHADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="169" NAME="C_S_AXI_GP0_LOWOCM_DDR_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="170" NAME="C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="171" NAME="C_S_AXI_GP1_BASEADDR" TYPE="std_logic_vector" VALUE="0xE0000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="172" NAME="C_S_AXI_GP1_HIGHADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="173" NAME="C_S_AXI_GP1_LOWOCM_DDR_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="174" NAME="C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="175" NAME="C_S_AXI_ACP_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="176" NAME="C_S_AXI_ACP_HIGHADDR" TYPE="std_logic_vector" VALUE="0x3FFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="177" NAME="C_S_AXI_ACP_HIGHOCM_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFC0000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="178" NAME="C_S_AXI_ACP_HIGHOCM_HIGHADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="179" NAME="C_S_AXI_HP0_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="180" NAME="C_S_AXI_HP0_HIGHADDR" TYPE="std_logic_vector" VALUE="0x1FFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="181" NAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFC0000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="182" NAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="183" NAME="C_S_AXI_HP1_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="184" NAME="C_S_AXI_HP1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x1FFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="185" NAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFC0000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="186" NAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="187" NAME="C_S_AXI_HP2_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="188" NAME="C_S_AXI_HP2_HIGHADDR" TYPE="std_logic_vector" VALUE="0x1FFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="189" NAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFC0000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="190" NAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="191" NAME="C_S_AXI_HP3_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="192" NAME="C_S_AXI_HP3_HIGHADDR" TYPE="std_logic_vector" VALUE="0x1FFFFFFF"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="193" NAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFC0000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="CONSTANT" MPD_INDEX="194" NAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="195" NAME="C_M_AXI_GP0_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="196" NAME="C_M_AXI_GP0_THREAD_ID_WIDTH" VALUE="12"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="197" NAME="C_M_AXI_GP1_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="198" NAME="C_M_AXI_GP1_THREAD_ID_WIDTH" VALUE="12"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="199" NAME="C_NUM_F2P_INTR_INPUTS" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="46" MPD_INDEX="200" NAME="C_EN_DDR" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="201" NAME="C_EN_SMC" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="202" NAME="C_EN_QSPI" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="25" MPD_INDEX="203" NAME="C_EN_CAN0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="204" NAME="C_EN_CAN1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="27" MPD_INDEX="205" NAME="C_EN_ENET0" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="28" MPD_INDEX="206" NAME="C_EN_ENET1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="55" MPD_INDEX="207" NAME="C_EN_GPIO" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="208" NAME="C_EN_I2C0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="209" NAME="C_EN_I2C1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="210" NAME="C_EN_PJTAG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="211" NAME="C_EN_SDIO0" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="212" NAME="C_EN_SDIO1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="34" MPD_INDEX="213" NAME="C_EN_SPI0" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="35" MPD_INDEX="214" NAME="C_EN_SPI1" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="39" MPD_INDEX="215" NAME="C_EN_UART0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="40" MPD_INDEX="216" NAME="C_EN_UART1" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="41" MPD_INDEX="217" NAME="C_EN_MODEM_UART0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="42" MPD_INDEX="218" NAME="C_EN_MODEM_UART1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="37" MPD_INDEX="219" NAME="C_EN_TTC0" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="220" NAME="C_EN_TTC1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="45" MPD_INDEX="221" NAME="C_EN_WDT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="36" MPD_INDEX="222" NAME="C_EN_TRACE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="43" MPD_INDEX="223" NAME="C_EN_USB0" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="44" MPD_INDEX="224" NAME="C_EN_USB1" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="225" NAME="C_EN_4K_TIMER" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="47" MPD_INDEX="226" NAME="C_FCLK_CLK0_FREQ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="48" MPD_INDEX="227" NAME="C_FCLK_CLK1_FREQ" TYPE="INTEGER" VALUE="142857132"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="49" MPD_INDEX="228" NAME="C_FCLK_CLK2_FREQ" TYPE="INTEGER" VALUE="200000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="50" MPD_INDEX="229" NAME="C_FCLK_CLK3_FREQ" TYPE="INTEGER" VALUE="12500000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="230" NAME="C_FCLK_CLK0_BUF" TYPE="STRING" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="231" NAME="C_FCLK_CLK1_BUF" TYPE="STRING" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="232" NAME="C_FCLK_CLK2_BUF" TYPE="STRING" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="233" NAME="C_FCLK_CLK3_BUF" TYPE="STRING" VALUE="TRUE"/>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="54" NAME="C_INTERCONNECT_S_AXI_HP2_MASTERS" VALUE="axi_dma_i2s.M_AXI_MM2S &amp; axi_dma_i2s.M_AXI_SG &amp; axi_dma_i2s.M_AXI_S2MM"/>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="66" NAME="C_INTERCONNECT_S_AXI_HP0_MASTERS" VALUE="axi_vdma_0.M_AXI_MM2S"/>
        <PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="67" NAME="C_INTERCONNECT_S_AXI_HP1_MASTERS" VALUE="axi_vdma_1.M_AXI_MM2S"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="PS_REQUIRED_EXTERNAL_IO" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="53" LSB="0" MHS_INDEX="0" MPD_INDEX="623" MSB="53" NAME="MIO" RIGHT="0" SIGNAME="processing_system7_0_MIO" VECFORMULA="[C_MIO_PRIMITIVE - 1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_MIO"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="PS_REQUIRED_EXTERNAL_IO" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="641" NAME="PS_SRSTB" SIGNAME="processing_system7_0_PS_SRSTB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_PS_SRSTB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="PS_REQUIRED_EXTERNAL_IO" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="642" NAME="PS_CLK" SIGIS="CLK" SIGNAME="processing_system7_0_PS_CLK">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_PS_CLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="PS_REQUIRED_EXTERNAL_IO" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="643" NAME="PS_PORB" SIGNAME="processing_system7_0_PS_PORB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_PS_PORB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="4" MPD_INDEX="624" NAME="DDR_Clk" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_Clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="5" MPD_INDEX="625" NAME="DDR_Clk_n" SIGIS="CLK" SIGNAME="processing_system7_0_DDR_Clk_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_Clk_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="6" MPD_INDEX="626" NAME="DDR_CKE" SIGNAME="processing_system7_0_DDR_CKE">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_CKE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="7" MPD_INDEX="627" NAME="DDR_CS_n" SIGNAME="processing_system7_0_DDR_CS_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_CS_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="8" MPD_INDEX="628" NAME="DDR_RAS_n" SIGNAME="processing_system7_0_DDR_RAS_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_RAS_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="9" MPD_INDEX="629" NAME="DDR_CAS_n" SIGNAME="processing_system7_0_DDR_CAS_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_CAS_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="630" NAME="DDR_WEB" SIGNAME="processing_system7_0_DDR_WEB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_WEB_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="2" LSB="0" MHS_INDEX="11" MPD_INDEX="631" MSB="2" NAME="DDR_BankAddr" RIGHT="0" SIGNAME="processing_system7_0_DDR_BankAddr" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_BankAddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="14" LSB="0" MHS_INDEX="12" MPD_INDEX="632" MSB="14" NAME="DDR_Addr" RIGHT="0" SIGNAME="processing_system7_0_DDR_Addr" VECFORMULA="[14:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_Addr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="13" MPD_INDEX="633" NAME="DDR_ODT" SIGNAME="processing_system7_0_DDR_ODT">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_ODT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="14" MPD_INDEX="634" NAME="DDR_DRSTB" SIGIS="RST" SIGNAME="processing_system7_0_DDR_DRSTB">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_DRSTB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="31" LSB="0" MHS_INDEX="15" MPD_INDEX="635" MSB="31" NAME="DDR_DQ" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQ" VECFORMULA="[C_DQ_WIDTH - 1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_DQ"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MHS_INDEX="16" MPD_INDEX="636" MSB="3" NAME="DDR_DM" RIGHT="0" SIGNAME="processing_system7_0_DDR_DM" VECFORMULA="[C_DM_WIDTH - 1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_DM"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MHS_INDEX="17" MPD_INDEX="637" MSB="3" NAME="DDR_DQS" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS" VECFORMULA="[C_DQS_WIDTH - 1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_DQS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="3" LSB="0" MHS_INDEX="18" MPD_INDEX="638" MSB="3" NAME="DDR_DQS_n" RIGHT="0" SIGNAME="processing_system7_0_DDR_DQS_n" VECFORMULA="[C_DQS_WIDTH - 1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_DQS_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="19" MPD_INDEX="639" NAME="DDR_VRN" SIGNAME="processing_system7_0_DDR_VRN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_VRN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="MEMORY_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="20" MPD_INDEX="640" NAME="DDR_VRP" SIGNAME="processing_system7_0_DDR_VRP">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_DDR_VRP"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="603" NAME="FCLK_CLK0" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ACLK"/>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_ACLK"/>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_ACLK"/>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_aclk"/>
            <CONNECTION BUSINTERFACE="[S_AXI_CTRL]" INSTANCE="axi_interconnect_1" PORT="INTERCONNECT_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_ACLK"/>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_aclk"/>
            <CONNECTION INSTANCE="axi_ad7303_0" PORT="ref_clk"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_aclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="142857132" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="602" NAME="FCLK_CLK1" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ACLK"/>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ACLK"/>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_aclk"/>
            <CONNECTION INSTANCE="axi_vdma_0" PORT="m_axis_mm2s_aclk"/>
            <CONNECTION BUSINTERFACE="[S_AXI_CTRL]" INSTANCE="axi_interconnect_2" PORT="INTERCONNECT_ACLK"/>
            <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="vdma_clk"/>
            <CONNECTION BUSINTERFACE="[S_AXI_CTRL]" INSTANCE="axi_interconnect_3" PORT="INTERCONNECT_ACLK"/>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_aclk"/>
            <CONNECTION INSTANCE="axi_vdma_1" PORT="m_axis_mm2s_aclk"/>
            <CONNECTION INSTANCE="axi_ad7303_0" PORT="m_axis_mm2s_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="200000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="601" NAME="FCLK_CLK2" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_clkgen_0" PORT="ref_clk"/>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKIN"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="12500000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="600" NAME="FCLK_CLK3" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_ad7303_0" PORT="tx_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="25" MPD_INDEX="611" NAME="FCLK_RESET0_N" SIGIS="RST" SIGNAME="processing_system7_0_FCLK_RESET0_N">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="INTERCONNECT_ARESETN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="610" NAME="FCLK_RESET1_N" SIGIS="RST" SIGNAME="processing_system7_0_FCLK_RESET1_N">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="INTERCONNECT_ARESETN"/>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="INTERCONNECT_ARESETN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="27" MPD_INDEX="196" NAME="M_AXI_GP0_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" CLKFREQUENCY="142857132" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="28" MPD_INDEX="386" NAME="S_AXI_HP0_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" CLKFREQUENCY="142857132" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="432" NAME="S_AXI_HP1_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="30" MPD_INDEX="614" MSB="7" NAME="IRQ_F2P" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="axi_vdma_0_mm2s_introut &amp; axi_vdma_1_mm2s_introut &amp; axi_iic_0_IIC2INTC_Irpt &amp; axi_iic_1_IIC2INTC_Irpt &amp; int_1 &amp; int_2 &amp; int_3 &amp; int_4" VECFORMULA="[(C_NUM_F2P_INTR_INPUTS-1) :0]">
          <SIGNALS>
            <SIGNAL NAME="axi_vdma_0_mm2s_introut"/>
            <SIGNAL NAME="axi_vdma_1_mm2s_introut"/>
            <SIGNAL NAME="axi_iic_0_IIC2INTC_Irpt"/>
            <SIGNAL NAME="axi_iic_1_IIC2INTC_Irpt"/>
            <SIGNAL NAME="int_1"/>
            <SIGNAL NAME="int_2"/>
            <SIGNAL NAME="int_3"/>
            <SIGNAL NAME="int_4"/>
          </SIGNALS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_vdma_0_mm2s_introut &amp; axi_vdma_1_mm2s_introut &amp; axi_iic_0_IIC2INTC_Irpt &amp; axi_iic_1_IIC2INTC_Irpt &amp; int_1 &amp; int_2 &amp; int_3 &amp; int_4"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="USBIND_0" IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="165" NAME="USB0_VBUS_PWRFAULT" SIGNAME="util_vector_logic_0_Res">
          <CONNECTIONS>
            <CONNECTION INSTANCE="util_vector_logic_0" PORT="Res"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="32" MPD_INDEX="558" NAME="DMA0_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="557" NAME="DMA0_RSTN" SIGNAME="processing_system7_0_DMA0_RSTN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_RSTN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="34" MPD_INDEX="554" MSB="1" NAME="DMA0_DATYPE" RIGHT="0" SIGNAME="processing_system7_0_DMA0_DATYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_DATYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="35" MPD_INDEX="555" NAME="DMA0_DAVALID" SIGNAME="processing_system7_0_DMA0_DAVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_DAVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="36" MPD_INDEX="556" NAME="DMA0_DRREADY" SIGNAME="processing_system7_0_DMA0_DRREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_DRREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="37" MPD_INDEX="559" NAME="DMA0_DAREADY" SIGNAME="axi_spdif_tx_0_DMA_REQ_DAREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_DAREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="38" MPD_INDEX="560" NAME="DMA0_DRLAST" SIGNAME="axi_spdif_tx_0_DMA_REQ_DRLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_DRLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="39" MPD_INDEX="562" MSB="1" NAME="DMA0_DRTYPE" RIGHT="0" SIGNAME="axi_spdif_tx_0_DMA_REQ_DRTYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_DRTYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA0_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="40" MPD_INDEX="561" NAME="DMA0_DRVALID" SIGNAME="axi_spdif_tx_0_DMA_REQ_DRVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ]" INSTANCE="axi_spdif_tx_0" PORT="DMA_REQ_DRVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="41" MPD_INDEX="567" NAME="DMA1_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="42" MPD_INDEX="564" NAME="DMA1_DAVALID" SIGNAME="processing_system7_0_DMA1_DAVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_DAVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="43" MPD_INDEX="563" MSB="1" NAME="DMA1_DATYPE" RIGHT="0" SIGNAME="processing_system7_0_DMA1_DATYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_DATYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="44" MPD_INDEX="565" NAME="DMA1_DRREADY" SIGNAME="processing_system7_0_DMA1_DRREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_DRREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="45" MPD_INDEX="566" NAME="DMA1_RSTN" SIGNAME="processing_system7_0_DMA1_RSTN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_RSTN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="46" MPD_INDEX="570" NAME="DMA1_DRVALID" SIGNAME="axi_i2s_adi_0_DMA_REQ_TX_DRVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_DRVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="47" MPD_INDEX="571" MSB="1" NAME="DMA1_DRTYPE" RIGHT="0" SIGNAME="axi_i2s_adi_0_DMA_REQ_TX_DRTYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_DRTYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="48" MPD_INDEX="568" NAME="DMA1_DAREADY" SIGNAME="axi_i2s_adi_0_DMA_REQ_TX_DAREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_DAREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA1_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="49" MPD_INDEX="569" NAME="DMA1_DRLAST" SIGNAME="axi_i2s_adi_0_DMA_REQ_TX_DRLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_TX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_TX_DRLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="50" MPD_INDEX="572" MSB="1" NAME="DMA2_DATYPE" RIGHT="0" SIGNAME="processing_system7_0_DMA2_DATYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_DATYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="51" MPD_INDEX="576" NAME="DMA2_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="52" MPD_INDEX="573" NAME="DMA2_DAVALID" SIGNAME="processing_system7_0_DMA2_DAVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_DAVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="53" MPD_INDEX="574" NAME="DMA2_DRREADY" SIGNAME="processing_system7_0_DMA2_DRREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_DRREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="54" MPD_INDEX="575" NAME="DMA2_RSTN" SIGNAME="processing_system7_0_DMA2_RSTN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_RSTN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="55" MPD_INDEX="578" NAME="DMA2_DRLAST" SIGNAME="axi_i2s_adi_0_DMA_REQ_RX_DRLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_DRLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="56" MPD_INDEX="579" NAME="DMA2_DRVALID" SIGNAME="axi_i2s_adi_0_DMA_REQ_RX_DRVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_DRVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="57" MPD_INDEX="588" MSB="1" NAME="DMA2_DRTYPE" RIGHT="0" SIGNAME="axi_i2s_adi_0_DMA_REQ_RX_DRTYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_DRTYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA2_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="58" MPD_INDEX="577" NAME="DMA2_DAREADY" SIGNAME="axi_i2s_adi_0_DMA_REQ_RX_DAREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA_REQ_RX]" INSTANCE="axi_i2s_adi_0" PORT="DMA_REQ_RX_DAREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="GPIO_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="30" LSB="0" MHS_INDEX="59" MPD_INDEX="675" MSB="30" NAME="GPIO" RIGHT="0" SIGNAME="processing_system7_0_GPIO_0" TRI_I="GPIO_I" TRI_O="GPIO_O" TRI_T="GPIO_T" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_GPIO_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="SPI_0" IS_INSTANTIATED="TRUE" MHS_INDEX="60" MPD_INDEX="101" NAME="SPI0_SCLK_O" SIGIS="CLK" SIGNAME="processing_system7_0_SPI0_SCLK_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_SPI0_SCLK_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="SPI_0" IS_INSTANTIATED="TRUE" MHS_INDEX="61" MPD_INDEX="104" NAME="SPI0_MOSI_O" SIGNAME="processing_system7_0_SPI0_MOSI_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_SPI0_MOSI_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="SPI_0" IS_INSTANTIATED="TRUE" MHS_INDEX="62" MPD_INDEX="106" NAME="SPI0_MISO_I" SIGNAME="processing_system7_0_SPI0_MISO_I">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_SPI0_MISO_I_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="SPI_0" IS_INSTANTIATED="TRUE" MHS_INDEX="63" MPD_INDEX="110" NAME="SPI0_SS_O" SIGNAME="processing_system7_0_SPI0_SS_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_SPI0_SS_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="SPI_0" IS_INSTANTIATED="TRUE" MHS_INDEX="64" MPD_INDEX="109" NAME="SPI0_SS_I" SIGNAME="net_vcc">
          <CONNECTIONS>
            <CONNECTION INSTANCE="net_vcc"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="SPI_1" IS_INSTANTIATED="TRUE" MHS_INDEX="65" MPD_INDEX="115" NAME="SPI1_SCLK_O" SIGIS="CLK" SIGNAME="processing_system7_0_SPI1_SCLK_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_SPI1_SCLK_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="SPI_1" IS_INSTANTIATED="TRUE" MHS_INDEX="66" MPD_INDEX="118" NAME="SPI1_MOSI_O" SIGNAME="processing_system7_0_SPI1_MOSI_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_SPI1_MOSI_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="SPI_1" IS_INSTANTIATED="TRUE" MHS_INDEX="67" MPD_INDEX="120" NAME="SPI1_MISO_I" SIGNAME="processing_system7_0_SPI1_MISO_I">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_SPI1_MISO_I_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="SPI_1" IS_INSTANTIATED="TRUE" MHS_INDEX="68" MPD_INDEX="124" NAME="SPI1_SS_O" SIGNAME="processing_system7_0_SPI1_SS_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="processing_system7_0_SPI1_SS_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="SPI_1" IS_INSTANTIATED="TRUE" MHS_INDEX="69" MPD_INDEX="123" NAME="SPI1_SS_I" SIGNAME="net_vcc">
          <CONNECTIONS>
            <CONNECTION INSTANCE="net_vcc"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="CAN_0" IS_VALID="FALSE" MPD_INDEX="0" NAME="CAN0_PHY_TX" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="CAN_0" IS_VALID="FALSE" MPD_INDEX="1" NAME="CAN0_PHY_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="CAN_1" IS_VALID="FALSE" MPD_INDEX="2" NAME="CAN1_PHY_TX" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="CAN_1" IS_VALID="FALSE" MPD_INDEX="3" NAME="CAN1_PHY_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="4" NAME="ENET0_GMII_TX_EN" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="5" NAME="ENET0_GMII_TX_ER" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="6" NAME="ENET0_MDIO_MDC" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="7" NAME="ENET0_MDIO_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="8" NAME="ENET0_MDIO_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="9" NAME="ENET0_PTP_DELAY_REQ_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="10" NAME="ENET0_PTP_DELAY_REQ_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="11" NAME="ENET0_PTP_PDELAY_REQ_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="12" NAME="ENET0_PTP_PDELAY_REQ_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="13" NAME="ENET0_PTP_PDELAY_RESP_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="14" NAME="ENET0_PTP_PDELAY_RESP_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="15" NAME="ENET0_PTP_SYNC_FRAME_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="16" NAME="ENET0_PTP_SYNC_FRAME_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="17" NAME="ENET0_SOF_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="18" NAME="ENET0_SOF_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="ETHERNETIF_0" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="ENET0_GMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="20" NAME="ENET0_GMII_COL" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="21" NAME="ENET0_GMII_CRS" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="22" NAME="ENET0_EXT_INTIN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="23" NAME="ENET0_GMII_RX_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="24" NAME="ENET0_GMII_RX_DV" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="25" NAME="ENET0_GMII_RX_ER" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="26" NAME="ENET0_GMII_TX_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_0" IS_VALID="FALSE" MPD_INDEX="27" NAME="ENET0_MDIO_I" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="ETHERNETIF_0" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="28" MSB="7" NAME="ENET0_GMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="29" NAME="ENET1_GMII_TX_EN" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="30" NAME="ENET1_GMII_TX_ER" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="31" NAME="ENET1_MDIO_MDC" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="32" NAME="ENET1_MDIO_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="33" NAME="ENET1_MDIO_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="34" NAME="ENET1_PTP_DELAY_REQ_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="35" NAME="ENET1_PTP_DELAY_REQ_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="36" NAME="ENET1_PTP_PDELAY_REQ_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="37" NAME="ENET1_PTP_PDELAY_REQ_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="38" NAME="ENET1_PTP_PDELAY_RESP_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="39" NAME="ENET1_PTP_PDELAY_RESP_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="40" NAME="ENET1_PTP_SYNC_FRAME_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="41" NAME="ENET1_PTP_SYNC_FRAME_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="42" NAME="ENET1_SOF_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="43" NAME="ENET1_SOF_TX" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="ETHERNETIF_1" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="44" MSB="7" NAME="ENET1_GMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="45" NAME="ENET1_GMII_COL" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="46" NAME="ENET1_GMII_CRS" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="47" NAME="ENET1_EXT_INTIN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="48" NAME="ENET1_GMII_RX_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="49" NAME="ENET1_GMII_RX_DV" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="50" NAME="ENET1_GMII_RX_ER" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="51" NAME="ENET1_GMII_TX_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="ETHERNETIF_1" IS_VALID="FALSE" MPD_INDEX="52" NAME="ENET1_MDIO_I" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="ETHERNETIF_1" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="53" MSB="7" NAME="ENET1_GMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="GPIO_0" LEFT="30" LSB="0" MPD_INDEX="54" MSB="30" NAME="GPIO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="GPIO_0" LEFT="30" LSB="0" MPD_INDEX="55" MSB="30" NAME="GPIO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="GPIO_0" LEFT="30" LSB="0" MPD_INDEX="56" MSB="30" NAME="GPIO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_EMIO_GPIO_WIDTH-1):0]"/>
        <PORT DIR="I" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="57" NAME="I2C0_SDA_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="58" NAME="I2C0_SDA_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="59" NAME="I2C0_SDA_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="60" NAME="I2C0_SCL_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="61" NAME="I2C0_SCL_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="IIC_0" IS_VALID="FALSE" MPD_INDEX="62" NAME="I2C0_SCL_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="63" NAME="I2C1_SDA_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="64" NAME="I2C1_SDA_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="65" NAME="I2C1_SDA_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="66" NAME="I2C1_SCL_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="67" NAME="I2C1_SCL_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="IIC_1" IS_VALID="FALSE" MPD_INDEX="68" NAME="I2C1_SCL_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="69" NAME="PJTAG_TCK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="70" NAME="PJTAG_TMS" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="71" NAME="PJTAG_TD_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="72" NAME="PJTAG_TD_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="PJTAG" IS_VALID="FALSE" MPD_INDEX="73" NAME="PJTAG_TD_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="74" NAME="SDIO0_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="75" NAME="SDIO0_CLK_FB" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="76" NAME="SDIO0_CMD_O" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="77" NAME="SDIO0_CMD_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="78" NAME="SDIO0_CMD_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="SDIO0_DATA_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="SDIO0_DATA_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="SDIO0_DATA_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="82" NAME="SDIO0_LED" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="83" NAME="SDIO0_CDN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="84" NAME="SDIO0_WP" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SDIO_0" IS_VALID="FALSE" MPD_INDEX="85" NAME="SDIO0_BUSPOW" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_0" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="86" MSB="2" NAME="SDIO0_BUSVOLT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="87" NAME="SDIO1_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="88" NAME="SDIO1_CLK_FB" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="89" NAME="SDIO1_CMD_O" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="90" NAME="SDIO1_CMD_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="91" NAME="SDIO1_CMD_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="92" MSB="3" NAME="SDIO1_DATA_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="SDIO1_DATA_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="94" MSB="3" NAME="SDIO1_DATA_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="95" NAME="SDIO1_LED" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="96" NAME="SDIO1_CDN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="97" NAME="SDIO1_WP" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SDIO_1" IS_VALID="FALSE" MPD_INDEX="98" NAME="SDIO1_BUSPOW" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="SDIO_1" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="99" MSB="2" NAME="SDIO1_BUSVOLT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT DIR="I" IOS="SPI_0" MPD_INDEX="100" NAME="SPI0_SCLK_I" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_0" MPD_INDEX="102" NAME="SPI0_SCLK_T" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SPI_0" MPD_INDEX="103" NAME="SPI0_MOSI_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_0" MPD_INDEX="105" NAME="SPI0_MOSI_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_0" MPD_INDEX="107" NAME="SPI0_MISO_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_0" MPD_INDEX="108" NAME="SPI0_MISO_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_0" MPD_INDEX="111" NAME="SPI0_SS1_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_0" MPD_INDEX="112" NAME="SPI0_SS2_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_0" MPD_INDEX="113" NAME="SPI0_SS_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SPI_1" MPD_INDEX="114" NAME="SPI1_SCLK_I" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_1" MPD_INDEX="116" NAME="SPI1_SCLK_T" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="SPI_1" MPD_INDEX="117" NAME="SPI1_MOSI_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_1" MPD_INDEX="119" NAME="SPI1_MOSI_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_1" MPD_INDEX="121" NAME="SPI1_MISO_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_1" MPD_INDEX="122" NAME="SPI1_MISO_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_1" MPD_INDEX="125" NAME="SPI1_SS1_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_1" MPD_INDEX="126" NAME="SPI1_SS2_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="SPI_1" MPD_INDEX="127" NAME="SPI1_SS_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="128" NAME="UART0_DTRN" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="129" NAME="UART0_RTSN" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="130" NAME="UART0_TX" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="131" NAME="UART0_CTSN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="132" NAME="UART0_DCDN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="133" NAME="UART0_DSRN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="134" NAME="UART0_RIN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_0" IS_VALID="FALSE" MPD_INDEX="135" NAME="UART0_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="136" NAME="UART1_DTRN" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="137" NAME="UART1_RTSN" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="138" NAME="UART1_TX" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="139" NAME="UART1_CTSN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="140" NAME="UART1_DCDN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="141" NAME="UART1_DSRN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="142" NAME="UART1_RIN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="UART_1" IS_VALID="FALSE" MPD_INDEX="143" NAME="UART1_RX" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="144" NAME="TTC0_WAVE0_OUT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="145" NAME="TTC0_WAVE1_OUT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="146" NAME="TTC0_WAVE2_OUT" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="147" NAME="TTC0_CLK0_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="148" NAME="TTC0_CLK1_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="TTC_0" IS_VALID="FALSE" MPD_INDEX="149" NAME="TTC0_CLK2_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="150" NAME="TTC1_WAVE0_OUT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="151" NAME="TTC1_WAVE1_OUT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="152" NAME="TTC1_WAVE2_OUT" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="153" NAME="TTC1_CLK0_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="154" NAME="TTC1_CLK1_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="TTC_1" IS_VALID="FALSE" MPD_INDEX="155" NAME="TTC1_CLK2_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="WDT_0" IS_VALID="FALSE" MPD_INDEX="156" NAME="WDT_CLK_IN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="WDT_0" IS_VALID="FALSE" MPD_INDEX="157" NAME="WDT_RST_OUT" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="TRACE_0" IS_VALID="FALSE" MPD_INDEX="158" NAME="TRACE_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="TRACE_0" IS_VALID="FALSE" MPD_INDEX="159" NAME="TRACE_CTL" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="TRACE_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="160" MSB="31" NAME="TRACE_DATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="USBIND_0" LEFT="1" LSB="0" MPD_INDEX="161" MSB="1" NAME="USB0_PORT_INDCTL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="USBIND_1" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="162" MSB="1" NAME="USB1_PORT_INDCTL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT DIR="O" IOS="USBIND_0" MPD_INDEX="163" NAME="USB0_VBUS_PWRSELECT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="USBIND_1" IS_VALID="FALSE" MPD_INDEX="164" NAME="USB1_VBUS_PWRSELECT" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="USBIND_1" IS_VALID="FALSE" MPD_INDEX="166" NAME="USB1_VBUS_PWRFAULT" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="167" NAME="SRAM_INTIN" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="168" NAME="M_AXI_GP0_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARVALID" DIR="O" MPD_INDEX="169" NAME="M_AXI_GP0_ARVALID" SIGNAME="axi_interconnect_1_S_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWVALID" DIR="O" MPD_INDEX="170" NAME="M_AXI_GP0_AWVALID" SIGNAME="axi_interconnect_1_S_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_BREADY" DIR="O" MPD_INDEX="171" NAME="M_AXI_GP0_BREADY" SIGNAME="axi_interconnect_1_S_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_RREADY" DIR="O" MPD_INDEX="172" NAME="M_AXI_GP0_RREADY" SIGNAME="axi_interconnect_1_S_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_WLAST" DIR="O" MPD_INDEX="173" NAME="M_AXI_GP0_WLAST" SIGNAME="axi_interconnect_1_S_WLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_WVALID" DIR="O" MPD_INDEX="174" NAME="M_AXI_GP0_WVALID" SIGNAME="axi_interconnect_1_S_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="175" MSB="11" NAME="M_AXI_GP0_ARID" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARID" VECFORMULA="[C_M_AXI_GP0_THREAD_ID_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="176" MSB="11" NAME="M_AXI_GP0_AWID" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWID" VECFORMULA="[C_M_AXI_GP0_THREAD_ID_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_WID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="177" MSB="11" NAME="M_AXI_GP0_WID" RIGHT="0" SIGNAME="axi_interconnect_1_S_WID" VECFORMULA="[C_M_AXI_GP0_THREAD_ID_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_WID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="178" MSB="1" NAME="M_AXI_GP0_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="179" MSB="1" NAME="M_AXI_GP0_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARLOCK" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="180" MSB="2" NAME="M_AXI_GP0_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="181" MSB="1" NAME="M_AXI_GP0_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="182" MSB="1" NAME="M_AXI_GP0_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWLOCK" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="183" MSB="2" NAME="M_AXI_GP0_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="184" MSB="2" NAME="M_AXI_GP0_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="185" MSB="2" NAME="M_AXI_GP0_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="M_AXI_GP0_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARADDR" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="187" MSB="31" NAME="M_AXI_GP0_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWADDR" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="M_AXI_GP0_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_S_WDATA" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="189" MSB="3" NAME="M_AXI_GP0_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="190" MSB="3" NAME="M_AXI_GP0_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARLEN" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="191" MSB="3" NAME="M_AXI_GP0_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARQOS" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="192" MSB="3" NAME="M_AXI_GP0_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="193" MSB="3" NAME="M_AXI_GP0_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWLEN" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="194" MSB="3" NAME="M_AXI_GP0_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWQOS" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="195" MSB="3" NAME="M_AXI_GP0_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_S_WSTRB" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_ARREADY" DIR="I" MPD_INDEX="197" NAME="M_AXI_GP0_ARREADY" SIGNAME="axi_interconnect_1_S_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_AWREADY" DIR="I" MPD_INDEX="198" NAME="M_AXI_GP0_AWREADY" SIGNAME="axi_interconnect_1_S_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_BVALID" DIR="I" MPD_INDEX="199" NAME="M_AXI_GP0_BVALID" SIGNAME="axi_interconnect_1_S_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_RLAST" DIR="I" MPD_INDEX="200" NAME="M_AXI_GP0_RLAST" SIGNAME="axi_interconnect_1_S_RLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_RVALID" DIR="I" MPD_INDEX="201" NAME="M_AXI_GP0_RVALID" SIGNAME="axi_interconnect_1_S_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_WREADY" DIR="I" MPD_INDEX="202" NAME="M_AXI_GP0_WREADY" SIGNAME="axi_interconnect_1_S_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_BID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="203" MSB="11" NAME="M_AXI_GP0_BID" RIGHT="0" SIGNAME="axi_interconnect_1_S_BID" VECFORMULA="[C_M_AXI_GP0_THREAD_ID_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_RID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="204" MSB="11" NAME="M_AXI_GP0_RID" RIGHT="0" SIGNAME="axi_interconnect_1_S_RID" VECFORMULA="[C_M_AXI_GP0_THREAD_ID_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="205" MSB="1" NAME="M_AXI_GP0_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_S_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="206" MSB="1" NAME="M_AXI_GP0_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_S_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_GP0" DEF_SIGNAME="axi_interconnect_1_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="207" MSB="31" NAME="M_AXI_GP0_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_S_RDATA" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="S_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="208" NAME="M_AXI_GP1_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="209" NAME="M_AXI_GP1_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="210" NAME="M_AXI_GP1_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="211" NAME="M_AXI_GP1_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="212" NAME="M_AXI_GP1_RREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="213" NAME="M_AXI_GP1_WLAST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="214" NAME="M_AXI_GP1_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="11" LSB="0" MPD_INDEX="215" MSB="11" NAME="M_AXI_GP1_ARID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_GP1_THREAD_ID_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="11" LSB="0" MPD_INDEX="216" MSB="11" NAME="M_AXI_GP1_AWID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_GP1_THREAD_ID_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="11" LSB="0" MPD_INDEX="217" MSB="11" NAME="M_AXI_GP1_WID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_GP1_THREAD_ID_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="218" MSB="1" NAME="M_AXI_GP1_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="219" MSB="1" NAME="M_AXI_GP1_ARLOCK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="220" MSB="2" NAME="M_AXI_GP1_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="221" MSB="1" NAME="M_AXI_GP1_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="222" MSB="1" NAME="M_AXI_GP1_AWLOCK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="223" MSB="2" NAME="M_AXI_GP1_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="224" MSB="2" NAME="M_AXI_GP1_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="225" MSB="2" NAME="M_AXI_GP1_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="226" MSB="31" NAME="M_AXI_GP1_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="227" MSB="31" NAME="M_AXI_GP1_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="228" MSB="31" NAME="M_AXI_GP1_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="229" MSB="3" NAME="M_AXI_GP1_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="230" MSB="3" NAME="M_AXI_GP1_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="231" MSB="3" NAME="M_AXI_GP1_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="232" MSB="3" NAME="M_AXI_GP1_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="233" MSB="3" NAME="M_AXI_GP1_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="234" MSB="3" NAME="M_AXI_GP1_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="M_AXI_GP1_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="236" NAME="M_AXI_GP1_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="237" NAME="M_AXI_GP1_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="238" NAME="M_AXI_GP1_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="239" NAME="M_AXI_GP1_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="240" NAME="M_AXI_GP1_RLAST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="241" NAME="M_AXI_GP1_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_GP1" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="242" NAME="M_AXI_GP1_WREADY" SIGNAME="__NOC__"/>
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        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="336" MSB="1" NAME="S_AXI_ACP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="337" MSB="2" NAME="S_AXI_ACP_BID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ACP_ID_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="338" MSB="2" NAME="S_AXI_ACP_RID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ACP_ID_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="339" MSB="63" NAME="S_AXI_ACP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="340" NAME="S_AXI_ACP_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="341" NAME="S_AXI_ACP_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="342" NAME="S_AXI_ACP_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="343" NAME="S_AXI_ACP_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="344" NAME="S_AXI_ACP_RREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="345" NAME="S_AXI_ACP_WLAST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="346" NAME="S_AXI_ACP_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="347" MSB="2" NAME="S_AXI_ACP_ARID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ACP_ID_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="348" MSB="2" NAME="S_AXI_ACP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="349" MSB="2" NAME="S_AXI_ACP_AWID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ACP_ID_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="350" MSB="2" NAME="S_AXI_ACP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="351" MSB="2" NAME="S_AXI_ACP_WID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_ACP_ID_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="352" MSB="31" NAME="S_AXI_ACP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="353" MSB="31" NAME="S_AXI_ACP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="354" MSB="3" NAME="S_AXI_ACP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="355" MSB="3" NAME="S_AXI_ACP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="356" MSB="3" NAME="S_AXI_ACP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="357" MSB="3" NAME="S_AXI_ACP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="358" MSB="3" NAME="S_AXI_ACP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="359" MSB="3" NAME="S_AXI_ACP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="360" MSB="1" NAME="S_AXI_ACP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="361" MSB="1" NAME="S_AXI_ACP_ARLOCK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="362" MSB="2" NAME="S_AXI_ACP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="363" MSB="1" NAME="S_AXI_ACP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="364" MSB="1" NAME="S_AXI_ACP_AWLOCK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="2" LSB="0" MPD_INDEX="365" MSB="2" NAME="S_AXI_ACP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="366" MSB="4" NAME="S_AXI_ACP_ARUSER" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[4:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="367" MSB="4" NAME="S_AXI_ACP_AWUSER" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[4:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="368" MSB="63" NAME="S_AXI_ACP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
        <PORT BUS="S_AXI_ACP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="369" MSB="7" NAME="S_AXI_ACP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" MPD_INDEX="370" NAME="S_AXI_HP0_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARREADY" DIR="O" MPD_INDEX="371" NAME="S_AXI_HP0_ARREADY" SIGNAME="axi_interconnect_2_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWREADY" DIR="O" MPD_INDEX="372" NAME="S_AXI_HP0_AWREADY" SIGNAME="axi_interconnect_2_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_BVALID" DIR="O" MPD_INDEX="373" NAME="S_AXI_HP0_BVALID" SIGNAME="axi_interconnect_2_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_RLAST" DIR="O" MPD_INDEX="374" NAME="S_AXI_HP0_RLAST" SIGNAME="axi_interconnect_2_M_RLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_RVALID" DIR="O" MPD_INDEX="375" NAME="S_AXI_HP0_RVALID" SIGNAME="axi_interconnect_2_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_WREADY" DIR="O" MPD_INDEX="376" NAME="S_AXI_HP0_WREADY" SIGNAME="axi_interconnect_2_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="377" MSB="1" NAME="S_AXI_HP0_BRESP" RIGHT="0" SIGNAME="axi_interconnect_2_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="378" MSB="1" NAME="S_AXI_HP0_RRESP" RIGHT="0" SIGNAME="axi_interconnect_2_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_BID" DIR="O" MPD_INDEX="379" NAME="S_AXI_HP0_BID" SIGNAME="axi_interconnect_2_M_BID" VECFORMULA="[(C_S_AXI_HP0_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_RID" DIR="O" MPD_INDEX="380" NAME="S_AXI_HP0_RID" SIGNAME="axi_interconnect_2_M_RID" VECFORMULA="[(C_S_AXI_HP0_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="381" MSB="63" NAME="S_AXI_HP0_RDATA" RIGHT="0" SIGNAME="axi_interconnect_2_M_RDATA" VECFORMULA="[(C_S_AXI_HP0_DATA_WIDTH - 1) :0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" LEFT="7" LSB="0" MPD_INDEX="382" MSB="7" NAME="S_AXI_HP0_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" LEFT="7" LSB="0" MPD_INDEX="383" MSB="7" NAME="S_AXI_HP0_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" LEFT="2" LSB="0" MPD_INDEX="384" MSB="2" NAME="S_AXI_HP0_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP0_FIFO_CTRL" LEFT="5" LSB="0" MPD_INDEX="385" MSB="5" NAME="S_AXI_HP0_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARVALID" DIR="I" MPD_INDEX="387" NAME="S_AXI_HP0_ARVALID" SIGNAME="axi_interconnect_2_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWVALID" DIR="I" MPD_INDEX="388" NAME="S_AXI_HP0_AWVALID" SIGNAME="axi_interconnect_2_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_BREADY" DIR="I" MPD_INDEX="389" NAME="S_AXI_HP0_BREADY" SIGNAME="axi_interconnect_2_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="S_AXI_HP0_FIFO_CTRL" MPD_INDEX="390" NAME="S_AXI_HP0_RDISSUECAP1_EN" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_RREADY" DIR="I" MPD_INDEX="391" NAME="S_AXI_HP0_RREADY" SIGNAME="axi_interconnect_2_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_WLAST" DIR="I" MPD_INDEX="392" NAME="S_AXI_HP0_WLAST" SIGNAME="axi_interconnect_2_M_WLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="S_AXI_HP0_FIFO_CTRL" MPD_INDEX="393" NAME="S_AXI_HP0_WRISSUECAP1_EN" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_WVALID" DIR="I" MPD_INDEX="394" NAME="S_AXI_HP0_WVALID" SIGNAME="axi_interconnect_2_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="395" MSB="1" NAME="S_AXI_HP0_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="396" MSB="1" NAME="S_AXI_HP0_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARLOCK" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="397" MSB="2" NAME="S_AXI_HP0_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="398" MSB="1" NAME="S_AXI_HP0_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="399" MSB="1" NAME="S_AXI_HP0_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWLOCK" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="400" MSB="2" NAME="S_AXI_HP0_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="401" MSB="2" NAME="S_AXI_HP0_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="402" MSB="2" NAME="S_AXI_HP0_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="403" MSB="31" NAME="S_AXI_HP0_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARADDR" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="404" MSB="31" NAME="S_AXI_HP0_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWADDR" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="405" MSB="3" NAME="S_AXI_HP0_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="406" MSB="3" NAME="S_AXI_HP0_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARLEN" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="407" MSB="3" NAME="S_AXI_HP0_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARQOS" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="408" MSB="3" NAME="S_AXI_HP0_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="409" MSB="3" NAME="S_AXI_HP0_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWLEN" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="410" MSB="3" NAME="S_AXI_HP0_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWQOS" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_ARID" DIR="I" MPD_INDEX="411" NAME="S_AXI_HP0_ARID" SIGNAME="axi_interconnect_2_M_ARID" VECFORMULA="[(C_S_AXI_HP0_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_AWID" DIR="I" MPD_INDEX="412" NAME="S_AXI_HP0_AWID" SIGNAME="axi_interconnect_2_M_AWID" VECFORMULA="[(C_S_AXI_HP0_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_WID" DIR="I" MPD_INDEX="413" NAME="S_AXI_HP0_WID" SIGNAME="axi_interconnect_2_M_WID" VECFORMULA="[(C_S_AXI_HP0_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_WID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="414" MSB="63" NAME="S_AXI_HP0_WDATA" RIGHT="0" SIGNAME="axi_interconnect_2_M_WDATA" VECFORMULA="[(C_S_AXI_HP0_DATA_WIDTH - 1) :0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP0" DEF_SIGNAME="axi_interconnect_2_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="415" MSB="7" NAME="S_AXI_HP0_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_2_M_WSTRB" VECFORMULA="[((C_S_AXI_HP0_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="416" NAME="S_AXI_HP1_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARREADY" DIR="O" MPD_INDEX="417" NAME="S_AXI_HP1_ARREADY" SIGNAME="axi_interconnect_3_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWREADY" DIR="O" MPD_INDEX="418" NAME="S_AXI_HP1_AWREADY" SIGNAME="axi_interconnect_3_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_BVALID" DIR="O" MPD_INDEX="419" NAME="S_AXI_HP1_BVALID" SIGNAME="axi_interconnect_3_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_RLAST" DIR="O" MPD_INDEX="420" NAME="S_AXI_HP1_RLAST" SIGNAME="axi_interconnect_3_M_RLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_RVALID" DIR="O" MPD_INDEX="421" NAME="S_AXI_HP1_RVALID" SIGNAME="axi_interconnect_3_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_WREADY" DIR="O" MPD_INDEX="422" NAME="S_AXI_HP1_WREADY" SIGNAME="axi_interconnect_3_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="423" MSB="1" NAME="S_AXI_HP1_BRESP" RIGHT="0" SIGNAME="axi_interconnect_3_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="424" MSB="1" NAME="S_AXI_HP1_RRESP" RIGHT="0" SIGNAME="axi_interconnect_3_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_BID" DIR="O" MPD_INDEX="425" NAME="S_AXI_HP1_BID" SIGNAME="axi_interconnect_3_M_BID" VECFORMULA="[(C_S_AXI_HP1_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_RID" DIR="O" MPD_INDEX="426" NAME="S_AXI_HP1_RID" SIGNAME="axi_interconnect_3_M_RID" VECFORMULA="[(C_S_AXI_HP1_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="427" MSB="63" NAME="S_AXI_HP1_RDATA" RIGHT="0" SIGNAME="axi_interconnect_3_M_RDATA" VECFORMULA="[(C_S_AXI_HP1_DATA_WIDTH - 1) :0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" LEFT="7" LSB="0" MPD_INDEX="428" MSB="7" NAME="S_AXI_HP1_RCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" LEFT="7" LSB="0" MPD_INDEX="429" MSB="7" NAME="S_AXI_HP1_WCOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" LEFT="2" LSB="0" MPD_INDEX="430" MSB="2" NAME="S_AXI_HP1_RACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="S_AXI_HP1_FIFO_CTRL" LEFT="5" LSB="0" MPD_INDEX="431" MSB="5" NAME="S_AXI_HP1_WACOUNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARVALID" DIR="I" MPD_INDEX="433" NAME="S_AXI_HP1_ARVALID" SIGNAME="axi_interconnect_3_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWVALID" DIR="I" MPD_INDEX="434" NAME="S_AXI_HP1_AWVALID" SIGNAME="axi_interconnect_3_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_BREADY" DIR="I" MPD_INDEX="435" NAME="S_AXI_HP1_BREADY" SIGNAME="axi_interconnect_3_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="S_AXI_HP1_FIFO_CTRL" MPD_INDEX="436" NAME="S_AXI_HP1_RDISSUECAP1_EN" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_RREADY" DIR="I" MPD_INDEX="437" NAME="S_AXI_HP1_RREADY" SIGNAME="axi_interconnect_3_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_WLAST" DIR="I" MPD_INDEX="438" NAME="S_AXI_HP1_WLAST" SIGNAME="axi_interconnect_3_M_WLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="S_AXI_HP1_FIFO_CTRL" MPD_INDEX="439" NAME="S_AXI_HP1_WRISSUECAP1_EN" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_WVALID" DIR="I" MPD_INDEX="440" NAME="S_AXI_HP1_WVALID" SIGNAME="axi_interconnect_3_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="441" MSB="1" NAME="S_AXI_HP1_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="442" MSB="1" NAME="S_AXI_HP1_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARLOCK" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="443" MSB="2" NAME="S_AXI_HP1_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="444" MSB="1" NAME="S_AXI_HP1_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="445" MSB="1" NAME="S_AXI_HP1_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWLOCK" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="446" MSB="2" NAME="S_AXI_HP1_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="447" MSB="2" NAME="S_AXI_HP1_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="448" MSB="2" NAME="S_AXI_HP1_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="449" MSB="31" NAME="S_AXI_HP1_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARADDR" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="450" MSB="31" NAME="S_AXI_HP1_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWADDR" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="451" MSB="3" NAME="S_AXI_HP1_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="452" MSB="3" NAME="S_AXI_HP1_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARLEN" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="453" MSB="3" NAME="S_AXI_HP1_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARQOS" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="454" MSB="3" NAME="S_AXI_HP1_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="455" MSB="3" NAME="S_AXI_HP1_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWLEN" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="456" MSB="3" NAME="S_AXI_HP1_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWQOS" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_ARID" DIR="I" MPD_INDEX="457" NAME="S_AXI_HP1_ARID" SIGNAME="axi_interconnect_3_M_ARID" VECFORMULA="[(C_S_AXI_HP1_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_AWID" DIR="I" MPD_INDEX="458" NAME="S_AXI_HP1_AWID" SIGNAME="axi_interconnect_3_M_AWID" VECFORMULA="[(C_S_AXI_HP1_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_WID" DIR="I" MPD_INDEX="459" NAME="S_AXI_HP1_WID" SIGNAME="axi_interconnect_3_M_WID" VECFORMULA="[(C_S_AXI_HP1_ID_WIDTH - 1) : 0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_WID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="460" MSB="63" NAME="S_AXI_HP1_WDATA" RIGHT="0" SIGNAME="axi_interconnect_3_M_WDATA" VECFORMULA="[(C_S_AXI_HP1_DATA_WIDTH - 1) :0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_HP1" DEF_SIGNAME="axi_interconnect_3_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="461" MSB="7" NAME="S_AXI_HP1_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_3_M_WSTRB" VECFORMULA="[((C_S_AXI_HP1_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="462" NAME="S_AXI_HP2_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="463" NAME="S_AXI_HP2_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="464" NAME="S_AXI_HP2_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="465" NAME="S_AXI_HP2_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="466" NAME="S_AXI_HP2_RLAST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="467" NAME="S_AXI_HP2_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="468" NAME="S_AXI_HP2_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_HP2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="469" MSB="1" NAME="S_AXI_HP2_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
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        <PORT DIR="O" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="583" NAME="DMA3_DRREADY" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="584" NAME="DMA3_RSTN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="585" NAME="DMA3_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="586" NAME="DMA3_DAREADY" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="DMA3_REQ" IS_VALID="FALSE" MPD_INDEX="587" NAME="DMA3_DRLAST" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA3_REQ" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="589" MSB="1" NAME="DMA3_DRTYPE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="590" MSB="31" NAME="FTMD_TRACEIN_DATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT DIR="I" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" MPD_INDEX="591" NAME="FTMD_TRACEIN_VALID" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" MPD_INDEX="592" NAME="FTMD_TRACEIN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRACE_DATA" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="593" MSB="3" NAME="FTMD_TRACEIN_ATID" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="594" MSB="3" NAME="FTMT_F2P_TRIG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="595" MSB="3" NAME="FTMT_F2P_TRIGACK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="596" MSB="31" NAME="FTMT_F2P_DEBUG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="597" MSB="3" NAME="FTMT_P2F_TRIGACK" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="598" MSB="3" NAME="FTMT_P2F_TRIG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="FTM_TRIG" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="599" MSB="31" NAME="FTMT_P2F_DEBUG" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT DIR="I" MPD_INDEX="604" NAME="FCLK_CLKTRIG3_N" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="605" NAME="FCLK_CLKTRIG2_N" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="606" NAME="FCLK_CLKTRIG1_N" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="607" NAME="FCLK_CLKTRIG0_N" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="608" NAME="FCLK_RESET3_N" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="609" NAME="FCLK_RESET2_N" SIGIS="RST" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="612" NAME="FPGA_IDLE_N" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="613" MSB="3" NAME="DDR_ARB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT DIR="I" MPD_INDEX="615" NAME="Core0_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="616" NAME="Core0_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="617" NAME="Core1_nFIQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="618" NAME="Core1_nIRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="619" NAME="EVENT_EVENTO" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="620" MSB="1" NAME="EVENT_STANDBYWFE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="621" MSB="1" NAME="EVENT_STANDBYWFI" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="622" NAME="EVENT_EVENTI" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="644" NAME="IRQ_P2F_DMAC_ABORT" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="645" NAME="IRQ_P2F_DMAC0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="646" NAME="IRQ_P2F_DMAC1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="647" NAME="IRQ_P2F_DMAC2" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="648" NAME="IRQ_P2F_DMAC3" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="649" NAME="IRQ_P2F_DMAC4" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="650" NAME="IRQ_P2F_DMAC5" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="651" NAME="IRQ_P2F_DMAC6" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="652" NAME="IRQ_P2F_DMAC7" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="653" NAME="IRQ_P2F_SMC" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="654" NAME="IRQ_P2F_QSPI" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="655" NAME="IRQ_P2F_CTI" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="656" NAME="IRQ_P2F_GPIO" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="657" NAME="IRQ_P2F_USB0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="658" NAME="IRQ_P2F_ENET0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="659" NAME="IRQ_P2F_ENET_WAKE0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="660" NAME="IRQ_P2F_SDIO0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="661" NAME="IRQ_P2F_I2C0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="662" NAME="IRQ_P2F_SPI0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="663" NAME="IRQ_P2F_UART0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="664" NAME="IRQ_P2F_CAN0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="665" NAME="IRQ_P2F_USB1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="666" NAME="IRQ_P2F_ENET1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="667" NAME="IRQ_P2F_ENET_WAKE1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="668" NAME="IRQ_P2F_SDIO1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="669" NAME="IRQ_P2F_I2C1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="670" NAME="IRQ_P2F_SPI1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="671" NAME="IRQ_P2F_UART1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="672" NAME="IRQ_P2F_CAN1" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="IO" IOS="ETHERNETIF_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="673" NAME="ENET0_MDIO" SIGNAME="__NOC__" TRI_I="ENET0_MDIO_I" TRI_O="ENET0_MDIO_O" TRI_T="ENET0_MDIO_T"/>
        <PORT DIR="IO" IOS="ETHERNETIF_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="674" NAME="ENET1_MDIO" SIGNAME="__NOC__" TRI_I="ENET1_MDIO_I" TRI_O="ENET1_MDIO_O" TRI_T="ENET1_MDIO_T"/>
        <PORT DIR="IO" IOS="IIC_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="676" NAME="I2C0_SDA" SIGNAME="__NOC__" TRI_I="I2C0_SDA_I" TRI_O="I2C0_SDA_O" TRI_T="I2C0_SDA_T"/>
        <PORT DIR="IO" IOS="IIC_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="677" NAME="I2C0_SCL" SIGNAME="__NOC__" TRI_I="I2C0_SCL_I" TRI_O="I2C0_SCL_O" TRI_T="I2C0_SCL_T"/>
        <PORT DIR="IO" IOS="IIC_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="678" NAME="I2C1_SDA" SIGNAME="__NOC__" TRI_I="I2C1_SDA_I" TRI_O="I2C1_SDA_O" TRI_T="I2C1_SDA_T"/>
        <PORT DIR="IO" IOS="IIC_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="679" NAME="I2C1_SCL" SIGNAME="__NOC__" TRI_I="I2C1_SCL_I" TRI_O="I2C1_SCL_O" TRI_T="I2C1_SCL_T"/>
        <PORT DIR="IO" IOS="SDIO_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="680" NAME="SDIO0_CMD" SIGNAME="__NOC__" TRI_I="SDIO0_CMD_I" TRI_O="SDIO0_CMD_O" TRI_T="SDIO0_CMD_T"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="SDIO_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="681" MSB="3" NAME="SDIO0_DATA" RIGHT="0" SIGNAME="__NOC__" TRI_I="SDIO0_DATA_I" TRI_O="SDIO0_DATA_O" TRI_T="SDIO0_DATA_T" VECFORMULA="[3:0]"/>
        <PORT DIR="IO" IOS="SDIO_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" MPD_INDEX="682" NAME="SDIO1_CMD" SIGNAME="__NOC__" TRI_I="SDIO1_CMD_I" TRI_O="SDIO1_CMD_O" TRI_T="SDIO1_CMD_T"/>
        <PORT DIR="IO" ENDIAN="LITTLE" IOS="SDIO_1" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="683" MSB="3" NAME="SDIO1_DATA" RIGHT="0" SIGNAME="__NOC__" TRI_I="SDIO1_DATA_I" TRI_O="SDIO1_DATA_O" TRI_T="SDIO1_DATA_T" VECFORMULA="[3:0]"/>
        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" MPD_INDEX="684" NAME="SPI0_SCLK" SIGIS="CLK" SIGNAME="__NOC__" TRI_I="SPI0_SCLK_I" TRI_O="SPI0_SCLK_O" TRI_T="SPI0_SCLK_T"/>
        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" MPD_INDEX="685" NAME="SPI0_MOSI" SIGNAME="__NOC__" TRI_I="SPI0_MOSI_I" TRI_O="SPI0_MOSI_O" TRI_T="SPI0_MOSI_T"/>
        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" MPD_INDEX="686" NAME="SPI0_MISO" SIGNAME="__NOC__" TRI_I="SPI0_MISO_I" TRI_O="SPI0_MISO_O" TRI_T="SPI0_MISO_T"/>
        <PORT DIR="IO" IOS="SPI_0" IS_THREE_STATE="TRUE" MPD_INDEX="687" NAME="SPI0_SS" SIGNAME="__NOC__" TRI_I="SPI0_SS_I" TRI_O="SPI0_SS_O" TRI_T="SPI0_SS_T"/>
        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" MPD_INDEX="688" NAME="SPI1_SCLK" SIGIS="CLK" SIGNAME="__NOC__" TRI_I="SPI1_SCLK_I" TRI_O="SPI1_SCLK_O" TRI_T="SPI1_SCLK_T"/>
        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" MPD_INDEX="689" NAME="SPI1_MOSI" SIGNAME="__NOC__" TRI_I="SPI1_MOSI_I" TRI_O="SPI1_MOSI_O" TRI_T="SPI1_MOSI_T"/>
        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" MPD_INDEX="690" NAME="SPI1_MISO" SIGNAME="__NOC__" TRI_I="SPI1_MISO_I" TRI_O="SPI1_MISO_O" TRI_T="SPI1_MISO_T"/>
        <PORT DIR="IO" IOS="SPI_1" IS_THREE_STATE="TRUE" MPD_INDEX="691" NAME="SPI1_SS" SIGNAME="__NOC__" TRI_I="SPI1_SS_I" TRI_O="SPI1_SS_O" TRI_T="SPI1_SS_T"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="M_AXI_GP0" PROTOCOL="AXI3" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_ACLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_BREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_RREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP0_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_ARREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_WREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP0_RDATA"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_interconnect_2" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="S_AXI_HP0" PROTOCOL="AXI3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ACLK"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RLAST"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_BID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_ARID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_AWID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WSTRB"/>
          </PORTMAPS>
          <MASTERS>
            <MASTER BUSINTERFACE="M_AXI_MM2S" INSTANCE="axi_vdma_0"/>
          </MASTERS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_interconnect_3" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="S_AXI_HP1" PROTOCOL="AXI3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ACLK"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RLAST"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_BID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_ARID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_AWID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WSTRB"/>
          </PORTMAPS>
          <MASTERS>
            <MASTER BUSINTERFACE="M_AXI_MM2S" INSTANCE="axi_vdma_1"/>
          </MASTERS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="1" NAME="M_AXI_GP1" PROTOCOL="AXI3" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_BREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_RREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWBURST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWLOCK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWSIZE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWPROT"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWADDR"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_ARQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWCACHE"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWLEN"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_AWQOS"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXI_GP1_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_ARREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_WREADY"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_BRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RRESP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXI_GP1_RDATA"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="S_AXI_GP0" PROTOCOL="AXI3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RLAST"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_BID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP0_RID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_ARID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_AWID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP0_WID"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_GP1" PROTOCOL="AXI3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RLAST"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_BID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_GP1_RID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_ARID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_AWID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_GP1_WID"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="4" NAME="S_AXI_ACP" PROTOCOL="AXI3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RLAST"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_BID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ACP_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_ARUSER"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_AWUSER"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACP_WSTRB"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="7" NAME="S_AXI_HP2" PROTOCOL="AXI3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RLAST"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_BID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_ARID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_AWID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WSTRB"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="8" NAME="S_AXI_HP3" PROTOCOL="AXI3" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_AWREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RLAST"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_BID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_RREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWBURST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWLOCK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWSIZE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWPROT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWCACHE"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWLEN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWQOS"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_ARID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_AWID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WSTRB"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="4" NAME="PS_REQUIRED_EXTERNAL_IO" TYPE="XIL_REQUIRED_EXTERNAL_IO">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="MIO"/>
            <PORTMAP DIR="I" PHYSICAL="PS_SRSTB"/>
            <PORTMAP DIR="I" PHYSICAL="PS_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="PS_PORB"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="3" NAME="MEMORY_0" TYPE="XIL_MEMORY_V1">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="DDR_Clk"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_Clk_n"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_CKE"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_CS_n"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_RAS_n"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_CAS_n"/>
            <PORTMAP DIR="O" PHYSICAL="DDR_WEB"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_BankAddr"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_Addr"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_ODT"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_DRSTB"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_DQ"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_DM"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_DQS"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_DQS_n"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_VRN"/>
            <PORTMAP DIR="IO" PHYSICAL="DDR_VRP"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="20" NAME="USBIND_0" TYPE="XIL_USBIND_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="USB0_VBUS_PWRFAULT"/>
            <PORTMAP DIR="O" PHYSICAL="USB0_PORT_INDCTL"/>
            <PORTMAP DIR="O" PHYSICAL="USB0_VBUS_PWRSELECT"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="26" NAME="DMA0_REQ" TYPE="XIL_DMA_REQ_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="DMA0_ACLK"/>
            <PORTMAP DIR="O" PHYSICAL="DMA0_RSTN"/>
            <PORTMAP DIR="O" PHYSICAL="DMA0_DATYPE"/>
            <PORTMAP DIR="O" PHYSICAL="DMA0_DAVALID"/>
            <PORTMAP DIR="O" PHYSICAL="DMA0_DRREADY"/>
            <PORTMAP DIR="I" PHYSICAL="DMA0_DAREADY"/>
            <PORTMAP DIR="I" PHYSICAL="DMA0_DRLAST"/>
            <PORTMAP DIR="I" PHYSICAL="DMA0_DRTYPE"/>
            <PORTMAP DIR="I" PHYSICAL="DMA0_DRVALID"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="27" NAME="DMA1_REQ" TYPE="XIL_DMA_REQ_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="DMA1_ACLK"/>
            <PORTMAP DIR="O" PHYSICAL="DMA1_DAVALID"/>
            <PORTMAP DIR="O" PHYSICAL="DMA1_DATYPE"/>
            <PORTMAP DIR="O" PHYSICAL="DMA1_DRREADY"/>
            <PORTMAP DIR="O" PHYSICAL="DMA1_RSTN"/>
            <PORTMAP DIR="I" PHYSICAL="DMA1_DRVALID"/>
            <PORTMAP DIR="I" PHYSICAL="DMA1_DRTYPE"/>
            <PORTMAP DIR="I" PHYSICAL="DMA1_DAREADY"/>
            <PORTMAP DIR="I" PHYSICAL="DMA1_DRLAST"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="28" NAME="DMA2_REQ" TYPE="XIL_DMA_REQ_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="DMA2_DATYPE"/>
            <PORTMAP DIR="I" PHYSICAL="DMA2_ACLK"/>
            <PORTMAP DIR="O" PHYSICAL="DMA2_DAVALID"/>
            <PORTMAP DIR="O" PHYSICAL="DMA2_DRREADY"/>
            <PORTMAP DIR="O" PHYSICAL="DMA2_RSTN"/>
            <PORTMAP DIR="I" PHYSICAL="DMA2_DRLAST"/>
            <PORTMAP DIR="I" PHYSICAL="DMA2_DRVALID"/>
            <PORTMAP DIR="I" PHYSICAL="DMA2_DRTYPE"/>
            <PORTMAP DIR="I" PHYSICAL="DMA2_DAREADY"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="2" NAME="GPIO_0" TYPE="XIL_GPIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="GPIO"/>
            <PORTMAP DIR="I" PHYSICAL="GPIO_I"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_O"/>
            <PORTMAP DIR="O" PHYSICAL="GPIO_T"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="9" NAME="SPI_0" TYPE="XIL_SPI_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SPI0_SCLK_O"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_MOSI_O"/>
            <PORTMAP DIR="I" PHYSICAL="SPI0_MISO_I"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_SS_O"/>
            <PORTMAP DIR="I" PHYSICAL="SPI0_SS_I"/>
            <PORTMAP DIR="I" PHYSICAL="SPI0_SCLK_I"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_SCLK_T"/>
            <PORTMAP DIR="I" PHYSICAL="SPI0_MOSI_I"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_MOSI_T"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_MISO_O"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_MISO_T"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_SS1_O"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_SS2_O"/>
            <PORTMAP DIR="O" PHYSICAL="SPI0_SS_T"/>
            <PORTMAP DIR="IO" PHYSICAL="SPI0_SCLK"/>
            <PORTMAP DIR="IO" PHYSICAL="SPI0_MOSI"/>
            <PORTMAP DIR="IO" PHYSICAL="SPI0_MISO"/>
            <PORTMAP DIR="IO" PHYSICAL="SPI0_SS"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="10" NAME="SPI_1" TYPE="XIL_SPI_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SPI1_SCLK_O"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_MOSI_O"/>
            <PORTMAP DIR="I" PHYSICAL="SPI1_MISO_I"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_SS_O"/>
            <PORTMAP DIR="I" PHYSICAL="SPI1_SS_I"/>
            <PORTMAP DIR="I" PHYSICAL="SPI1_SCLK_I"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_SCLK_T"/>
            <PORTMAP DIR="I" PHYSICAL="SPI1_MOSI_I"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_MOSI_T"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_MISO_O"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_MISO_T"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_SS1_O"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_SS2_O"/>
            <PORTMAP DIR="O" PHYSICAL="SPI1_SS_T"/>
            <PORTMAP DIR="IO" PHYSICAL="SPI1_SCLK"/>
            <PORTMAP DIR="IO" PHYSICAL="SPI1_MOSI"/>
            <PORTMAP DIR="IO" PHYSICAL="SPI1_MISO"/>
            <PORTMAP DIR="IO" PHYSICAL="SPI1_SS"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="11" NAME="CAN_0" TYPE="XIL_CAN_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="CAN0_PHY_TX"/>
            <PORTMAP DIR="I" PHYSICAL="CAN0_PHY_RX"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="12" NAME="CAN_1" TYPE="XIL_CAN_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="CAN1_PHY_TX"/>
            <PORTMAP DIR="I" PHYSICAL="CAN1_PHY_RX"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="0" NAME="ETHERNETIF_0" TYPE="XIL_AXIETHERNET_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="ENET0_GMII_TX_EN"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_GMII_TX_ER"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_MDIO_MDC"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_MDIO_O"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_MDIO_T"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_PTP_DELAY_REQ_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_PTP_DELAY_REQ_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_PTP_PDELAY_REQ_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_PTP_PDELAY_REQ_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_PTP_PDELAY_RESP_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_PTP_PDELAY_RESP_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_PTP_SYNC_FRAME_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_PTP_SYNC_FRAME_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_SOF_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_SOF_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET0_GMII_TXD"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_GMII_COL"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_GMII_CRS"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_EXT_INTIN"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_GMII_RX_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_GMII_RX_DV"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_GMII_RX_ER"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_GMII_TX_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_MDIO_I"/>
            <PORTMAP DIR="I" PHYSICAL="ENET0_GMII_RXD"/>
            <PORTMAP DIR="IO" PHYSICAL="ENET0_MDIO"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="1" NAME="ETHERNETIF_1" TYPE="XIL_AXIETHERNET_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="ENET1_GMII_TX_EN"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_GMII_TX_ER"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_MDIO_MDC"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_MDIO_O"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_MDIO_T"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_PTP_DELAY_REQ_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_PTP_DELAY_REQ_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_PTP_PDELAY_REQ_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_PTP_PDELAY_REQ_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_PTP_PDELAY_RESP_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_PTP_PDELAY_RESP_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_PTP_SYNC_FRAME_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_PTP_SYNC_FRAME_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_SOF_RX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_SOF_TX"/>
            <PORTMAP DIR="O" PHYSICAL="ENET1_GMII_TXD"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_GMII_COL"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_GMII_CRS"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_EXT_INTIN"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_GMII_RX_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_GMII_RX_DV"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_GMII_RX_ER"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_GMII_TX_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_MDIO_I"/>
            <PORTMAP DIR="I" PHYSICAL="ENET1_GMII_RXD"/>
            <PORTMAP DIR="IO" PHYSICAL="ENET1_MDIO"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="7" NAME="IIC_0" TYPE="XIL_IIC_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="I2C0_SDA_I"/>
            <PORTMAP DIR="O" PHYSICAL="I2C0_SDA_O"/>
            <PORTMAP DIR="O" PHYSICAL="I2C0_SDA_T"/>
            <PORTMAP DIR="I" PHYSICAL="I2C0_SCL_I"/>
            <PORTMAP DIR="O" PHYSICAL="I2C0_SCL_O"/>
            <PORTMAP DIR="O" PHYSICAL="I2C0_SCL_T"/>
            <PORTMAP DIR="IO" PHYSICAL="I2C0_SDA"/>
            <PORTMAP DIR="IO" PHYSICAL="I2C0_SCL"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="8" NAME="IIC_1" TYPE="XIL_IIC_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="I2C1_SDA_I"/>
            <PORTMAP DIR="O" PHYSICAL="I2C1_SDA_O"/>
            <PORTMAP DIR="O" PHYSICAL="I2C1_SDA_T"/>
            <PORTMAP DIR="I" PHYSICAL="I2C1_SCL_I"/>
            <PORTMAP DIR="O" PHYSICAL="I2C1_SCL_O"/>
            <PORTMAP DIR="O" PHYSICAL="I2C1_SCL_T"/>
            <PORTMAP DIR="IO" PHYSICAL="I2C1_SDA"/>
            <PORTMAP DIR="IO" PHYSICAL="I2C1_SCL"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="13" NAME="PJTAG" TYPE="XIL_JTAG_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="PJTAG_TCK"/>
            <PORTMAP DIR="I" PHYSICAL="PJTAG_TMS"/>
            <PORTMAP DIR="I" PHYSICAL="PJTAG_TD_I"/>
            <PORTMAP DIR="O" PHYSICAL="PJTAG_TD_T"/>
            <PORTMAP DIR="O" PHYSICAL="PJTAG_TD_O"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="14" NAME="SDIO_0" TYPE="XIL_SDIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDIO0_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO0_CLK_FB"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO0_CMD_O"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO0_CMD_I"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO0_CMD_T"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO0_DATA_I"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO0_DATA_O"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO0_DATA_T"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO0_LED"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO0_CDN"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO0_WP"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO0_BUSPOW"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO0_BUSVOLT"/>
            <PORTMAP DIR="IO" PHYSICAL="SDIO0_CMD"/>
            <PORTMAP DIR="IO" PHYSICAL="SDIO0_DATA"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="15" NAME="SDIO_1" TYPE="XIL_SDIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="SDIO1_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO1_CLK_FB"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO1_CMD_O"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO1_CMD_I"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO1_CMD_T"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO1_DATA_I"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO1_DATA_O"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO1_DATA_T"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO1_LED"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO1_CDN"/>
            <PORTMAP DIR="I" PHYSICAL="SDIO1_WP"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO1_BUSPOW"/>
            <PORTMAP DIR="O" PHYSICAL="SDIO1_BUSVOLT"/>
            <PORTMAP DIR="IO" PHYSICAL="SDIO1_CMD"/>
            <PORTMAP DIR="IO" PHYSICAL="SDIO1_DATA"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="5" NAME="UART_0" TYPE="XIL_UART_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="UART0_DTRN"/>
            <PORTMAP DIR="O" PHYSICAL="UART0_RTSN"/>
            <PORTMAP DIR="O" PHYSICAL="UART0_TX"/>
            <PORTMAP DIR="I" PHYSICAL="UART0_CTSN"/>
            <PORTMAP DIR="I" PHYSICAL="UART0_DCDN"/>
            <PORTMAP DIR="I" PHYSICAL="UART0_DSRN"/>
            <PORTMAP DIR="I" PHYSICAL="UART0_RIN"/>
            <PORTMAP DIR="I" PHYSICAL="UART0_RX"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="6" NAME="UART_1" TYPE="XIL_UART_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="UART1_DTRN"/>
            <PORTMAP DIR="O" PHYSICAL="UART1_RTSN"/>
            <PORTMAP DIR="O" PHYSICAL="UART1_TX"/>
            <PORTMAP DIR="I" PHYSICAL="UART1_CTSN"/>
            <PORTMAP DIR="I" PHYSICAL="UART1_DCDN"/>
            <PORTMAP DIR="I" PHYSICAL="UART1_DSRN"/>
            <PORTMAP DIR="I" PHYSICAL="UART1_RIN"/>
            <PORTMAP DIR="I" PHYSICAL="UART1_RX"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="16" NAME="TTC_0" TYPE="XIL_TTC_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="TTC0_WAVE0_OUT"/>
            <PORTMAP DIR="O" PHYSICAL="TTC0_WAVE1_OUT"/>
            <PORTMAP DIR="O" PHYSICAL="TTC0_WAVE2_OUT"/>
            <PORTMAP DIR="I" PHYSICAL="TTC0_CLK0_IN"/>
            <PORTMAP DIR="I" PHYSICAL="TTC0_CLK1_IN"/>
            <PORTMAP DIR="I" PHYSICAL="TTC0_CLK2_IN"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="17" NAME="TTC_1" TYPE="XIL_TTC_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="TTC1_WAVE0_OUT"/>
            <PORTMAP DIR="O" PHYSICAL="TTC1_WAVE1_OUT"/>
            <PORTMAP DIR="O" PHYSICAL="TTC1_WAVE2_OUT"/>
            <PORTMAP DIR="I" PHYSICAL="TTC1_CLK0_IN"/>
            <PORTMAP DIR="I" PHYSICAL="TTC1_CLK1_IN"/>
            <PORTMAP DIR="I" PHYSICAL="TTC1_CLK2_IN"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="18" NAME="WDT_0" TYPE="XIL_WDT_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="WDT_CLK_IN"/>
            <PORTMAP DIR="O" PHYSICAL="WDT_RST_OUT"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="19" NAME="TRACE_0" TYPE="XIL_TRACE_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="TRACE_CLK"/>
            <PORTMAP DIR="O" PHYSICAL="TRACE_CTL"/>
            <PORTMAP DIR="O" PHYSICAL="TRACE_DATA"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="21" NAME="USBIND_1" TYPE="XIL_USBIND_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="USB1_PORT_INDCTL"/>
            <PORTMAP DIR="O" PHYSICAL="USB1_VBUS_PWRSELECT"/>
            <PORTMAP DIR="I" PHYSICAL="USB1_VBUS_PWRFAULT"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="22" NAME="S_AXI_HP0_FIFO_CTRL" TYPE="XIL_HP_FIFO_CTRL_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RCOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_WCOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_RACOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP0_WACOUNT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_RDISSUECAP1_EN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP0_WRISSUECAP1_EN"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="23" NAME="S_AXI_HP1_FIFO_CTRL" TYPE="XIL_HP_FIFO_CTRL_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RCOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_WCOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_RACOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP1_WACOUNT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_RDISSUECAP1_EN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP1_WRISSUECAP1_EN"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="24" NAME="S_AXI_HP2_FIFO_CTRL" TYPE="XIL_HP_FIFO_CTRL_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RCOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_WCOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_RACOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP2_WACOUNT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_RDISSUECAP1_EN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP2_WRISSUECAP1_EN"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="25" NAME="S_AXI_HP3_FIFO_CTRL" TYPE="XIL_HP_FIFO_CTRL_V1">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RCOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_WCOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_RACOUNT"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_HP3_WACOUNT"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_RDISSUECAP1_EN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_HP3_WRISSUECAP1_EN"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="29" NAME="DMA3_REQ" TYPE="XIL_DMA_REQ_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="DMA3_DRVALID"/>
            <PORTMAP DIR="O" PHYSICAL="DMA3_DATYPE"/>
            <PORTMAP DIR="O" PHYSICAL="DMA3_DAVALID"/>
            <PORTMAP DIR="O" PHYSICAL="DMA3_DRREADY"/>
            <PORTMAP DIR="O" PHYSICAL="DMA3_RSTN"/>
            <PORTMAP DIR="I" PHYSICAL="DMA3_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="DMA3_DAREADY"/>
            <PORTMAP DIR="I" PHYSICAL="DMA3_DRLAST"/>
            <PORTMAP DIR="I" PHYSICAL="DMA3_DRTYPE"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="30" NAME="FTM_TRACE_DATA" TYPE="XIL_FTMD_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FTMD_TRACEIN_DATA"/>
            <PORTMAP DIR="I" PHYSICAL="FTMD_TRACEIN_VALID"/>
            <PORTMAP DIR="I" PHYSICAL="FTMD_TRACEIN_CLK"/>
            <PORTMAP DIR="I" PHYSICAL="FTMD_TRACEIN_ATID"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="31" NAME="FTM_TRIG" TYPE="XIL_FTMTIO_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="FTMT_F2P_TRIG"/>
            <PORTMAP DIR="O" PHYSICAL="FTMT_F2P_TRIGACK"/>
            <PORTMAP DIR="I" PHYSICAL="FTMT_F2P_DEBUG"/>
            <PORTMAP DIR="I" PHYSICAL="FTMT_P2F_TRIGACK"/>
            <PORTMAP DIR="O" PHYSICAL="FTMT_P2F_TRIG"/>
            <PORTMAP DIR="O" PHYSICAL="FTMT_P2F_DEBUG"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE IS_VALID="FALSE" MPD_INDEX="32" NAME="PROC_EVENT" TYPE="XIL_PROC_EVENT_V1"/>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_DDR_RAM_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_DDR_RAM_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" MEMTYPE="MEMORY" SIZE="536870912" SIZEABRV="512M"/>
        <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_UART0_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="3758100479" HIGHNAME="C_UART0_HIGHADDR" HIGHVALUE="0xE0000FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758100480" BASENAME="C_UART1_BASEADDR" BASEVALUE="0xE0001000" HIGHDECIMAL="3758104575" HIGHNAME="C_UART1_HIGHADDR" HIGHVALUE="0xE0001FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758112768" BASENAME="C_I2C0_BASEADDR" BASEVALUE="0xE0004000" HIGHDECIMAL="3758116863" HIGHNAME="C_I2C0_HIGHADDR" HIGHVALUE="0xE0004FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758116864" BASENAME="C_I2C1_BASEADDR" BASEVALUE="0xE0005000" HIGHDECIMAL="3758120959" HIGHNAME="C_I2C1_HIGHADDR" HIGHVALUE="0xE0005FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758120960" BASENAME="C_SPI0_BASEADDR" BASEVALUE="0xE0006000" HIGHDECIMAL="3758125055" HIGHNAME="C_SPI0_HIGHADDR" HIGHVALUE="0xE0006FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758125056" BASENAME="C_SPI1_BASEADDR" BASEVALUE="0xE0007000" HIGHDECIMAL="3758129151" HIGHNAME="C_SPI1_HIGHADDR" HIGHVALUE="0xE0007FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758129152" BASENAME="C_CAN0_BASEADDR" BASEVALUE="0xE0008000" HIGHDECIMAL="3758133247" HIGHNAME="C_CAN0_HIGHADDR" HIGHVALUE="0xE0008FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758133248" BASENAME="C_CAN1_BASEADDR" BASEVALUE="0xE0009000" HIGHDECIMAL="3758137343" HIGHNAME="C_CAN1_HIGHADDR" HIGHVALUE="0xE0009FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758137344" BASENAME="C_GPIO_BASEADDR" BASEVALUE="0xE000A000" HIGHDECIMAL="3758141439" HIGHNAME="C_GPIO_HIGHADDR" HIGHVALUE="0xE000AFFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758141440" BASENAME="C_ENET0_BASEADDR" BASEVALUE="0xE000B000" HIGHDECIMAL="3758145535" HIGHNAME="C_ENET0_HIGHADDR" HIGHVALUE="0xE000BFFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758145536" BASENAME="C_ENET1_BASEADDR" BASEVALUE="0xE000C000" HIGHDECIMAL="3758149631" HIGHNAME="C_ENET1_HIGHADDR" HIGHVALUE="0xE000CFFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3759144960" BASENAME="C_SDIO0_BASEADDR" BASEVALUE="0xE0100000" HIGHDECIMAL="3759149055" HIGHNAME="C_SDIO0_HIGHADDR" HIGHVALUE="0xE0100FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3759149056" BASENAME="C_SDIO1_BASEADDR" BASEVALUE="0xE0101000" HIGHDECIMAL="3759153151" HIGHNAME="C_SDIO1_HIGHADDR" HIGHVALUE="0xE0101FFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3759153152" BASENAME="C_USB0_BASEADDR" BASEVALUE="0xE0102000" HIGHDECIMAL="3759157247" HIGHNAME="C_USB0_HIGHADDR" HIGHVALUE="0xE0102fff" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3759157248" BASENAME="C_USB1_BASEADDR" BASEVALUE="0xE0103000" HIGHDECIMAL="3759161343" HIGHNAME="C_USB1_HIGHADDR" HIGHVALUE="0xE0103fff" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3759161344" BASENAME="C_TTC0_BASEADDR" BASEVALUE="0xE0104000" HIGHDECIMAL="3759165439" HIGHNAME="C_TTC0_HIGHADDR" HIGHVALUE="0xE0104fff" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3759165440" BASENAME="C_TTC1_BASEADDR" BASEVALUE="0xE0105000" HIGHDECIMAL="3759169535" HIGHNAME="C_TTC1_HIGHADDR" HIGHVALUE="0xE0105fff" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="4096" SIZEABRV="4K"/>
        <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_S_AXI_GP0_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="4294967295" HIGHNAME="C_S_AXI_GP0_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="536870912" SIZEABRV="512M">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_GP0"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_GP0_LOWOCM_DDR_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="1073741823" HIGHNAME="C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR" HIGHVALUE="0x3FFFFFFF" INSTANCE="processing_system7_0" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="1073741824" SIZEABRV="1G">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_GP0"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="3758096384" BASENAME="C_S_AXI_GP1_BASEADDR" BASEVALUE="0xE0000000" HIGHDECIMAL="4294967295" HIGHNAME="C_S_AXI_GP1_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="processing_system7_0" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="536870912" SIZEABRV="512M">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_GP1"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_GP1_LOWOCM_DDR_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="1073741823" HIGHNAME="C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR" HIGHVALUE="0x3FFFFFFF" INSTANCE="processing_system7_0" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="1073741824" SIZEABRV="1G">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_GP1"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_ACP_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="1073741823" HIGHNAME="C_S_AXI_ACP_HIGHADDR" HIGHVALUE="0x3FFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="1073741824" SIZEABRV="1G">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_ACP"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_ACP_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294967295" HIGHNAME="C_S_AXI_ACP_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="262144" SIZEABRV="256K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_ACP"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP0_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP0_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" MEMTYPE="REGISTER" SIZE="536870912" SIZEABRV="512M">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_HP0"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP0_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294967295" HIGHNAME="C_S_AXI_HP0_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="262144" SIZEABRV="256K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_HP0"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP1_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP1_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" MEMTYPE="REGISTER" SIZE="536870912" SIZEABRV="512M">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_HP1"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP1_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294967295" HIGHNAME="C_S_AXI_HP1_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="262144" SIZEABRV="256K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_HP1"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP2_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP2_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="536870912" SIZEABRV="512M">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_HP2"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP2_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294967295" HIGHNAME="C_S_AXI_HP2_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="262144" SIZEABRV="256K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_HP2"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="0" BASENAME="C_S_AXI_HP3_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="536870911" HIGHNAME="C_S_AXI_HP3_HIGHADDR" HIGHVALUE="0x1FFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="536870912" SIZEABRV="512M">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_HP3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="4294705152" BASENAME="C_S_AXI_HP3_HIGHOCM_BASEADDR" BASEVALUE="0xFFFC0000" HIGHDECIMAL="4294967295" HIGHNAME="C_S_AXI_HP3_HIGHOCM_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="processing_system7_0" IS_CACHEABLE="TRUE" IS_CONSTANT="TRUE" IS_LOCKED="TRUE" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="262144" SIZEABRV="256K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_HP3"/>
          </SLAVES>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1124073472" BASENAME="C_BASEADDR" BASEVALUE="0x43000000" HIGHDECIMAL="1124139007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4300ffff" INSTANCE="axi_vdma_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1893728256" BASENAME="C_BASEADDR" BASEVALUE="0x70e00000" HIGHDECIMAL="1893793791" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x70e0ffff" INSTANCE="axi_hdmi_tx_16b_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1975517184" BASENAME="C_BASEADDR" BASEVALUE="0x75c00000" HIGHDECIMAL="1975582719" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x75c0ffff" INSTANCE="axi_spdif_tx_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1096810496" BASENAME="C_BASEADDR" BASEVALUE="0x41600000" HIGHDECIMAL="1096876031" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4160ffff" INSTANCE="axi_iic_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2030043136" BASENAME="C_BASEADDR" BASEVALUE="0x79000000" HIGHDECIMAL="2030108671" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7900ffff" INSTANCE="axi_clkgen_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2002780160" BASENAME="C_BASEADDR" BASEVALUE="0x77600000" HIGHDECIMAL="2002845695" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7760ffff" INSTANCE="axi_i2s_adi_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1097072640" BASENAME="C_BASEADDR" BASEVALUE="0x41640000" HIGHDECIMAL="1097138175" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4164ffff" INSTANCE="axi_iic_1" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="1124335616" BASENAME="C_BASEADDR" BASEVALUE="0x43040000" HIGHDECIMAL="1124401151" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4304ffff" INSTANCE="axi_vdma_1" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
        <MEMRANGE BASEDECIMAL="2002911232" BASENAME="C_BASEADDR" BASEVALUE="0x77620000" HIGHDECIMAL="2002976767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7762ffff" INSTANCE="axi_ad7303_0" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
          <ACCESSROUTE>
            <ROUTEPNT INDEX="0" INSTANCE="axi_interconnect_1"/>
          </ACCESSROUTE>
        </MEMRANGE>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="axi_vdma_0"/>
        <PERIPHERAL INSTANCE="axi_hdmi_tx_16b_0"/>
        <PERIPHERAL INSTANCE="axi_spdif_tx_0"/>
        <PERIPHERAL INSTANCE="axi_iic_0"/>
        <PERIPHERAL INSTANCE="axi_clkgen_0"/>
        <PERIPHERAL INSTANCE="axi_i2s_adi_0"/>
        <PERIPHERAL INSTANCE="axi_iic_1"/>
        <PERIPHERAL INSTANCE="axi_vdma_1"/>
        <PERIPHERAL INSTANCE="axi_ad7303_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE HWVERSION="5.04.a" INSTANCE="axi_vdma_0" IPTYPE="PERIPHERAL" MHS_INDEX="1" MODCLASS="PERIPHERAL" MODTYPE="axi_vdma">
      <DESCRIPTION TYPE="SHORT">AXI Video DMA</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">MemoryMap to/from Stream Video Direct Memory Access for AXI</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdma.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_LITE_ADDR_WIDTH" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_LITE_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_DLYTMR_RESOLUTION" TYPE="INTEGER" VALUE="125"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="3" NAME="C_PRMRY_IS_ACLK_ASYNC" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_M_AXI_SG_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_M_AXI_SG_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_NUM_FSTORES" TYPE="INTEGER" VALUE="3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="7" NAME="C_USE_FSYNC" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_FLUSH_ON_FSYNC" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_DYNAMIC_RESOLUTION" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_INCLUDE_SG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_INCLUDE_INTERNAL_GENLOCK" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_ENABLE_VIDPRMTR_READS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_INCLUDE_MM2S" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="14" NAME="C_M_AXI_MM2S_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="15" NAME="C_M_AXIS_MM2S_TDATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_INCLUDE_MM2S_DRE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_INCLUDE_MM2S_SF" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_MM2S_SOF_ENABLE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_MM2S_MAX_BURST_LENGTH" TYPE="INTEGER" VALUE="16"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="20" NAME="C_MM2S_GENLOCK_MODE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="21" NAME="C_MM2S_GENLOCK_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="22" NAME="C_MM2S_GENLOCK_REPEAT_EN" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="23" NAME="C_MM2S_LINEBUFFER_DEPTH" TYPE="INTEGER" VALUE="128"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="24" NAME="C_MM2S_LINEBUFFER_THRESH" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="25" NAME="C_M_AXI_MM2S_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="26" NAME="C_M_AXIS_MM2S_TUSER_BITS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="27" NAME="C_INCLUDE_S2MM" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_M_AXI_S2MM_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="29" NAME="C_S_AXIS_S2MM_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="30" NAME="C_INCLUDE_S2MM_DRE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="31" NAME="C_INCLUDE_S2MM_SF" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="32" NAME="C_S2MM_SOF_ENABLE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="33" NAME="C_S2MM_MAX_BURST_LENGTH" TYPE="INTEGER" VALUE="16"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="34" NAME="C_S2MM_GENLOCK_MODE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="35" NAME="C_S2MM_GENLOCK_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="36" NAME="C_S2MM_GENLOCK_REPEAT_EN" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="37" NAME="C_S2MM_LINEBUFFER_DEPTH" TYPE="INTEGER" VALUE="128"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="38" NAME="C_S2MM_LINEBUFFER_THRESH" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="39" NAME="C_M_AXI_S2MM_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="40" NAME="C_S_AXIS_S2MM_TUSER_BITS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="41" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="42" NAME="C_INSTANCE" TYPE="STRING" VALUE="axi_vdma_0"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="43" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x43000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="44" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x4300ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="45" NAME="C_S_AXI_LITE_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="46" NAME="C_S_AXI_LITE_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_LITE_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="48" NAME="C_M_AXI_SG_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="49" NAME="C_M_AXI_SG_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_SG_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="51" NAME="C_M_AXI_SG_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="52" NAME="C_M_AXI_SG_SUPPORTS_READ" TYPE="STRING" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_SG_SUPPORTS_WRITE" TYPE="STRING" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="54" NAME="C_M_AXI_MM2S_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="55" NAME="C_M_AXI_MM2S_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="56" NAME="C_M_AXI_MM2S_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="57" NAME="C_M_AXI_MM2S_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="58" NAME="C_M_AXI_MM2S_SUPPORTS_READ" TYPE="STRING" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="59" NAME="C_M_AXI_MM2S_SUPPORTS_WRITE" TYPE="STRING" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="60" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="61" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="62" NAME="C_M_AXI_S2MM_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="63" NAME="C_M_AXI_S2MM_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="64" NAME="C_M_AXI_S2MM_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="65" NAME="C_M_AXI_S2MM_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="66" NAME="C_M_AXI_S2MM_SUPPORTS_WRITE" TYPE="STRING" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_M_AXI_S2MM_SUPPORTS_READ" TYPE="STRING" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="68" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_M_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_VID_DATA"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXIS_S2MM_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_VID_DATA"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="142857132" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="m_axis_mm2s_aclk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="82" NAME="mm2s_fsync_out" SIGNAME="axi_vdma_0_mm2s_fsync_out">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="vdma_fs_ret"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="85" NAME="mm2s_buffer_almost_empty" SIGNAME="axi_vdma_0_mm2s_buffer_almost_empty">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="vdma_almost_empty"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="84" NAME="mm2s_buffer_empty" SIGNAME="axi_vdma_0_mm2s_buffer_empty">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="vdma_empty"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="79" NAME="mm2s_fsync" SIGNAME="axi_hdmi_tx_16b_0_vdma_fs">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="vdma_fs"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" CLKFREQUENCY="142857132" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="m_axi_mm2s_aclk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="93" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_vdma_0_mm2s_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1" NAME="m_axi_sg_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="3" NAME="m_axi_s2mm_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="5" NAME="s_axis_s2mm_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_LITE:M_AXI_SG:M_AXI_MM2S:M_AXI_S2MM:M_AXIS_MM2S:S_AXIS_S2MM" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="6" NAME="axi_resetn" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="s_axi_lite_awvalid" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="s_axi_lite_awready" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="9" MSB="8" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="10" NAME="s_axi_lite_wvalid" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="11" NAME="s_axi_lite_wready" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="14" NAME="s_axi_lite_bvalid" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="15" NAME="s_axi_lite_bready" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="16" NAME="s_axi_lite_arvalid" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="17" NAME="s_axi_lite_arready" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="18" MSB="8" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="19" NAME="s_axi_lite_rvalid" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="20" NAME="s_axi_lite_rready" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="m_axi_sg_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_SG_ADDR_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="24" MSB="7" NAME="m_axi_sg_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="25" MSB="2" NAME="m_axi_sg_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="m_axi_sg_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="27" MSB="2" NAME="m_axi_sg_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="28" MSB="3" NAME="m_axi_sg_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="m_axi_sg_arvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="m_axi_sg_arready" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="31" MSB="31" NAME="m_axi_sg_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_SG_DATA_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="32" MSB="1" NAME="m_axi_sg_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="m_axi_sg_rlast" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="m_axi_sg_rvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="35" NAME="m_axi_sg_rready" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="36" MSB="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARADDR" VECFORMULA="[C_M_AXI_MM2S_ADDR_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARLEN" VECFORMULA="[7:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="38" MSB="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="40" MSB="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="41" MSB="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_ARVALID" DIR="O" MPD_INDEX="42" NAME="m_axi_mm2s_arvalid" SIGNAME="axi_interconnect_2_S_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_ARREADY" DIR="I" MPD_INDEX="43" NAME="m_axi_mm2s_arready" SIGNAME="axi_interconnect_2_S_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="44" MSB="63" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGNAME="axi_interconnect_2_S_RDATA" VECFORMULA="[C_M_AXI_MM2S_DATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGNAME="axi_interconnect_2_S_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_RLAST" DIR="I" MPD_INDEX="46" NAME="m_axi_mm2s_rlast" SIGNAME="axi_interconnect_2_S_RLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_RVALID" DIR="I" MPD_INDEX="47" NAME="m_axi_mm2s_rvalid" SIGNAME="axi_interconnect_2_S_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_2_S_RREADY" DIR="O" MPD_INDEX="48" NAME="m_axi_mm2s_rready" SIGNAME="axi_interconnect_2_S_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_2" PORT="S_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="49" NAME="mm2s_prmry_reset_out_n" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="50" MSB="63" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TDATA" VECFORMULA="[C_M_AXIS_MM2S_TDATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_hdmi_tx_16b_0" PORT="M_AXIS_MM2S_TDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TKEEP" VECFORMULA="[(C_M_AXIS_MM2S_TDATA_WIDTH/8)-1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_hdmi_tx_16b_0" PORT="M_AXIS_MM2S_TKEEP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TVALID" DIR="O" MPD_INDEX="52" NAME="m_axis_mm2s_tvalid" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_hdmi_tx_16b_0" PORT="M_AXIS_MM2S_TVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TREADY" DIR="I" MPD_INDEX="53" NAME="m_axis_mm2s_tready" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_hdmi_tx_16b_0" PORT="M_AXIS_MM2S_TREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TLAST" DIR="O" MPD_INDEX="54" NAME="m_axis_mm2s_tlast" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_hdmi_tx_16b_0" PORT="M_AXIS_MM2S_TLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TUSER" DIR="O" MPD_INDEX="55" NAME="m_axis_mm2s_tuser" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TUSER" VECFORMULA="[C_M_AXIS_MM2S_TUSER_BITS-1:0]">
          <CONNECTIONS/>
        </PORT>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="56" MSB="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_S2MM_ADDR_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="57" MSB="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="58" MSB="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="59" MSB="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="60" MSB="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="61" MSB="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="m_axi_s2mm_awvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="63" NAME="m_axi_s2mm_awready" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="64" MSB="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_S2MM_DATA_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="65" MSB="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_S2MM_DATA_WIDTH/8)-1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="m_axi_s2mm_wlast" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="m_axi_s2mm_wvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="m_axi_s2mm_wready" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="69" MSB="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="70" NAME="m_axi_s2mm_bvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="m_axi_s2mm_bready" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="72" NAME="s2mm_prmry_reset_out_n" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXIS_S2MM_TDATA_WIDTH-1:0]"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="74" MSB="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXIS_S2MM_TDATA_WIDTH/8)-1:0]"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="s_axis_s2mm_tvalid" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="76" NAME="s_axis_s2mm_tready" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="s_axis_s2mm_tlast" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="s_axis_s2mm_tuser" SIGNAME="__NOC__" VECFORMULA="[C_S_AXIS_S2MM_TUSER_BITS-1:0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="80" MSB="5" NAME="mm2s_frame_ptr_in" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_MM2S_GENLOCK_NUM_MASTERS*6)-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="81" MSB="5" NAME="mm2s_frame_ptr_out" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
        <PORT DIR="O" MPD_INDEX="83" NAME="mm2s_prmtr_update" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="86" NAME="s2mm_fsync" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="87" MSB="5" NAME="s2mm_frame_ptr_in" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2MM_GENLOCK_NUM_MASTERS*6)-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="88" MSB="5" NAME="s2mm_frame_ptr_out" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
        <PORT DIR="O" MPD_INDEX="89" NAME="s2mm_fsync_out" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="90" NAME="s2mm_buffer_full" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="91" NAME="s2mm_buffer_almost_full" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="92" NAME="s2mm_prmtr_update" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="94" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="95" MSB="63" NAME="axi_vdma_tstvec" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_interconnect_2" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="M_AXI_MM2S" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_araddr"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arlen"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arsize"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arburst"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arprot"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arcache"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_arready"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rdata"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rresp"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rlast"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rvalid"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="M_AXI_SG" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_araddr"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arlen"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arsize"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arburst"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arprot"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arcache"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_arready"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rdata"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rresp"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rlast"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rvalid"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="M_AXI_S2MM" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awaddr"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awlen"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awsize"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awburst"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awprot"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awcache"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_awready"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wdata"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wstrb"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wlast"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_wready"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bresp"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bvalid"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_bready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_vdma_0_M_AXIS_MM2S" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="M_AXIS_MM2S" PROTOCOL="XIL_AXI_STREAM_VID_DATA" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tdata"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tkeep"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tready"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tlast"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tuser"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="5" NAME="S_AXIS_S2MM" PROTOCOL="XIL_AXI_STREAM_VID_DATA" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tdata"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tkeep"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axis_s2mm_tready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tlast"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tuser"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1124073472" BASENAME="C_BASEADDR" BASEVALUE="0x43000000" HIGHDECIMAL="1124139007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4300ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_LITE"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.06.a" INSTANCE="axi_interconnect_1" IPTYPE="BUS" MHS_INDEX="2" MODCLASS="BUS" MODTYPE="axi_interconnect">
      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768_axi_interconnect.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="12"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000020000000200000002000000020000000200000002000000020000000200000002"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="[encoded data, 4098 characters]"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="[encoded data, 4098 characters]"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000100000001000000010000000105f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e10005f5e100"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="processing_system7_0_FCLK_RESET0_N">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_RESET0_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_interconnect_1_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="3" MSB="8" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE:M_AXI_MM2S:M_AXIS_MM2S]" INSTANCE="axi_vdma_0" PORT="axi_resetn"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_ARESETN"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE:M_AXI_MM2S:M_AXIS_MM2S]" INSTANCE="axi_vdma_1" PORT="axi_resetn"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi_interconnect_1_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="6" MSB="11" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_1_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi_interconnect_1_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_WID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="18" MSB="11" NAME="S_AXI_WID" RIGHT="0" SIGNAME="axi_interconnect_1_S_WID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_WLAST" DIR="I" MPD_INDEX="21" NAME="S_AXI_WLAST" SIGNAME="axi_interconnect_1_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_WUSER" DIR="I" MPD_INDEX="22" NAME="S_AXI_WUSER" SIGNAME="axi_interconnect_1_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_WVALID" DIR="I" MPD_INDEX="23" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_WREADY" DIR="O" MPD_INDEX="24" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="25" MSB="11" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi_interconnect_1_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_BUSER" DIR="O" MPD_INDEX="27" NAME="S_AXI_BUSER" SIGNAME="axi_interconnect_1_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_BVALID" DIR="O" MPD_INDEX="28" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_BREADY" DIR="I" MPD_INDEX="29" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="30" MSB="11" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="31" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="32" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="35" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="38" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_1_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARUSER" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARUSER" SIGNAME="axi_interconnect_1_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARVALID" DIR="I" MPD_INDEX="40" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_ARREADY" DIR="O" MPD_INDEX="41" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="42" MSB="11" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi_interconnect_1_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="43" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_RLAST" DIR="O" MPD_INDEX="45" NAME="S_AXI_RLAST" SIGNAME="axi_interconnect_1_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_RUSER" DIR="O" MPD_INDEX="46" NAME="S_AXI_RUSER" SIGNAME="axi_interconnect_1_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_RVALID" DIR="O" MPD_INDEX="47" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_S_RREADY" DIR="I" MPD_INDEX="48" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_GP0]" INSTANCE="processing_system7_0" PORT="M_AXI_GP0_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ACLK" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="49" MSB="8" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="axi_interconnect_1_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="107" LSB="0" MPD_INDEX="50" MSB="107" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="287" LSB="0" MPD_INDEX="51" MSB="287" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_awaddr"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_AWADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_awaddr"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="71" LSB="0" MPD_INDEX="52" MSB="71" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="26" LSB="0" MPD_INDEX="53" MSB="26" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="54" MSB="17" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="55" MSB="17" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="56" MSB="35" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="26" LSB="0" MPD_INDEX="57" MSB="26" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="58" MSB="35" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="59" MSB="35" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="60" MSB="8" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="61" MSB="8" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_awvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_AWVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_awvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="62" MSB="8" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_awready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_AWREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_awready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="107" LSB="0" MPD_INDEX="63" MSB="107" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi_interconnect_1_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="287" LSB="0" MPD_INDEX="64" MSB="287" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_wdata"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_WDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_wdata"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="65" MSB="35" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_WSTRB"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="66" MSB="8" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi_interconnect_1_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="67" MSB="8" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="68" MSB="8" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_wvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_WVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_wvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="69" MSB="8" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_wready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_WREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_wready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="107" LSB="0" MPD_INDEX="70" MSB="107" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi_interconnect_1_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="71" MSB="17" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_bresp"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_BRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_bresp"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="72" MSB="8" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="73" MSB="8" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_bvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_BVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_bvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="74" MSB="8" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_bready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_BREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_bready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="107" LSB="0" MPD_INDEX="75" MSB="107" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="287" LSB="0" MPD_INDEX="76" MSB="287" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_araddr"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_ARADDR"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_araddr"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="71" LSB="0" MPD_INDEX="77" MSB="71" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="26" LSB="0" MPD_INDEX="78" MSB="26" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="79" MSB="17" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="80" MSB="17" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="81" MSB="35" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="26" LSB="0" MPD_INDEX="82" MSB="26" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="83" MSB="35" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="84" MSB="35" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="85" MSB="8" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="86" MSB="8" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_arvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_ARVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_arvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="87" MSB="8" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_arready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_ARREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_arready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="107" LSB="0" MPD_INDEX="88" MSB="107" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi_interconnect_1_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="287" LSB="0" MPD_INDEX="89" MSB="287" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_rdata"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_RDATA"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_rdata"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="17" LSB="0" MPD_INDEX="90" MSB="17" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_rresp"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_RRESP"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_rresp"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="91" MSB="8" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi_interconnect_1_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="92" MSB="8" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi_interconnect_1_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="93" MSB="8" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi_interconnect_1_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_rvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_RVALID"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_rvalid"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="94" MSB="8" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi_interconnect_1_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_0" PORT="s_axi_lite_rready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_hdmi_tx_16b_0" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_spdif_tx_0" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_0" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_clkgen_0" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_i2s_adi_0" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_iic_1" PORT="S_AXI_RREADY"/>
            <CONNECTION BUSINTERFACE="[S_AXI_LITE]" INSTANCE="axi_vdma_1" PORT="s_axi_lite_rready"/>
            <CONNECTION BUSINTERFACE="[S_AXI]" INSTANCE="axi_ad7303_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="95" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="96" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="101" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="105" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="110" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="111" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="116" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="117" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="118" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="122" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="123" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="124" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="125" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="138" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
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        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="140" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
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        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="142" MSB="34" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="143" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
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        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="149" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="150" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="151" MSB="34" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="153" MSB="34" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="154" MSB="15" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="155" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="156" MSB="16" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="157" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="158" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="159" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="160" MSB="34" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="161" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="162" MSB="34" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="163" MSB="15" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="164" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="165" MSB="16" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="166" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="167" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="168" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="169" MSB="34" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="170" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="171" MSB="34" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="172" MSB="15" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="173" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="174" MSB="16" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="175" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="176" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="178" MSB="34" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="179" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="180" MSB="34" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="181" MSB="15" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="182" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="183" MSB="16" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="184" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="185" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="187" MSB="34" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="189" MSB="34" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="190" MSB="15" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="192" MSB="16" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="193" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="194" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="195" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="196" MSB="34" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="197" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="34" LSB="0" MPD_INDEX="198" MSB="34" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="199" MSB="15" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="200" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="16" LSB="0" MPD_INDEX="201" MSB="16" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="202" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="203" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.06.a" INSTANCE="axi_interconnect_2" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="axi_interconnect">
      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768_axi_interconnect.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000040"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000040"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="[encoded data, 4098 characters]"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="[encoded data, 4098 characters]"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010883d3ac"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010883d3ac"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="142857132"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="142857132" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="processing_system7_0_FCLK_RESET1_N">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_RESET1_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_interconnect_2_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_interconnect_2_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi_interconnect_2_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi_interconnect_2_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_2_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_2_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_2_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_2_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_2_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_2_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_2_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_2_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi_interconnect_2_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_2_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_2_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_WID" DIR="I" MPD_INDEX="18" NAME="S_AXI_WID" SIGNAME="axi_interconnect_2_S_WID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="19" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_2_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="20" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_2_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_WLAST" DIR="I" MPD_INDEX="21" NAME="S_AXI_WLAST" SIGNAME="axi_interconnect_2_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_WUSER" DIR="I" MPD_INDEX="22" NAME="S_AXI_WUSER" SIGNAME="axi_interconnect_2_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_WVALID" DIR="I" MPD_INDEX="23" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_2_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_WREADY" DIR="O" MPD_INDEX="24" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_2_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_BID" DIR="O" MPD_INDEX="25" NAME="S_AXI_BID" SIGNAME="axi_interconnect_2_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_2_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_BUSER" DIR="O" MPD_INDEX="27" NAME="S_AXI_BUSER" SIGNAME="axi_interconnect_2_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_BVALID" DIR="O" MPD_INDEX="28" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_2_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_BREADY" DIR="I" MPD_INDEX="29" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_2_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARID" DIR="I" MPD_INDEX="30" NAME="S_AXI_ARID" SIGNAME="axi_interconnect_2_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="31" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="32" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="35" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="38" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_2_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARUSER" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARUSER" SIGNAME="axi_interconnect_2_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARVALID" DIR="I" MPD_INDEX="40" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_2_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_ARREADY" DIR="O" MPD_INDEX="41" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_2_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_RID" DIR="O" MPD_INDEX="42" NAME="S_AXI_RID" SIGNAME="axi_interconnect_2_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="43" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_2_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_2_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_RLAST" DIR="O" MPD_INDEX="45" NAME="S_AXI_RLAST" SIGNAME="axi_interconnect_2_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_RUSER" DIR="O" MPD_INDEX="46" NAME="S_AXI_RUSER" SIGNAME="axi_interconnect_2_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_RVALID" DIR="O" MPD_INDEX="47" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_2_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_S_RREADY" DIR="I" MPD_INDEX="48" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_2_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axi_mm2s_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ACLK" DIR="I" MPD_INDEX="49" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="axi_interconnect_2_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWID" DIR="O" MPD_INDEX="50" NAME="M_AXI_AWID" SIGNAME="axi_interconnect_2_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="51" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="52" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="53" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="55" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="56" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="57" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="59" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_2_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWUSER" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWUSER" SIGNAME="axi_interconnect_2_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWVALID" DIR="O" MPD_INDEX="61" NAME="M_AXI_AWVALID" SIGNAME="axi_interconnect_2_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_AWREADY" DIR="I" MPD_INDEX="62" NAME="M_AXI_AWREADY" SIGNAME="axi_interconnect_2_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_WID" DIR="O" MPD_INDEX="63" NAME="M_AXI_WID" SIGNAME="axi_interconnect_2_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="64" MSB="63" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_2_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="65" MSB="7" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_2_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_WLAST" DIR="O" MPD_INDEX="66" NAME="M_AXI_WLAST" SIGNAME="axi_interconnect_2_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_WUSER" DIR="O" MPD_INDEX="67" NAME="M_AXI_WUSER" SIGNAME="axi_interconnect_2_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_WVALID" DIR="O" MPD_INDEX="68" NAME="M_AXI_WVALID" SIGNAME="axi_interconnect_2_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_WREADY" DIR="I" MPD_INDEX="69" NAME="M_AXI_WREADY" SIGNAME="axi_interconnect_2_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_BID" DIR="I" MPD_INDEX="70" NAME="M_AXI_BID" SIGNAME="axi_interconnect_2_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="71" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_2_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_BUSER" DIR="I" MPD_INDEX="72" NAME="M_AXI_BUSER" SIGNAME="axi_interconnect_2_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_BVALID" DIR="I" MPD_INDEX="73" NAME="M_AXI_BVALID" SIGNAME="axi_interconnect_2_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_BREADY" DIR="O" MPD_INDEX="74" NAME="M_AXI_BREADY" SIGNAME="axi_interconnect_2_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARID" DIR="O" MPD_INDEX="75" NAME="M_AXI_ARID" SIGNAME="axi_interconnect_2_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="77" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="78" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="80" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="82" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="84" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_2_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARUSER" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARUSER" SIGNAME="axi_interconnect_2_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARVALID" DIR="O" MPD_INDEX="86" NAME="M_AXI_ARVALID" SIGNAME="axi_interconnect_2_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_ARREADY" DIR="I" MPD_INDEX="87" NAME="M_AXI_ARREADY" SIGNAME="axi_interconnect_2_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_RID" DIR="I" MPD_INDEX="88" NAME="M_AXI_RID" SIGNAME="axi_interconnect_2_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="89" MSB="63" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_2_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="90" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_2_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_RLAST" DIR="I" MPD_INDEX="91" NAME="M_AXI_RLAST" SIGNAME="axi_interconnect_2_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_RUSER" DIR="I" MPD_INDEX="92" NAME="M_AXI_RUSER" SIGNAME="axi_interconnect_2_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_RVALID" DIR="I" MPD_INDEX="93" NAME="M_AXI_RVALID" SIGNAME="axi_interconnect_2_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_2_M_RREADY" DIR="O" MPD_INDEX="94" NAME="M_AXI_RREADY" SIGNAME="axi_interconnect_2_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP0]" INSTANCE="processing_system7_0" PORT="S_AXI_HP0_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="95" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="96" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="101" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="105" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="110" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="111" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="115" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="116" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="117" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="118" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="122" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="123" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="124" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="125" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="137" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="138" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="139" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="140" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="141" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="142" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="143" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="144" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="145" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="146" MSB="63" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="147" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="148" MSB="63" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="149" MSB="10" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="150" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="151" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="153" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="154" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="155" MSB="63" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="156" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="157" MSB="63" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="158" MSB="10" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="159" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="160" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="161" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="162" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="163" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="164" MSB="63" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="165" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="166" MSB="63" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="167" MSB="10" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="168" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="169" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="170" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="171" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="172" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="173" MSB="63" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="174" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="175" MSB="63" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="176" MSB="10" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="178" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="179" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="180" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="181" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="182" MSB="63" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="183" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="184" MSB="63" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="185" MSB="10" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="187" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="189" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="190" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="191" MSB="63" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="192" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="193" MSB="63" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="194" MSB="10" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="195" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="196" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="197" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="198" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="199" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="200" MSB="63" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="201" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="202" MSB="63" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="203" MSB="10" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="axi_hdmi_tx_16b_0" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="PERIPHERAL" MODTYPE="axi_hdmi_tx_16b">
      <DESCRIPTION TYPE="SHORT">AXI_HDMI_TX_16B</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_development"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x70e00000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x70e0ffff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="13" NAME="C_M_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_VID_DATA"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="14" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="hdmi_ref_clk" SIGIS="CLK" SIGNAME="axi_hdmi_tx_16b_0_hdmi_ref_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_clkgen_0" PORT="clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="hdmi_clk" SIGNAME="axi_hdmi_tx_16b_0_hdmi_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="hdmi_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="15" LSB="0" MHS_INDEX="3" MPD_INDEX="5" MSB="15" NAME="hdmi_data" RIGHT="0" SIGNAME="axi_hdmi_tx_16b_0_hdmi_data" VECFORMULA="[15:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="hdmi_data"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="3" NAME="hdmi_hsync" SIGNAME="axi_hdmi_tx_16b_0_hdmi_hsync">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="hdmi_hsync"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="hdmi_vsync" SIGNAME="axi_hdmi_tx_16b_0_hdmi_vsync">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="hdmi_vsync"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="4" NAME="hdmi_data_e" SIGNAME="axi_hdmi_tx_16b_0_hdmi_data_e">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="hdmi_data_e"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="142857132" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="6" NAME="vdma_clk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="7" NAME="vdma_fs" SIGNAME="axi_hdmi_tx_16b_0_vdma_fs">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_vdma_0" PORT="mm2s_fsync"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="vdma_fs_ret" SIGNAME="axi_vdma_0_mm2s_fsync_out">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_vdma_0" PORT="mm2s_fsync_out"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="9" NAME="vdma_empty" SIGNAME="axi_vdma_0_mm2s_buffer_empty">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_vdma_0" PORT="mm2s_buffer_empty"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="10" NAME="vdma_almost_empty" SIGNAME="axi_vdma_0_mm2s_buffer_almost_empty">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_vdma_0" PORT="mm2s_buffer_almost_empty"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="11" MSB="7" NAME="up_status" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="debug_trigger" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="13" MSB="63" NAME="debug_data" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="15" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="21" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="23" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="24" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="25" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="26" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="28" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="29" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="31" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="32" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TVALID" DIR="I" MPD_INDEX="33" NAME="M_AXIS_MM2S_TVALID" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axis_mm2s_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="34" MSB="7" NAME="M_AXIS_MM2S_TKEEP" RIGHT="0" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TKEEP" VECFORMULA="[7:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axis_mm2s_tkeep"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="35" MSB="63" NAME="M_AXIS_MM2S_TDATA" RIGHT="0" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TDATA" VECFORMULA="[63:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axis_mm2s_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TLAST" DIR="I" MPD_INDEX="36" NAME="M_AXIS_MM2S_TLAST" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axis_mm2s_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_0_M_AXIS_MM2S_TREADY" DIR="O" MPD_INDEX="37" NAME="M_AXIS_MM2S_TREADY" SIGNAME="axi_vdma_0_M_AXIS_MM2S_TREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_0" PORT="m_axis_mm2s_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_vdma_0_M_AXIS_MM2S" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="M_AXIS_MM2S" PROTOCOL="XIL_AXI_STREAM_VID_DATA" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="M_AXIS_MM2S_TVALID"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXIS_MM2S_TKEEP"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXIS_MM2S_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXIS_MM2S_TLAST"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXIS_MM2S_TREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1893728256" BASENAME="C_BASEADDR" BASEVALUE="0x70e00000" HIGHDECIMAL="1893793791" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x70e0ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="axi_spdif_tx_0" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="PERIPHERAL" MODTYPE="axi_spdif_tx">
      <DESCRIPTION TYPE="SHORT">AXI_SPDIF_TX</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_development"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x75c00000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x75c0ffff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="6" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="7" NAME="C_S_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="8" NAME="C_DMA_TYPE" TYPE="INTEGER" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="35" NAME="spdif_tx_o" SIGNAME="axi_spdif_tx_0_spdif_tx_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="hdmi_spdif"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="12288135" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="34" NAME="spdif_data_clk" SIGIS="CLK" SIGNAME="clock_generator_0_CLKOUT0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="25" NAME="DMA_REQ_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="26" NAME="DMA_REQ_RSTN" SIGNAME="processing_system7_0_DMA0_RSTN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_RSTN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="4" MPD_INDEX="28" MSB="1" NAME="DMA_REQ_DATYPE" RIGHT="0" SIGNAME="processing_system7_0_DMA0_DATYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_DATYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="27" NAME="DMA_REQ_DAVALID" SIGNAME="processing_system7_0_DMA0_DAVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_DAVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="29" NAME="DMA_REQ_DRREADY" SIGNAME="processing_system7_0_DMA0_DRREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_DRREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="33" NAME="DMA_REQ_DAREADY" SIGNAME="axi_spdif_tx_0_DMA_REQ_DAREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_DAREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="32" NAME="DMA_REQ_DRLAST" SIGNAME="axi_spdif_tx_0_DMA_REQ_DRLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_DRLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="9" MPD_INDEX="31" MSB="1" NAME="DMA_REQ_DRTYPE" RIGHT="0" SIGNAME="axi_spdif_tx_0_DMA_REQ_DRTYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_DRTYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="30" NAME="DMA_REQ_DRVALID" SIGNAME="axi_spdif_tx_0_DMA_REQ_DRVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA0_REQ]" INSTANCE="processing_system7_0" PORT="DMA0_DRVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="5" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="6" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="7" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="10" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="19" NAME="S_AXIS_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="20" NAME="S_AXIS_ARESETN" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="21" NAME="S_AXIS_TREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="23" NAME="S_AXIS_TLAST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="24" NAME="S_AXIS_TVALID" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXIS_MM2S" PROTOCOL="XIL_AXI_STREAM_ETH_DATA" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_ARESETN"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXIS_TREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_TVALID"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="DMA_REQ" TYPE="XIL_DMA_REQ_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_RSTN"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_DATYPE"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_DAVALID"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_DRREADY"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_DAREADY"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_DRLAST"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_DRTYPE"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_DRVALID"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1975517184" BASENAME="C_BASEADDR" BASEVALUE="0x75c00000" HIGHDECIMAL="1975582719" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x75c0ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.02.a" INSTANCE="axi_iic_0" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="PERIPHERAL" MODTYPE="axi_iic">
      <DESCRIPTION TYPE="SHORT">AXI IIC Interface</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">AXI interface to Philips I2C bus v2.1</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="axi_iic_0"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41600000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4160ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_IIC_FREQ" TYPE="INTEGER" VALUE="100000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_TEN_BIT_ADR" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_GPO_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SCL_INERTIAL_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SDA_INERTIAL_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_SDA_LEVEL" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="13" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="IIC2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_iic_0_IIC2INTC_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="iic_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="20" NAME="Sda_I" SIGNAME="util_i2c_mixer_0_upstream_sda_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="util_i2c_mixer_0" PORT="upstream_sda_O"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="iic_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="21" NAME="Sda_O" SIGNAME="axi_iic_0_Sda_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="util_i2c_mixer_0" PORT="upstream_sda_I"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="iic_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="22" NAME="Sda_T" SIGNAME="axi_iic_0_Sda_T">
          <CONNECTIONS>
            <CONNECTION INSTANCE="util_i2c_mixer_0" PORT="upstream_sda_T"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="iic_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="23" NAME="Scl_I" SIGNAME="util_i2c_mixer_0_upstream_scl_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="util_i2c_mixer_0" PORT="upstream_scl_O"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="iic_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="24" NAME="Scl_O" SIGNAME="axi_iic_0_Scl_O">
          <CONNECTIONS>
            <CONNECTION INSTANCE="util_i2c_mixer_0" PORT="upstream_scl_I"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="iic_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="25" NAME="Scl_T" SIGNAME="axi_iic_0_Scl_T">
          <CONNECTIONS>
            <CONNECTION INSTANCE="util_i2c_mixer_0" PORT="upstream_scl_T"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="3" MSB="8" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="13" MSB="8" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="26" NAME="Gpo" SIGNAME="__NOC__" VECFORMULA="[(C_GPO_WIDTH-1):0]">
          <DESCRIPTION>IIC General Purpose Output</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" IOS="iic_0" IS_THREE_STATE="TRUE" MPD_INDEX="27" NAME="Sda" SIGNAME="__NOC__" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
          <DESCRIPTION>IIC Serial Data</DESCRIPTION>
        </PORT>
        <PORT DIR="IO" IOS="iic_0" IS_THREE_STATE="TRUE" MPD_INDEX="28" NAME="Scl" SIGNAME="__NOC__" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
          <DESCRIPTION>IIC Serial Clock</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="iic_0" TYPE="XIL_AXI_IIC_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="Sda_I"/>
            <PORTMAP DIR="O" PHYSICAL="Sda_O"/>
            <PORTMAP DIR="O" PHYSICAL="Sda_T"/>
            <PORTMAP DIR="I" PHYSICAL="Scl_I"/>
            <PORTMAP DIR="O" PHYSICAL="Scl_O"/>
            <PORTMAP DIR="O" PHYSICAL="Scl_T"/>
            <PORTMAP DIR="O" PHYSICAL="Gpo"/>
            <PORTMAP DIR="IO" PHYSICAL="Sda"/>
            <PORTMAP DIR="IO" PHYSICAL="Scl"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1096810496" BASENAME="C_BASEADDR" BASEVALUE="0x41600000" HIGHDECIMAL="1096876031" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4160ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="axi_clkgen_0" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="PERIPHERAL" MODTYPE="axi_clkgen">
      <DESCRIPTION TYPE="SHORT">AXI_CLKGEN</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_development"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x000001ff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_USE_WSTRB" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="4" NAME="C_DPHASE_TIMEOUT" TYPE="INTEGER" VALUE="8"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x79000000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7900ffff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_NUM_REG" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_NUM_MEM" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SLV_AWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SLV_DWIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_MMCM_TYPE" TYPE="INTEGER" VALUE="0"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="ref_clk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK2"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="clk" SIGIS="CLK" SIGNAME="axi_hdmi_tx_16b_0_hdmi_ref_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_hdmi_tx_16b_0" PORT="hdmi_ref_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="3" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="5" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="9" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="10" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="13" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="14" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="15" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="16" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="18" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="19" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="20" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2030043136" BASENAME="C_BASEADDR" BASEVALUE="0x79000000" HIGHDECIMAL="2030108671" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7900ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="4.03.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="IP" MODTYPE="clock_generator">
      <DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_generator.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="7z020"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="clg484"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="12288135"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="REAL" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="94" NAME="C_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="95" NAME="C_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="96" NAME="C_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="97" NAME="C_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="98" NAME="C_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="99" NAME="C_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="100" NAME="C_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="101" NAME="C_CLKOUT7_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="102" NAME="C_CLKOUT8_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="103" NAME="C_CLKOUT9_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="104" NAME="C_CLKOUT10_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="105" NAME="C_CLKOUT11_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="106" NAME="C_CLKOUT12_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="107" NAME="C_CLKOUT13_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="108" NAME="C_CLKOUT14_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="109" NAME="C_CLKOUT15_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="110" NAME="C_CLK_GEN" VALUE="UPDATE"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="net_gnd">
          <CONNECTIONS>
            <CONNECTION INSTANCE="net_gnd"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="12288135" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="clock_generator_0_CLKOUT0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_i2s_adi_0_MCLK_pin"/>
            <CONNECTION INSTANCE="axi_spdif_tx_0" PORT="spdif_data_clk"/>
            <CONNECTION INSTANCE="axi_i2s_adi_0" PORT="DATA_CLK_I"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK2"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="24" NAME="LOCKED" SIGNAME="__NOC__"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="util_vector_logic_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="IP" MODTYPE="util_vector_logic">
      <DESCRIPTION TYPE="SHORT">Utility Vector Logic</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">'Simple logic functions, and, or, xor, not.'</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="D:/Xilinx/14.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/util_vector_logic_v1_00_a/doc/util_vector_logic.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_preferred"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_OPERATION" TYPE="string" VALUE="not"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_SIZE" TYPE="INTEGER" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="Res" SIGNAME="util_vector_logic_0_Res" VECFORMULA="[0:C_SIZE-1]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[USBIND_0]" INSTANCE="processing_system7_0" PORT="USB0_VBUS_PWRFAULT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="Op1" SIGNAME="net_otg_oc" VECFORMULA="[0:C_SIZE-1]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="otg_vbusoc"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" MPD_INDEX="1" NAME="Op2" SIGNAME="__NOC__" VECFORMULA="[0:C_SIZE-1]"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="axi_i2s_adi_0" IPTYPE="PERIPHERAL" MHS_INDEX="10" MODCLASS="PERIPHERAL" MODTYPE="axi_i2s_adi">
      <DESCRIPTION TYPE="SHORT">AXI_I2S_ADI</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_development"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_SLOT_WIDTH" TYPE="INTEGER" VALUE="24"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_LRCLK_POL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_BCLK_POL" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="3" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="5" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x77600000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="6" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7760ffff"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="8" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="9" NAME="C_S_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="10" NAME="C_M_AXIS_S2MM_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="11" NAME="C_DMA_TYPE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_NUM_CH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_HAS_TX" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_HAS_RX" TYPE="INTEGER" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="12288135" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="DATA_CLK_I" SIGIS="CLK" SIGNAME="clock_generator_0_CLKOUT0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clock_generator_0" PORT="CLKOUT0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="I2S" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BCLK_O" SIGNAME="axi_i2s_adi_0_BCLK_O" VECFORMULA="[C_NUM_CH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_i2s_adi_0_BCLK_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="I2S" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="LRCLK_O" SIGNAME="axi_i2s_adi_0_LRCLK_O" VECFORMULA="[C_NUM_CH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_i2s_adi_0_LRCLK_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="I2S" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="SDATA_I" SIGNAME="axi_i2s_adi_0_SDATA_I" VECFORMULA="[C_NUM_CH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_i2s_adi_0_SDATA_I_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="I2S" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="3" NAME="SDATA_O" SIGNAME="axi_i2s_adi_0_SDATA_O" VECFORMULA="[C_NUM_CH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_i2s_adi_0_SDATA_O_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="17" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="45" NAME="DMA_REQ_RX_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="36" NAME="DMA_REQ_TX_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="38" NAME="DMA_REQ_TX_DAVALID" SIGNAME="processing_system7_0_DMA1_DAVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_DAVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="9" MPD_INDEX="39" MSB="1" NAME="DMA_REQ_TX_DATYPE" RIGHT="0" SIGNAME="processing_system7_0_DMA1_DATYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_DATYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="40" NAME="DMA_REQ_TX_DRREADY" SIGNAME="processing_system7_0_DMA1_DRREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_DRREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="37" NAME="DMA_REQ_TX_RSTN" SIGNAME="processing_system7_0_DMA1_RSTN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_RSTN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="41" NAME="DMA_REQ_TX_DRVALID" SIGNAME="axi_i2s_adi_0_DMA_REQ_TX_DRVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_DRVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="13" MPD_INDEX="42" MSB="1" NAME="DMA_REQ_TX_DRTYPE" RIGHT="0" SIGNAME="axi_i2s_adi_0_DMA_REQ_TX_DRTYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_DRTYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="43" NAME="DMA_REQ_TX_DRLAST" SIGNAME="axi_i2s_adi_0_DMA_REQ_TX_DRLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_DRLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ_TX" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="44" NAME="DMA_REQ_TX_DAREADY" SIGNAME="axi_i2s_adi_0_DMA_REQ_TX_DAREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA1_REQ]" INSTANCE="processing_system7_0" PORT="DMA1_DAREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" ENDIAN="LITTLE" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="16" MPD_INDEX="48" MSB="1" NAME="DMA_REQ_RX_DATYPE" RIGHT="0" SIGNAME="processing_system7_0_DMA2_DATYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_DATYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="47" NAME="DMA_REQ_RX_DAVALID" SIGNAME="processing_system7_0_DMA2_DAVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_DAVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="49" NAME="DMA_REQ_RX_DRREADY" SIGNAME="processing_system7_0_DMA2_DRREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_DRREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="46" NAME="DMA_REQ_RX_RSTN" SIGNAME="processing_system7_0_DMA2_RSTN">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_RSTN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="52" NAME="DMA_REQ_RX_DRLAST" SIGNAME="axi_i2s_adi_0_DMA_REQ_RX_DRLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_DRLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="50" NAME="DMA_REQ_RX_DRVALID" SIGNAME="axi_i2s_adi_0_DMA_REQ_RX_DRVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_DRVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" ENDIAN="LITTLE" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" LEFT="1" LSB="0" MHS_INDEX="22" MPD_INDEX="51" MSB="1" NAME="DMA_REQ_RX_DRTYPE" RIGHT="0" SIGNAME="axi_i2s_adi_0_DMA_REQ_RX_DRTYPE" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_DRTYPE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IOS="DMA_REQ_RX" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="53" NAME="DMA_REQ_RX_DAREADY" SIGNAME="axi_i2s_adi_0_DMA_REQ_RX_DAREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[DMA2_REQ]" INSTANCE="processing_system7_0" PORT="DMA2_DAREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="5" NAME="S_AXIS_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="6" NAME="S_AXIS_ARESETN" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="7" NAME="S_AXIS_TREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="8" MSB="31" NAME="S_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="9" NAME="S_AXIS_TLAST" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_MM2S" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="10" NAME="S_AXIS_TVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="11" NAME="M_AXIS_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="M_AXIS_TVALID" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="M_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
        <PORT BUS="M_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="M_AXIS_TLAST" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="15" NAME="M_AXIS_TREADY" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="16" MSB="3" NAME="M_AXIS_TKEEP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="18" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="23" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="24" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="26" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="27" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="28" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="31" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="32" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="34" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="35" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="1" NAME="S_AXIS_MM2S" PROTOCOL="XIL_AXI_STREAM_ETH_DATA" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_ARESETN"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXIS_TREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_TDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXIS_TVALID"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="2" NAME="M_AXIS_S2MM" PROTOCOL="XIL_AXI_STREAM_ETH_DATA" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="M_AXIS_ACLK"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXIS_TVALID"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXIS_TDATA"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXIS_TLAST"/>
            <PORTMAP DIR="I" PHYSICAL="M_AXIS_TREADY"/>
            <PORTMAP DIR="O" PHYSICAL="M_AXIS_TKEEP"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="2" NAME="I2S" TYPE="I2S">
          <PORTMAPS>
            <PORTMAP DIR="O" PHYSICAL="BCLK_O"/>
            <PORTMAP DIR="O" PHYSICAL="LRCLK_O"/>
            <PORTMAP DIR="I" PHYSICAL="SDATA_I"/>
            <PORTMAP DIR="O" PHYSICAL="SDATA_O"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="1" NAME="DMA_REQ_RX" TYPE="XIL_DMA_REQ_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_RX_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_RX_DATYPE"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_RX_DAVALID"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_RX_DRREADY"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_RX_RSTN"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_RX_DRLAST"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_RX_DRVALID"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_RX_DRTYPE"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_RX_DAREADY"/>
          </PORTMAPS>
        </IOINTERFACE>
        <IOINTERFACE MPD_INDEX="0" NAME="DMA_REQ_TX" TYPE="XIL_DMA_REQ_V1">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_TX_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_TX_DAVALID"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_TX_DATYPE"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_TX_DRREADY"/>
            <PORTMAP DIR="I" PHYSICAL="DMA_REQ_TX_RSTN"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_TX_DRVALID"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_TX_DRTYPE"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_TX_DRLAST"/>
            <PORTMAP DIR="O" PHYSICAL="DMA_REQ_TX_DAREADY"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2002780160" BASENAME="C_BASEADDR" BASEVALUE="0x77600000" HIGHDECIMAL="2002845695" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7760ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="util_i2c_mixer_0" IPTYPE="PERIPHERAL" MHS_INDEX="11" MODCLASS="IP" MODTYPE="util_i2c_mixer">
      <DESCRIPTION TYPE="SHORT">UTIL_I2C_MIXER</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_development"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="C_WIDTH" TYPE="integer" VALUE="2"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="5" NAME="upstream_sda_O" SIGNAME="util_i2c_mixer_0_upstream_sda_O">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Sda_I"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="upstream_sda_I" SIGNAME="axi_iic_0_Sda_O">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Sda_O"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="upstream_sda_T" SIGNAME="axi_iic_0_Sda_T">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Sda_T"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="upstream_scl_O" SIGNAME="util_i2c_mixer_0_upstream_scl_O">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Scl_I"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="upstream_scl_I" SIGNAME="axi_iic_0_Scl_O">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Scl_O"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="0" NAME="upstream_scl_T" SIGNAME="axi_iic_0_Scl_T">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[iic_0]" INSTANCE="axi_iic_0" PORT="Scl_T"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="1" LSB="0" MHS_INDEX="6" MPD_INDEX="6" MSB="1" NAME="downstream_scl" RIGHT="0" SIGNAME="util_i2c_mixer_0_downstream_scl" VECFORMULA="[C_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="util_i2c_mixer_0_downstream_scl_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="1" LSB="0" MHS_INDEX="7" MPD_INDEX="7" MSB="1" NAME="downstream_sda" RIGHT="0" SIGNAME="util_i2c_mixer_0_downstream_sda" VECFORMULA="[C_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="util_i2c_mixer_0_downstream_sda_pin"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE HWVERSION="1.02.a" INSTANCE="axi_iic_1" IPTYPE="PERIPHERAL" MHS_INDEX="12" MODCLASS="PERIPHERAL" MODTYPE="axi_iic">
      <DESCRIPTION TYPE="SHORT">AXI IIC Interface</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">AXI interface to Philips I2C bus v2.1</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_INSTANCE" TYPE="STRING" VALUE="axi_iic_1"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x41640000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4164ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_IIC_FREQ" TYPE="INTEGER" VALUE="100000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="7" NAME="C_TEN_BIT_ADR" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_GPO_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_SCL_INERTIAL_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_SDA_INERTIAL_DELAY" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_SDA_LEVEL" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="13" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="iic_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="1" MPD_INDEX="27" NAME="Sda" SIGNAME="axi_iic_1_Sda" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
          <DESCRIPTION>IIC Serial Data</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_iic_1_Sda_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" IOS="iic_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="2" MPD_INDEX="28" NAME="Scl" SIGNAME="axi_iic_1_Scl" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
          <DESCRIPTION>IIC Serial Clock</DESCRIPTION>
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_iic_1_Scl_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="IIC2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_iic_1_IIC2INTC_Irpt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="3" MSB="8" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="13" MSB="8" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[8:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IOS="iic_0" MPD_INDEX="20" NAME="Sda_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="21" NAME="Sda_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="22" NAME="Sda_T" SIGNAME="__NOC__"/>
        <PORT DIR="I" IOS="iic_0" MPD_INDEX="23" NAME="Scl_I" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="24" NAME="Scl_O" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="25" NAME="Scl_T" SIGNAME="__NOC__"/>
        <PORT DIR="O" IOS="iic_0" MPD_INDEX="26" NAME="Gpo" SIGNAME="__NOC__" VECFORMULA="[(C_GPO_WIDTH-1):0]">
          <DESCRIPTION>IIC General Purpose Output</DESCRIPTION>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <IOINTERFACES>
        <IOINTERFACE MPD_INDEX="0" NAME="iic_0" TYPE="XIL_AXI_IIC_V1">
          <PORTMAPS>
            <PORTMAP DIR="IO" PHYSICAL="Sda"/>
            <PORTMAP DIR="IO" PHYSICAL="Scl"/>
            <PORTMAP DIR="I" PHYSICAL="Sda_I"/>
            <PORTMAP DIR="O" PHYSICAL="Sda_O"/>
            <PORTMAP DIR="O" PHYSICAL="Sda_T"/>
            <PORTMAP DIR="I" PHYSICAL="Scl_I"/>
            <PORTMAP DIR="O" PHYSICAL="Scl_O"/>
            <PORTMAP DIR="O" PHYSICAL="Scl_T"/>
            <PORTMAP DIR="O" PHYSICAL="Gpo"/>
          </PORTMAPS>
        </IOINTERFACE>
      </IOINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1097072640" BASENAME="C_BASEADDR" BASEVALUE="0x41640000" HIGHDECIMAL="1097138175" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4164ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.06.a" INSTANCE="axi_interconnect_3" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="13" MODCLASS="BUS" MODTYPE="axi_interconnect">
      <DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768_axi_interconnect.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000040"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="64"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="[encoded data, 4098 characters]"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="[encoded data, 4098 characters]"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010883d3ac"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010883d3ac"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="142857132"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008"/>
        <PARAMETER ASSIGNMENT="UPDATE" CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="UPDATE" MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="2"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI_CTRL" CLKFREQUENCY="142857132" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="processing_system7_0_FCLK_RESET1_N">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_RESET1_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_interconnect_3_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_interconnect_3_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ACLK" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="axi_interconnect_3_S_ACLK" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi_interconnect_3_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_3_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_3_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_3_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_3_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_3_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_3_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_3_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_3_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi_interconnect_3_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi_interconnect_3_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi_interconnect_3_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_WID" DIR="I" MPD_INDEX="18" NAME="S_AXI_WID" SIGNAME="axi_interconnect_3_S_WID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="19" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_3_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="20" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_3_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_WLAST" DIR="I" MPD_INDEX="21" NAME="S_AXI_WLAST" SIGNAME="axi_interconnect_3_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_WUSER" DIR="I" MPD_INDEX="22" NAME="S_AXI_WUSER" SIGNAME="axi_interconnect_3_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_WVALID" DIR="I" MPD_INDEX="23" NAME="S_AXI_WVALID" SIGNAME="axi_interconnect_3_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_WREADY" DIR="O" MPD_INDEX="24" NAME="S_AXI_WREADY" SIGNAME="axi_interconnect_3_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_BID" DIR="O" MPD_INDEX="25" NAME="S_AXI_BID" SIGNAME="axi_interconnect_3_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_3_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_BUSER" DIR="O" MPD_INDEX="27" NAME="S_AXI_BUSER" SIGNAME="axi_interconnect_3_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_BVALID" DIR="O" MPD_INDEX="28" NAME="S_AXI_BVALID" SIGNAME="axi_interconnect_3_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_BREADY" DIR="I" MPD_INDEX="29" NAME="S_AXI_BREADY" SIGNAME="axi_interconnect_3_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARID" DIR="I" MPD_INDEX="30" NAME="S_AXI_ARID" SIGNAME="axi_interconnect_3_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="31" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="32" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="35" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="36" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="38" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARUSER" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARUSER" SIGNAME="axi_interconnect_3_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARVALID" DIR="I" MPD_INDEX="40" NAME="S_AXI_ARVALID" SIGNAME="axi_interconnect_3_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_ARREADY" DIR="O" MPD_INDEX="41" NAME="S_AXI_ARREADY" SIGNAME="axi_interconnect_3_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_RID" DIR="O" MPD_INDEX="42" NAME="S_AXI_RID" SIGNAME="axi_interconnect_3_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="43" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_3_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_3_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_RLAST" DIR="O" MPD_INDEX="45" NAME="S_AXI_RLAST" SIGNAME="axi_interconnect_3_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_RUSER" DIR="O" MPD_INDEX="46" NAME="S_AXI_RUSER" SIGNAME="axi_interconnect_3_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_RVALID" DIR="O" MPD_INDEX="47" NAME="S_AXI_RVALID" SIGNAME="axi_interconnect_3_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_S_RREADY" DIR="I" MPD_INDEX="48" NAME="S_AXI_RREADY" SIGNAME="axi_interconnect_3_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXI_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axi_mm2s_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ACLK" DIR="I" MPD_INDEX="49" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="axi_interconnect_3_M_ACLK" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWID" DIR="O" MPD_INDEX="50" NAME="M_AXI_AWID" SIGNAME="axi_interconnect_3_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="51" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="52" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="53" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="55" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="56" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="57" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="59" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_interconnect_3_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWUSER" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWUSER" SIGNAME="axi_interconnect_3_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWVALID" DIR="O" MPD_INDEX="61" NAME="M_AXI_AWVALID" SIGNAME="axi_interconnect_3_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_AWREADY" DIR="I" MPD_INDEX="62" NAME="M_AXI_AWREADY" SIGNAME="axi_interconnect_3_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_WID" DIR="O" MPD_INDEX="63" NAME="M_AXI_WID" SIGNAME="axi_interconnect_3_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_WID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="64" MSB="63" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_interconnect_3_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="65" MSB="7" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_interconnect_3_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_WLAST" DIR="O" MPD_INDEX="66" NAME="M_AXI_WLAST" SIGNAME="axi_interconnect_3_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_WLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_WUSER" DIR="O" MPD_INDEX="67" NAME="M_AXI_WUSER" SIGNAME="axi_interconnect_3_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_WVALID" DIR="O" MPD_INDEX="68" NAME="M_AXI_WVALID" SIGNAME="axi_interconnect_3_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_WREADY" DIR="I" MPD_INDEX="69" NAME="M_AXI_WREADY" SIGNAME="axi_interconnect_3_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_BID" DIR="I" MPD_INDEX="70" NAME="M_AXI_BID" SIGNAME="axi_interconnect_3_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_BID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="71" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_interconnect_3_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_BUSER" DIR="I" MPD_INDEX="72" NAME="M_AXI_BUSER" SIGNAME="axi_interconnect_3_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_BVALID" DIR="I" MPD_INDEX="73" NAME="M_AXI_BVALID" SIGNAME="axi_interconnect_3_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_BREADY" DIR="O" MPD_INDEX="74" NAME="M_AXI_BREADY" SIGNAME="axi_interconnect_3_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARID" DIR="O" MPD_INDEX="75" NAME="M_AXI_ARID" SIGNAME="axi_interconnect_3_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="77" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="78" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="80" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARLOCK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="82" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="84" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_interconnect_3_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARQOS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARUSER" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARUSER" SIGNAME="axi_interconnect_3_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARVALID" DIR="O" MPD_INDEX="86" NAME="M_AXI_ARVALID" SIGNAME="axi_interconnect_3_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_ARREADY" DIR="I" MPD_INDEX="87" NAME="M_AXI_ARREADY" SIGNAME="axi_interconnect_3_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_RID" DIR="I" MPD_INDEX="88" NAME="M_AXI_RID" SIGNAME="axi_interconnect_3_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_RID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="89" MSB="63" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_interconnect_3_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="90" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_interconnect_3_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_RLAST" DIR="I" MPD_INDEX="91" NAME="M_AXI_RLAST" SIGNAME="axi_interconnect_3_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_RUSER" DIR="I" MPD_INDEX="92" NAME="M_AXI_RUSER" SIGNAME="axi_interconnect_3_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]">
          <CONNECTIONS/>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_RVALID" DIR="I" MPD_INDEX="93" NAME="M_AXI_RVALID" SIGNAME="axi_interconnect_3_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT DEF_SIGNAME="axi_interconnect_3_M_RREADY" DIR="O" MPD_INDEX="94" NAME="M_AXI_RREADY" SIGNAME="axi_interconnect_3_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[S_AXI_HP1]" INSTANCE="processing_system7_0" PORT="S_AXI_HP1_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="95" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="96" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="101" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="103" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="105" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="110" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="111" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="115" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="116" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="117" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="118" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="122" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="123" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="124" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="125" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="137" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="138" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="139" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
        <PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="140" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="141" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="142" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="143" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="144" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="145" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="146" MSB="63" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="147" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="148" MSB="63" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="149" MSB="10" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="150" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="151" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="153" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="154" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="155" MSB="63" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="156" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="157" MSB="63" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="158" MSB="10" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="159" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="160" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="161" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="162" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="163" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="164" MSB="63" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="165" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="166" MSB="63" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="167" MSB="10" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="168" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="169" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="170" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="171" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="172" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="173" MSB="63" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="174" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="175" MSB="63" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="176" MSB="10" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="178" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="179" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="180" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="181" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="182" MSB="63" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="183" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="184" MSB="63" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="185" MSB="10" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="186" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="187" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="188" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="189" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="190" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="191" MSB="63" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="192" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="193" MSB="63" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="194" MSB="10" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="195" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="196" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="197" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="198" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="199" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="200" MSB="63" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="201" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="63" LSB="0" MPD_INDEX="202" MSB="63" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="10" LSB="0" MPD_INDEX="203" MSB="10" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
            <PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
            <PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_CTRL"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="5.04.a" INSTANCE="axi_vdma_1" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="axi_vdma">
      <DESCRIPTION TYPE="SHORT">AXI Video DMA</DESCRIPTION>
      <DESCRIPTION TYPE="LONG">MemoryMap to/from Stream Video Direct Memory Access for AXI</DESCRIPTION>
      <DOCUMENTATION>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdma.pdf" TYPE="IP"/>
      </DOCUMENTATION>
      <LICENSEINFO ICON_NAME="ps_core_earlyaccess"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="0" NAME="C_S_AXI_LITE_ADDR_WIDTH" TYPE="INTEGER" VALUE="9"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="1" NAME="C_S_AXI_LITE_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="C_DLYTMR_RESOLUTION" TYPE="INTEGER" VALUE="125"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="3" NAME="C_PRMRY_IS_ACLK_ASYNC" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="4" NAME="C_M_AXI_SG_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="5" NAME="C_M_AXI_SG_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="6" NAME="C_NUM_FSTORES" TYPE="INTEGER" VALUE="3"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="7" NAME="C_USE_FSYNC" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="8" NAME="C_FLUSH_ON_FSYNC" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="9" NAME="C_DYNAMIC_RESOLUTION" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="10" NAME="C_INCLUDE_SG" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="11" NAME="C_INCLUDE_INTERNAL_GENLOCK" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="12" NAME="C_ENABLE_VIDPRMTR_READS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="13" NAME="C_INCLUDE_MM2S" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="14" NAME="C_M_AXI_MM2S_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="15" NAME="C_M_AXIS_MM2S_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="16" NAME="C_INCLUDE_MM2S_DRE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="17" NAME="C_INCLUDE_MM2S_SF" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="18" NAME="C_MM2S_SOF_ENABLE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="19" NAME="C_MM2S_MAX_BURST_LENGTH" TYPE="INTEGER" VALUE="16"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="20" NAME="C_MM2S_GENLOCK_MODE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="21" NAME="C_MM2S_GENLOCK_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="22" NAME="C_MM2S_GENLOCK_REPEAT_EN" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="23" NAME="C_MM2S_LINEBUFFER_DEPTH" TYPE="INTEGER" VALUE="128"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="24" NAME="C_MM2S_LINEBUFFER_THRESH" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="25" NAME="C_M_AXI_MM2S_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="26" NAME="C_M_AXIS_MM2S_TUSER_BITS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="27" NAME="C_INCLUDE_S2MM" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="28" NAME="C_M_AXI_S2MM_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="29" NAME="C_S_AXIS_S2MM_TDATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="30" NAME="C_INCLUDE_S2MM_DRE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="31" NAME="C_INCLUDE_S2MM_SF" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="32" NAME="C_S2MM_SOF_ENABLE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="33" NAME="C_S2MM_MAX_BURST_LENGTH" TYPE="INTEGER" VALUE="16"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="34" NAME="C_S2MM_GENLOCK_MODE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="35" NAME="C_S2MM_GENLOCK_NUM_MASTERS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="36" NAME="C_S2MM_GENLOCK_REPEAT_EN" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="37" NAME="C_S2MM_LINEBUFFER_DEPTH" TYPE="INTEGER" VALUE="128"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="38" NAME="C_S2MM_LINEBUFFER_THRESH" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="39" NAME="C_M_AXI_S2MM_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="40" NAME="C_S_AXIS_S2MM_TUSER_BITS" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="41" NAME="C_FAMILY" TYPE="STRING" VALUE="zynq"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" CHANGEDBY="SYSTEM" MPD_INDEX="42" NAME="C_INSTANCE" TYPE="STRING" VALUE="axi_vdma_1"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="43" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x43040000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="REQUIRE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="44" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x4304ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="45" NAME="C_S_AXI_LITE_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="46" NAME="C_S_AXI_LITE_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="47" NAME="C_S_AXI_LITE_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="48" NAME="C_M_AXI_SG_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="49" NAME="C_M_AXI_SG_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="50" NAME="C_M_AXI_SG_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="51" NAME="C_M_AXI_SG_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="52" NAME="C_M_AXI_SG_SUPPORTS_READ" TYPE="STRING" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="53" NAME="C_M_AXI_SG_SUPPORTS_WRITE" TYPE="STRING" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="54" NAME="C_M_AXI_MM2S_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="55" NAME="C_M_AXI_MM2S_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="56" NAME="C_M_AXI_MM2S_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="57" NAME="C_M_AXI_MM2S_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="58" NAME="C_M_AXI_MM2S_SUPPORTS_READ" TYPE="STRING" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="59" NAME="C_M_AXI_MM2S_SUPPORTS_WRITE" TYPE="STRING" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="60" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="61" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="62" NAME="C_M_AXI_S2MM_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="63" NAME="C_M_AXI_S2MM_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="64" NAME="C_M_AXI_S2MM_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="65" NAME="C_M_AXI_S2MM_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="66" NAME="C_M_AXI_S2MM_SUPPORTS_WRITE" TYPE="STRING" VALUE="1"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="67" NAME="C_M_AXI_S2MM_SUPPORTS_READ" TYPE="STRING" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="68" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL_UPDATE" MPD_INDEX="69" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING" TYPE="INTEGER" VALUE="4"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="70" NAME="C_M_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_VID_DATA"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="71" NAME="C_S_AXIS_S2MM_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_VID_DATA"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI_LITE" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" CLKFREQUENCY="142857132" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="m_axi_mm2s_aclk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="142857132" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="m_axis_mm2s_aclk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="79" NAME="mm2s_fsync" SIGNAME="vdma_1_fsync">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_ad7303_0" PORT="m_axis_mm2s_fsync"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="93" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_vdma_1_mm2s_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="IRQ_F2P"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="1" NAME="m_axi_sg_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="3" NAME="m_axi_s2mm_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="5" NAME="s_axis_s2mm_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXI_LITE:M_AXI_SG:M_AXI_MM2S:M_AXI_S2MM:M_AXIS_MM2S:S_AXIS_S2MM" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="6" NAME="axi_resetn" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="s_axi_lite_awvalid" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="s_axi_lite_awready" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="9" MSB="8" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="10" NAME="s_axi_lite_wvalid" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="11" NAME="s_axi_lite_wready" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="14" NAME="s_axi_lite_bvalid" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="15" NAME="s_axi_lite_bready" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="16" NAME="s_axi_lite_arvalid" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="17" NAME="s_axi_lite_arready" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="18" MSB="8" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="19" NAME="s_axi_lite_rvalid" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="20" NAME="s_axi_lite_rready" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI_LITE" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="m_axi_sg_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_SG_ADDR_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="24" MSB="7" NAME="m_axi_sg_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="25" MSB="2" NAME="m_axi_sg_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="m_axi_sg_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="27" MSB="2" NAME="m_axi_sg_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="28" MSB="3" NAME="m_axi_sg_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="m_axi_sg_arvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="m_axi_sg_arready" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="31" MSB="31" NAME="m_axi_sg_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_SG_DATA_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="32" MSB="1" NAME="m_axi_sg_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="m_axi_sg_rlast" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="m_axi_sg_rvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_SG" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="35" NAME="m_axi_sg_rready" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="36" MSB="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARADDR" VECFORMULA="[C_M_AXI_MM2S_ADDR_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARLEN" VECFORMULA="[7:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_ARLEN"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="38" MSB="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARSIZE" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_ARSIZE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARBURST" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_ARBURST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="40" MSB="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARPROT" VECFORMULA="[2:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_ARPROT"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="41" MSB="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGNAME="axi_interconnect_3_S_ARCACHE" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_ARCACHE"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_ARVALID" DIR="O" MPD_INDEX="42" NAME="m_axi_mm2s_arvalid" SIGNAME="axi_interconnect_3_S_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_ARREADY" DIR="I" MPD_INDEX="43" NAME="m_axi_mm2s_arready" SIGNAME="axi_interconnect_3_S_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="44" MSB="31" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGNAME="axi_interconnect_3_S_RDATA" VECFORMULA="[C_M_AXI_MM2S_DATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGNAME="axi_interconnect_3_S_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_RLAST" DIR="I" MPD_INDEX="46" NAME="m_axi_mm2s_rlast" SIGNAME="axi_interconnect_3_S_RLAST">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_RLAST"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_RVALID" DIR="I" MPD_INDEX="47" NAME="m_axi_mm2s_rvalid" SIGNAME="axi_interconnect_3_S_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXI_MM2S" DEF_SIGNAME="axi_interconnect_3_S_RREADY" DIR="O" MPD_INDEX="48" NAME="m_axi_mm2s_rready" SIGNAME="axi_interconnect_3_S_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_3" PORT="S_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" MPD_INDEX="49" NAME="mm2s_prmry_reset_out_n" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TDATA" VECFORMULA="[C_M_AXIS_MM2S_TDATA_WIDTH-1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_ad7303_0" PORT="m_axis_mm2s_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="51" MSB="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TKEEP" VECFORMULA="[(C_M_AXIS_MM2S_TDATA_WIDTH/8)-1:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_ad7303_0" PORT="m_axis_mm2s_tkeep"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TVALID" DIR="O" MPD_INDEX="52" NAME="m_axis_mm2s_tvalid" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_ad7303_0" PORT="m_axis_mm2s_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TREADY" DIR="I" MPD_INDEX="53" NAME="m_axis_mm2s_tready" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_ad7303_0" PORT="m_axis_mm2s_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TLAST" DIR="O" MPD_INDEX="54" NAME="m_axis_mm2s_tlast" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_ad7303_0" PORT="m_axis_mm2s_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TUSER" DIR="O" MPD_INDEX="55" NAME="m_axis_mm2s_tuser" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TUSER" VECFORMULA="[C_M_AXIS_MM2S_TUSER_BITS-1:0]">
          <CONNECTIONS/>
        </PORT>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="56" MSB="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_S2MM_ADDR_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="57" MSB="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="58" MSB="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="59" MSB="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="60" MSB="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="61" MSB="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="62" NAME="m_axi_s2mm_awvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="63" NAME="m_axi_s2mm_awready" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="64" MSB="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M_AXI_S2MM_DATA_WIDTH-1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="65" MSB="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_S2MM_DATA_WIDTH/8)-1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="m_axi_s2mm_wlast" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="67" NAME="m_axi_s2mm_wvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="m_axi_s2mm_wready" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="69" MSB="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="70" NAME="m_axi_s2mm_bvalid" SIGNAME="__NOC__"/>
        <PORT BUS="M_AXI_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="m_axi_s2mm_bready" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="72" NAME="s2mm_prmry_reset_out_n" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXIS_S2MM_TDATA_WIDTH-1:0]"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="74" MSB="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXIS_S2MM_TDATA_WIDTH/8)-1:0]"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="s_axis_s2mm_tvalid" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="76" NAME="s_axis_s2mm_tready" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="s_axis_s2mm_tlast" SIGNAME="__NOC__"/>
        <PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="s_axis_s2mm_tuser" SIGNAME="__NOC__" VECFORMULA="[C_S_AXIS_S2MM_TUSER_BITS-1:0]"/>
        <PORT DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="80" MSB="5" NAME="mm2s_frame_ptr_in" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_MM2S_GENLOCK_NUM_MASTERS*6)-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="81" MSB="5" NAME="mm2s_frame_ptr_out" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
        <PORT DIR="O" MPD_INDEX="82" NAME="mm2s_fsync_out" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="83" NAME="mm2s_prmtr_update" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="84" NAME="mm2s_buffer_empty" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="85" NAME="mm2s_buffer_almost_empty" SIGNAME="__NOC__"/>
        <PORT DIR="I" MPD_INDEX="86" NAME="s2mm_fsync" SIGNAME="__NOC__"/>
        <PORT DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="87" MSB="5" NAME="s2mm_frame_ptr_in" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S2MM_GENLOCK_NUM_MASTERS*6)-1:0]"/>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="88" MSB="5" NAME="s2mm_frame_ptr_out" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[5:0]"/>
        <PORT DIR="O" MPD_INDEX="89" NAME="s2mm_fsync_out" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="90" NAME="s2mm_buffer_full" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="91" NAME="s2mm_buffer_almost_full" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="92" NAME="s2mm_prmtr_update" SIGNAME="__NOC__"/>
        <PORT DIR="O" MPD_INDEX="94" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
        <PORT DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="95" MSB="63" NAME="axi_vdma_tstvec" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[63:0]"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_interconnect_3" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="M_AXI_MM2S" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_araddr"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arlen"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arsize"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arburst"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arprot"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arcache"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_arready"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rdata"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rresp"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rlast"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rvalid"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="M_AXI_SG" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_araddr"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arlen"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arsize"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arburst"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arprot"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arcache"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_arvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_arready"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rdata"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rresp"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rlast"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_sg_rvalid"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_sg_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="M_AXI_S2MM" PROTOCOL="AXI4" TYPE="MASTER">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awaddr"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awlen"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awsize"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awburst"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awprot"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awcache"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_awready"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wdata"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wstrb"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wlast"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_wready"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bresp"/>
            <PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bvalid"/>
            <PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_bready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_vdma_1_M_AXIS_MM2S" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="M_AXIS_MM2S" PROTOCOL="XIL_AXI_STREAM_VID_DATA" TYPE="INITIATOR">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tdata"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tkeep"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tready"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tlast"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tuser"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="5" NAME="S_AXIS_S2MM" PROTOCOL="XIL_AXI_STREAM_VID_DATA" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tdata"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tkeep"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axis_s2mm_tready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tlast"/>
            <PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tuser"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="1124335616" BASENAME="C_BASEADDR" BASEVALUE="0x43040000" HIGHDECIMAL="1124401151" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x4304ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI_LITE"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
    <MODULE HWVERSION="1.00.a" INSTANCE="axi_ad7303_0" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_ad7303">
      <DESCRIPTION TYPE="SHORT">axi_ad7303</DESCRIPTION>
      <LICENSEINFO ICON_NAME="ps_core_development"/>
      <PARAMETERS>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="0" NAME="PCORE_ID" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="1" NAME="PCORE_DEVICE_TYPE" TYPE="INTEGER" VALUE="0"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="2" NAME="PCORE_IODELAY_GROUP" TYPE="STRING" VALUE="adc_if_delay_group"/>
        <PARAMETER ASSIGNMENT="OPTIONAL" MPD_INDEX="3" NAME="C_S_AXI_MIN_SIZE" TYPE="std_logic_vector" VALUE="0x0000ffff"/>
        <PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x77620000"/>
        <PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" ASSIGNMENT="OPTIONAL" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x7762ffff"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="6" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE"/>
        <PARAMETER ASSIGNMENT="CONSTANT" MPD_INDEX="7" NAME="C_M_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_VID_DATA"/>
      </PARAMETERS>
      <PORTS>
        <PORT BUS="S_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="13" NAME="s_axi_aclk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="142857132" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="6" NAME="m_axis_mm2s_clk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="7" NAME="m_axis_mm2s_fsync" SIGNAME="vdma_1_fsync">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_vdma_1" PORT="mm2s_fsync"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="ref_clk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="12500000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="5" NAME="tx_clk" SIGIS="CLK" SIGNAME="processing_system7_0_FCLK_CLK3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="processing_system7_0" PORT="FCLK_CLK3"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="0" NAME="cs_o" SIGNAME="axi_ad7303_0_cs_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_ad7303_0_cs_o_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="1" NAME="data0_o" SIGNAME="axi_ad7303_0_data0_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_ad7303_0_data0_o_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="2" NAME="data1_o" SIGNAME="axi_ad7303_0_data1_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_ad7303_0_data1_o_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="3" NAME="sclk_o" SIGIS="CLK" SIGNAME="axi_ad7303_0_sclk_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External Ports" PORT="axi_ad7303_0_sclk_o_pin"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TVALID" DIR="I" MPD_INDEX="8" NAME="m_axis_mm2s_tvalid" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TVALID">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axis_mm2s_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="9" MSB="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TKEEP" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axis_mm2s_tkeep"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="10" MSB="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TDATA" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axis_mm2s_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TLAST" DIR="I" MPD_INDEX="11" NAME="m_axis_mm2s_tlast" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TLAST">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axis_mm2s_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="axi_vdma_1_M_AXIS_MM2S_TREADY" DIR="O" MPD_INDEX="12" NAME="m_axis_mm2s_tready" SIGNAME="axi_vdma_1_M_AXIS_MM2S_TREADY">
          <CONNECTIONS>
            <CONNECTION BUSINTERFACE="[M_AXIS_MM2S]" INSTANCE="axi_vdma_1" PORT="m_axis_mm2s_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARESETN" DIR="I" MPD_INDEX="14" NAME="s_axi_aresetn" SIGIS="RST" SIGNAME="axi_interconnect_1_M_ARESETN">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARESET_OUT_N"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="s_axi_awaddr" RIGHT="0" SIGNAME="axi_interconnect_1_M_AWADDR" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWVALID" DIR="I" MPD_INDEX="16" NAME="s_axi_awvalid" SIGNAME="axi_interconnect_1_M_AWVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="17" MSB="31" NAME="s_axi_wdata" RIGHT="0" SIGNAME="axi_interconnect_1_M_WDATA" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="18" MSB="3" NAME="s_axi_wstrb" RIGHT="0" SIGNAME="axi_interconnect_1_M_WSTRB" VECFORMULA="[3:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WSTRB"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WVALID" DIR="I" MPD_INDEX="19" NAME="s_axi_wvalid" SIGNAME="axi_interconnect_1_M_WVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BREADY" DIR="I" MPD_INDEX="20" NAME="s_axi_bready" SIGNAME="axi_interconnect_1_M_BREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="s_axi_araddr" RIGHT="0" SIGNAME="axi_interconnect_1_M_ARADDR" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARADDR"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARVALID" DIR="I" MPD_INDEX="22" NAME="s_axi_arvalid" SIGNAME="axi_interconnect_1_M_ARVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RREADY" DIR="I" MPD_INDEX="23" NAME="s_axi_rready" SIGNAME="axi_interconnect_1_M_RREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_ARREADY" DIR="O" MPD_INDEX="24" NAME="s_axi_arready" SIGNAME="axi_interconnect_1_M_ARREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_ARREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="s_axi_rdata" RIGHT="0" SIGNAME="axi_interconnect_1_M_RDATA" VECFORMULA="[31:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RDATA"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="s_axi_rresp" RIGHT="0" SIGNAME="axi_interconnect_1_M_RRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_RVALID" DIR="O" MPD_INDEX="27" NAME="s_axi_rvalid" SIGNAME="axi_interconnect_1_M_RVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_RVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_WREADY" DIR="O" MPD_INDEX="28" NAME="s_axi_wready" SIGNAME="axi_interconnect_1_M_WREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_WREADY"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="s_axi_bresp" RIGHT="0" SIGNAME="axi_interconnect_1_M_BRESP" VECFORMULA="[1:0]">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BRESP"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_BVALID" DIR="O" MPD_INDEX="30" NAME="s_axi_bvalid" SIGNAME="axi_interconnect_1_M_BVALID">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_BVALID"/>
          </CONNECTIONS>
        </PORT>
        <PORT BUS="S_AXI" DEF_SIGNAME="axi_interconnect_1_M_AWREADY" DIR="O" MPD_INDEX="31" NAME="s_axi_awready" SIGNAME="axi_interconnect_1_M_AWREADY">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_interconnect_1" PORT="M_AXI_AWREADY"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_interconnect_1" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="s_axi_aclk"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_aresetn"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_wdata"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_bready"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_araddr"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP DIR="I" PHYSICAL="s_axi_rready"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_arready"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_rdata"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_rresp"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_wready"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_bresp"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP DIR="O" PHYSICAL="s_axi_awready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_vdma_1_M_AXIS_MM2S" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="M_AXIS_MM2S" PROTOCOL="XIL_AXI_STREAM_VID_DATA" TYPE="TARGET">
          <PORTMAPS>
            <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tvalid"/>
            <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tkeep"/>
            <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tdata"/>
            <PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tlast"/>
            <PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE BASEDECIMAL="2002911232" BASENAME="C_BASEADDR" BASEVALUE="0x77620000" HIGHDECIMAL="2002976767" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7762ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
          <SLAVES>
            <SLAVE BUSINTERFACE="S_AXI"/>
          </SLAVES>
        </MEMRANGE>
      </MEMORYMAP>
    </MODULE>
  </MODULES>

</EDKSYSTEM>