Saved contents of this file to system_log.14.4 during revup to EDK 14.5.

Xilinx Platform Studio (XPS)
Xilinx EDK 14.5 Build EDK_P.58f
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


********************************************************************************
At Local date and time: Wed Aug 28 10:12:37 2013
 make -f system.make exporttosdk started...
"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp D:/Temp/fpgahdl_xilinx/cf_lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.4 - platgen Xilinx EDK 14.4 Build EDK_P.49d

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp

D:/Temp/fpgahdl_xilinx/cf_lib/ -msg __xps/ise/xmsgprops.lst system.mhs 



Parse D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/system.mhs ...



Read MPD definitions ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 300 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 304 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 308 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 312 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 7 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 319 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock

   'processing_system7_0_PS_CLK' is not specified. Clock DRCs will not be

   performed for IPs connected to that clock port, unless they are connected

   through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   axi_clkgen_0:clk. Clock DRCs will not be performed on this core and cores

   connected to it. 



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

INFO:EDK - INFO: DDR Base and High address in current configuration is

   0x00000000 and 0x1FFFFFFF respectively. 

INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable

   Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a

   master on processing_system7 AXI slave interfaces, please use the top half of

   the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For

   all other master, any subset of the DDR address can be used. See Xilinx

   Answer 47167 for more information. 

Address Map for Processor processing_system7_0

  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1

  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1

  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1

  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1

  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1



Checking platform address map ...



Checking platform configuration ...

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 7

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - 1 master(s) : 1

slave(s) 



Checking port drivers...

WARNING:EDK:4181 - PORT: hdmi_int, CONNECTOR: hdmi_int - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 32 

WARNING:EDK:4181 - PORT: util_vector_logic_0_Op1_pin, CONNECTOR:

   net_util_vector_logic_0_Op1_pin - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 35 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_0_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 



Performing Clock DRCs...



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 353 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_2; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

ZynqConfig: Terminated for tcl mode



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.


INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.




Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...



Managing cache ...



Elaborating instances ...

IPNAME:clock_generator INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 1.00 seconds



Constructing platform-level connectivity ...

Completion time: 0.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:processing_system7_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 60 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_vdma_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199

- Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_interconnect_1 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 222 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_interconnect_2 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 230 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_hdmi_tx_16b_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 238 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_spdif_tx_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

259 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_iic_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_clkgen_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

296 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:clock_generator_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 307 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:util_vector_logic_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 317 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_i2s_adi_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

326 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:util_i2c_mixer_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 361 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_iic_1 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Running NGCBUILD ...

IPNAME:system_axi_vdma_0_wrapper INSTANCE:axi_vdma_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_vdma_0_wrapper.ngc

../system_axi_vdma_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_vdma_0_wrapper/system_

axi_vdma_0_wrapper.ngc" ...

Loading design module

"../system_axi_vdma_0_wrapper_fifo_generator_v9_1_2.ngc"...

Loading design module

"../system_axi_vdma_0_wrapper_fifo_generator_v9_1_1.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_vdma_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_vdma_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_interconnect_1_wrapper INSTANCE:axi_interconnect_1 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_interconnect_1_wrapper.ngc

../system_axi_interconnect_1_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_interconnect_1_wrapper

/system_axi_interconnect_1_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_interconnect_1_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_interconnect_1_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_interconnect_2_wrapper INSTANCE:axi_interconnect_2 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_interconnect_2_wrapper.ngc

../system_axi_interconnect_2_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_interconnect_2_wrapper

/system_axi_interconnect_2_wrapper.ngc" ...

Loading design module

"../system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1.ngc"...

Loading design module

"../system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_interconnect_2_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_interconnect_2_wrapper.blc"...



NGCBUILD done.

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/clock_generator_0_wrapper/

system_clock_generator_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 639.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc

Release 14.4 - Xflow P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc 

 

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

.... Copying flowfile D:/Xilinx/14.4/ISE_DS/ISE/xilinx/data/fpga.flw into

working directory D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation 



Using Flow File: D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/fpga.flw 

Using Option File(s): 

 D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc7z020clg484-1 -nt timestamp -bm system.bmm

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc" -uc system.ucf

system.ngd 

#----------------------------------------------#

Release 14.4 - ngdbuild P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>





Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc7z020clg484-1 -nt timestamp -bm system.bmm


D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc -uc system.ucf


system.ngd





Reading NGO file


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc" ...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_processing_system7_


0_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_util_vector_logic_0


_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_i2s_adi_0_wrapp


er.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_1_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_2_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_spdif_tx_0_wrap


per.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_clkgen_0_wrappe


r.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_clock_generator_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_vdma_0_wrapper.


ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_hdmi_tx_16b_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_iic_0_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_iic_1_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_util_i2c_mixer_0_wr


apper.ngc"...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_processing_system7_


0_wrapper.ncf" to module "processing_system7_0"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_1_


wrapper.ncf" to module "axi_interconnect_1"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_2_


wrapper.ncf" to module "axi_interconnect_2"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_vdma_0_wrapper.


ncf" to module "axi_vdma_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_PORB_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_CLK_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_SRSTB_IBUF'.  All constraints associated with this


   symbol will be ignored.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.s_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_lev

el_out_d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.p_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_lev

el_in_d1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.s_level_out_d1_cdc_to_GN...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_out_

d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.p_level_in_d1_cdc_from_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_in_d

1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.s_level_in_d1_cdc_from_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_

d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out

_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_lev

el_in_d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.p_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_lev

el_out_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out


   _d1_cdc_to_GND_148_o_MUX_596_o11 TNM =...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_MUX_5

96_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_


   d1_cdc_from_GND_148_o_MUX_595_o11 TNM ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o_MUX_

595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   p_out_d1_cdc_to_GND_148_o_MUX_596_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_

MUX_596_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   s_in_d1_cdc_from_GND_148_o_MUX_595_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o

_MUX_595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_132_o_MUX_591_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_132_o

_MUX_591_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.s_out_d1_cdc_to_GND_70_o_MUX_51_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o

_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.p_in_d1_cdc_from_GND_70_o_MUX_50_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_

o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_70_o_MUX_51_o11 T...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_

MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_70_o_MUX_50_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o

_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_34_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_34_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_26_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_26_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_10_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_10_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_2/axi_interconnect_2\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_2_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_2/axi_interconnect_2/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_PORB_IBUF" LOC = B5>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_CLK_IBUF" LOC = F7>' could not be found and so


   the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_SRSTB_IBUF" LOC = C9>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_2_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_2_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   axi_clkgen_0/USER_LOGIC_I/i_clkgen/i_mmcm. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC


   TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s = PERIOD


   "axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s" TS_clk_fpga_2 *


   0.742424242 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   clock_generator_0/MMCM1_INST/MMCM_ADV_inst. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0" TS_clk_fpga_2


   * 0.061440678 HIGH 50>





Done...





Processing BMM file "system.bmm" ...





WARNING::53 - File 'system.bmm' is empty or has no BMM content.








Checking expanded design ...


WARNING:NgdBuild:486 - Attribute "CLOCK_HOLD" is not allowed on symbol


   "clock_generator_0/MMCM1_INST/MMCM_ADV_inst" of type "MMCME2_ADV".  This


   attribute will be ignored.


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_0/axi_iic_0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_1/axi_iic_1/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:452 - logical net 'N165' has no driver


WARNING:NgdBuild:452 - logical net 'N166' has no driver


WARNING:NgdBuild:452 - logical net 'N167' has no driver


WARNING:NgdBuild:452 - logical net 'N168' has no driver


WARNING:NgdBuild:452 - logical net 'N169' has no driver


WARNING:NgdBuild:452 - logical net 'N170' has no driver


WARNING:NgdBuild:452 - logical net 'N171' has no driver


WARNING:NgdBuild:452 - logical net 'N172' has no driver


WARNING:NgdBuild:452 - logical net 'N173' has no driver


WARNING:NgdBuild:452 - logical net 'N174' has no driver


WARNING:NgdBuild:452 - logical net 'N175' has no driver


WARNING:NgdBuild:452 - logical net 'N176' has no driver


WARNING:NgdBuild:452 - logical net 'N177' has no driver


WARNING:NgdBuild:452 - logical net 'N178' has no driver


WARNING:NgdBuild:452 - logical net 'N179' has no driver


WARNING:NgdBuild:452 - logical net 'N180' has no driver


WARNING:NgdBuild:452 - logical net 'N181' has no driver


WARNING:NgdBuild:452 - logical net 'N182' has no driver


WARNING:NgdBuild:452 - logical net 'N183' has no driver


WARNING:NgdBuild:452 - logical net 'N184' has no driver


WARNING:NgdBuild:452 - logical net 'N185' has no driver


WARNING:NgdBuild:452 - logical net 'N186' has no driver


WARNING:NgdBuild:452 - logical net 'N187' has no driver


WARNING:NgdBuild:452 - logical net 'N188' has no driver


WARNING:NgdBuild:452 - logical net 'N189' has no driver


WARNING:NgdBuild:452 - logical net 'N190' has no driver


WARNING:NgdBuild:452 - logical net 'N191' has no driver


WARNING:NgdBuild:452 - logical net 'N192' has no driver


WARNING:NgdBuild:452 - logical net 'N193' has no driver


WARNING:NgdBuild:452 - logical net 'N194' has no driver


WARNING:NgdBuild:452 - logical net 'N195' has no driver


WARNING:NgdBuild:452 - logical net 'N196' has no driver


WARNING:NgdBuild:452 - logical net 'N197' has no driver


WARNING:NgdBuild:452 - logical net 'N198' has no driver


WARNING:NgdBuild:452 - logical net 'N199' has no driver


WARNING:NgdBuild:452 - logical net 'N200' has no driver


WARNING:NgdBuild:452 - logical net 'N201' has no driver


WARNING:NgdBuild:452 - logical net 'N202' has no driver


WARNING:NgdBuild:452 - logical net 'N203' has no driver


WARNING:NgdBuild:452 - logical net 'N204' has no driver


WARNING:NgdBuild:452 - logical net 'N205' has no driver


WARNING:NgdBuild:452 - logical net 'N206' has no driver


WARNING:NgdBuild:452 - logical net 'N207' has no driver


WARNING:NgdBuild:452 - logical net 'N208' has no driver


WARNING:NgdBuild:452 - logical net 'N209' has no driver


WARNING:NgdBuild:452 - logical net 'N210' has no driver


WARNING:NgdBuild:452 - logical net 'N211' has no driver


WARNING:NgdBuild:452 - logical net 'N212' has no driver


WARNING:NgdBuild:452 - logical net 'N213' has no driver


WARNING:NgdBuild:452 - logical net 'N214' has no driver


WARNING:NgdBuild:452 - logical net 'N215' has no driver


WARNING:NgdBuild:452 - logical net 'N216' has no driver


WARNING:NgdBuild:452 - logical net 'N217' has no driver


WARNING:NgdBuild:452 - logical net 'N218' has no driver


WARNING:NgdBuild:452 - logical net 'N219' has no driver


WARNING:NgdBuild:452 - logical net 'N220' has no driver


WARNING:NgdBuild:452 - logical net 'N221' has no driver


WARNING:NgdBuild:452 - logical net 'N222' has no driver


WARNING:NgdBuild:452 - logical net 'N223' has no driver


WARNING:NgdBuild:452 - logical net 'N224' has no driver


WARNING:NgdBuild:452 - logical net 'N225' has no driver


WARNING:NgdBuild:452 - logical net 'N226' has no driver


WARNING:NgdBuild:452 - logical net 'N227' has no driver


WARNING:NgdBuild:452 - logical net 'N228' has no driver


WARNING:NgdBuild:452 - logical net 'N229' has no driver


WARNING:NgdBuild:452 - logical net 'N230' has no driver


WARNING:NgdBuild:452 - logical net 'N231' has no driver


WARNING:NgdBuild:452 - logical net 'N232' has no driver


WARNING:NgdBuild:452 - logical net 'N233' has no driver


WARNING:NgdBuild:452 - logical net 'N234' has no driver


WARNING:NgdBuild:452 - logical net 'N235' has no driver


WARNING:NgdBuild:452 - logical net 'N236' has no driver


WARNING:NgdBuild:452 - logical net 'N237' has no driver


WARNING:NgdBuild:452 - logical net 'N238' has no driver


WARNING:NgdBuild:452 - logical net 'N239' has no driver


WARNING:NgdBuild:452 - logical net 'N240' has no driver


WARNING:NgdBuild:452 - logical net 'N241' has no driver


WARNING:NgdBuild:452 - logical net 'N242' has no driver


WARNING:NgdBuild:452 - logical net 'N243' has no driver


WARNING:NgdBuild:452 - logical net 'N244' has no driver


WARNING:NgdBuild:452 - logical net 'N245' has no driver


WARNING:NgdBuild:452 - logical net 'N246' has no driver


WARNING:NgdBuild:452 - logical net 'N247' has no driver


WARNING:NgdBuild:452 - logical net 'N248' has no driver


WARNING:NgdBuild:452 - logical net 'N249' has no driver


WARNING:NgdBuild:452 - logical net 'N250' has no driver


WARNING:NgdBuild:452 - logical net 'N251' has no driver


WARNING:NgdBuild:452 - logical net 'N252' has no driver


WARNING:NgdBuild:452 - logical net 'N253' has no driver


WARNING:NgdBuild:452 - logical net 'N254' has no driver


WARNING:NgdBuild:452 - logical net 'N255' has no driver


WARNING:NgdBuild:452 - logical net 'N256' has no driver


WARNING:NgdBuild:452 - logical net 'N257' has no driver


WARNING:NgdBuild:452 - logical net 'N258' has no driver


WARNING:NgdBuild:452 - logical net 'N259' has no driver


WARNING:NgdBuild:452 - logical net 'N260' has no driver


WARNING:NgdBuild:452 - logical net 'N261' has no driver


WARNING:NgdBuild:452 - logical net 'N262' has no driver


WARNING:NgdBuild:452 - logical net 'N263' has no driver


WARNING:NgdBuild:452 - logical net 'N264' has no driver


WARNING:NgdBuild:452 - logical net 'N265' has no driver


WARNING:NgdBuild:452 - logical net 'N266' has no driver


WARNING:NgdBuild:452 - logical net 'N267' has no driver


WARNING:NgdBuild:452 - logical net 'N268' has no driver


WARNING:NgdBuild:452 - logical net 'N269' has no driver


WARNING:NgdBuild:452 - logical net 'N270' has no driver


WARNING:NgdBuild:452 - logical net 'N271' has no driver


WARNING:NgdBuild:452 - logical net 'N272' has no driver


WARNING:NgdBuild:452 - logical net 'N273' has no driver


WARNING:NgdBuild:452 - logical net 'N274' has no driver


WARNING:NgdBuild:452 - logical net 'N275' has no driver


WARNING:NgdBuild:452 - logical net 'N276' has no driver


WARNING:NgdBuild:452 - logical net 'N277' has no driver


WARNING:NgdBuild:452 - logical net 'N278' has no driver


WARNING:NgdBuild:452 - logical net 'N279' has no driver


WARNING:NgdBuild:452 - logical net 'N280' has no driver


WARNING:NgdBuild:452 - logical net 'N316' has no driver


WARNING:NgdBuild:452 - logical net 'N317' has no driver


WARNING:NgdBuild:452 - logical net 'N318' has no driver


WARNING:NgdBuild:452 - logical net 'N319' has no driver


WARNING:NgdBuild:452 - logical net 'N320' has no driver


WARNING:NgdBuild:452 - logical net 'N321' has no driver


WARNING:NgdBuild:452 - logical net 'N322' has no driver


WARNING:NgdBuild:452 - logical net 'N323' has no driver


WARNING:NgdBuild:452 - logical net 'N324' has no driver


WARNING:NgdBuild:452 - logical net 'N325' has no driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings: 198





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  33 sec


Total CPU time to NGDBUILD completion:   32 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.4 - Map P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<D:/Xilinx/14.4/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<D:/Xilinx/14.4/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "7z020clg484-1".


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB" is not constrained


   (LOC) to a specific location.


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 38 secs 


Total CPU  time at the beginning of Placer: 33 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:b46c4639) REAL time: 43 secs 





Phase 2.7  Design Feasibility Check


WARNING:Place:838 - An IO Bus with more than one IO standard is found.


   Components associated with this bus are as follows: 


   	 Comp: processing_system7_0_GPIO_pin<0>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<1>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<2>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<3>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<4>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<5>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<6>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<7>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<8>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<9>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<10>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<11>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<12>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<13>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<14>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<15>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<16>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<17>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<18>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<19>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<20>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<21>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<22>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<23>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<24>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<25>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<26>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<27>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<28>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<29>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<30>   IOSTANDARD = LVCMOS25








Phase 2.7  Design Feasibility Check (Checksum:b46c4639) REAL time: 44 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:b46c4639) REAL time: 44 secs 





Phase 4.2  Initial Placement for Architecture Specific Features





Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:bb0559f) REAL time: 51 secs 





Phase 5.30  Global Clock Region Assignment


Phase 5.30  Global Clock Region Assignment (Checksum:bb0559f) REAL time: 51 secs 





Phase 6.3  Local Placement Optimization


Phase 6.3  Local Placement Optimization (Checksum:bb0559f) REAL time: 52 secs 





Phase 7.5  Local Placement Optimization


Phase 7.5  Local Placement Optimization (Checksum:bb0559f) REAL time: 52 secs 





Phase 8.8  Global Placement


........................................


....


............................................................................................


..............................................................................................................................................................................................


............................................................................................................................................................


Phase 8.8  Global Placement (Checksum:164bf083) REAL time: 2 mins 13 secs 





Phase 9.5  Local Placement Optimization


Phase 9.5  Local Placement Optimization (Checksum:164bf083) REAL time: 2 mins 14 secs 





Phase 10.18  Placement Optimization


Phase 10.18  Placement Optimization (Checksum:bd2c5eac) REAL time: 2 mins 27 secs 





Phase 11.5  Local Placement Optimization


Phase 11.5  Local Placement Optimization (Checksum:bd2c5eac) REAL time: 2 mins 27 secs 





Phase 12.34  Placement Validation


Phase 12.34  Placement Validation (Checksum:bd2c5eac) REAL time: 2 mins 27 secs 





Total REAL time to Placer completion: 2 mins 28 secs 


Total CPU  time to Placer completion: 2 mins 20 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:   26


Slice Logic Utilization:


  Number of Slice Registers:                 4,935 out of 106,400    4


    Number used as Flip Flops:               4,925


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:               10


  Number of Slice LUTs:                      5,177 out of  53,200    9


    Number used as logic:                    4,586 out of  53,200    8


      Number using O6 output only:           3,217


      Number using O5 output only:             127


      Number using O5 and O6:                1,242


      Number used as ROM:                        0


    Number used as Memory:                     405 out of  17,400    2


      Number used as Dual Port RAM:             74


        Number using O6 output only:             6


        Number using O5 output only:             5


        Number using O5 and O6:                 63


      Number used as Single Port RAM:            0


      Number used as Shift Register:           331


        Number using O6 output only:           323


        Number using O5 output only:             0


        Number using O5 and O6:                  8


    Number used exclusively as route-thrus:    186


      Number with same-slice register load:     49


      Number with same-slice carry load:       137


      Number with other load:                    0





Slice Logic Distribution:


  Number of occupied Slices:                 2,544 out of  13,300   19


  Number of LUT Flip Flop pairs used:        6,990


    Number with an unused Flip Flop:         2,456 out of   6,990   35


    Number with an unused LUT:               1,813 out of   6,990   25


    Number of fully used LUT-FF pairs:       2,721 out of   6,990   38


    Number of unique control sets:             304


    Number of slice register sites lost


      to control set restrictions:           1,127 out of 106,400    1





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.


  OVERMAPPING of BRAM resources should be ignored if the design is


  over-mapped for a non-BRAM resource or if placement fails.





IO Utilization:


  Number of bonded IOBs:                        78 out of     200   39


    Number of LOCed IOBs:                       78 out of      78  100


  Number of bonded IOPAD:                      130 out of     130  100


    IOB Flip Flops:                             25





Specific Feature Utilization:


  Number of RAMB36E1/FIFO36E1s:                  3 out of     140    2


    Number using RAMB36E1 only:                  3


    Number using FIFO36E1 only:                  0


  Number of RAMB18E1/FIFO18E1s:                  0 out of     280    0


  Number of BUFG/BUFGCTRLs:                      6 out of      32   18


    Number used as BUFGs:                        6


    Number used as BUFGCTRLs:                    0


  Number of IDELAYE2/IDELAYE2_FINEDELAYs:        0 out of     200    0


  Number of ILOGICE2/ILOGICE3/ISERDESE2s:        1 out of     200    1


    Number used as ILOGICE2s:                    1


  Number used as  ILOGICE3s:                     0


    Number used as ISERDESE2s:                   0


  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0


  Number of OLOGICE2/OLOGICE3/OSERDESE2s:       55 out of     200   27


    Number used as OLOGICE2s:                   55


    Number used as OLOGICE3s:                    0


    Number used as OSERDESE2s:                   0


  Number of PHASER_IN/PHASER_IN_PHYs:            0 out of      16    0


  Number of PHASER_OUT/PHASER_OUT_PHYs:          0 out of      16    0


  Number of BSCANs:                              0 out of       4    0


  Number of BUFHCEs:                             0 out of      72    0


  Number of BUFRs:                               0 out of      16    0


  Number of CAPTUREs:                            0 out of       1    0


  Number of DNA_PORTs:                           0 out of       1    0


  Number of DSP48E1s:                            0 out of     220    0


  Number of EFUSE_USRs:                          0 out of       1    0


  Number of FRAME_ECCs:                          0 out of       1    0


  Number of ICAPs:                               0 out of       2    0


  Number of IDELAYCTRLs:                         0 out of       4    0


  Number of IN_FIFOs:                            0 out of      16    0


  Number of MMCME2_ADVs:                         2 out of       4   50


  Number of OUT_FIFOs:                           0 out of      16    0


  Number of PHASER_REFs:                         0 out of       4    0


  Number of PHY_CONTROLs:                        0 out of       4    0


  Number of PLLE2_ADVs:                          0 out of       4    0


  Number of PS7s:                                1 out of       1  100


  Number of STARTUPs:                            0 out of       1    0


  Number of XADCs:                               0 out of       1    0





Average Fanout of Non-Clock Nets:                3.36





Peak Memory Usage:  971 MB


Total REAL time to MAP completion:  2 mins 35 secs 


Total CPU time to MAP completion:   2 mins 27 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - par P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/data/parBmgr.acd> with local file

<D:/Xilinx/14.4/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)





Device speed data version:  "ADVANCED 1.04 2012-12-04".







Device Utilization Summary:



   Number of BUFGs                           6 out of 32     18

   Number of ILOGICE2s                       1 out of 200     1

   Number of External IOB33s                78 out of 200    39

      Number of LOCed IOB33s                78 out of 78    100



   Number of External IOPADs               130 out of 130   100

      Number of LOCed IOPADs               127 out of 130    97



   Number of MMCME2_ADVs                     2 out of 4      50

   Number of OLOGICE2s                      55 out of 200    27

   Number of PS7s                            1 out of 1     100

   Number of RAMB36E1s                       3 out of 140     2

   Number of Slices                       2544 out of 13300  19

   Number of Slice Registers              4935 out of 106400  4

      Number used as Flip Flops           4935

      Number used as Latches                 0

      Number used as LatchThrus              0



   Number of Slice LUTS                   5177 out of 53200   9

   Number of Slice LUT-Flip Flop pairs    6829 out of 53200  12





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 19 secs 

Finished initial Timing Analysis.  REAL time: 19 secs 



WARNING:Par:288 - The signal hdmi_int_IBUF has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3> has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mra

   m_RAM_RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route this

   signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM

   _RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

Starting Router





Phase  1  : 33344 unrouted;      REAL time: 20 secs 



Phase  2  : 26228 unrouted;      REAL time: 22 secs 



Phase  3  : 8558 unrouted;      REAL time: 32 secs 



Phase  4  : 8580 unrouted; (Setup:0, Hold:40229, Component Switching Limit:0)     REAL time: 36 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 46 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 46 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 46 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 46 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 48 secs 

Total REAL time to Router completion: 48 secs 

Total CPU time to Router completion: 48 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK0 |BUFGCTRL_X0Y31| No   |  774 |  0.427     |  2.054      |

+---------------------+--------------+------+------+------------+-------------+

|axi_hdmi_tx_16b_0_hd |              |      |      |            |             |

|          mi_ref_clk | BUFGCTRL_X0Y1| No   |  368 |  0.280     |  1.902      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK1 |BUFGCTRL_X0Y29| No   |  653 |  0.418     |  2.057      |

+---------------------+--------------+------+------+------------+-------------+

|axi_i2s_adi_0_MCLK_p |              |      |      |            |             |

|             in_OBUF |BUFGCTRL_X0Y28| No   |   16 |  0.247     |  1.890      |

+---------------------+--------------+------+------+------------+-------------+

|axi_clkgen_0/axi_clk |              |      |      |            |             |

|gen_0/USER_LOGIC_I/i |              |      |      |            |             |

|_clkgen/buf_fb_clk_s |              |      |      |            |             |

|                     | BUFGCTRL_X0Y0| No   |    1 |  0.000     |  1.759      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK2 |BUFGCTRL_X0Y30| No   |    2 |  0.218     |  1.980      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0/cl |              |      |      |            |             |

|ock_generator_0/SIG_ |              |      |      |            |             |

|      MMCM1_CLKFBOUT |         Local|      |    1 |  0.000     |  0.014      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.000ns|    10.000ns|       0|           0

  0" 100 MHz HIGH 50| HOLD        |     0.000ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_1 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.147ns|     6.853ns|       0|           0

  1" 142.857 MHz HIGH 50| HOLD        |     0.014ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I | SETUP       |     0.587ns|     6.147ns|       0|           0

  _i_clkgen_mmcm_clk_s = PERIOD TIMEGRP     | HOLD        |     0.106ns|            |       0|           0

       "axi_clkgen_0_axi_clkgen_0_USER_LOGI |             |            |            |        |            

  C_I_i_clkgen_mmcm_clk_s"         TS_clk_f |             |            |            |        |            

  pga_2 * 0.742424242 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_2 = PERIOD TIMEGRP "clk_fpga_ | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0

  2" 200 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |    77.817ns|     3.562ns|       0|           0

  G_MMCM1_CLKOUT0 = PERIOD TIMEGRP          | HOLD        |     0.034ns|            |       0|           0

  "clock_generator_0_clock_generator_0_SIG_ |             |            |            |        |            

  MMCM1_CLKOUT0" TS_clk_fpga_2         * 0. |             |            |            |        |            

  061440678 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_tig_v_path" TIG   | SETUP       |         N/A|     7.151ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_from_2_cdc_to_pat | SETUP       |         N/A|     3.196ns|     N/A|           0

  h" TIG                                    |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_2_reset_resync_ | SETUP       |         N/A|     1.177ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_1_reset_resync_ | SETUP       |         N/A|     1.081ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_clk_fpga_2

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_clk_fpga_2                  |      5.000ns|      2.800ns|      4.564ns|            0|            0|            0|        43851|

| TS_axi_clkgen_0_axi_clkgen_0_U|      6.735ns|      6.147ns|          N/A|            0|            0|        43794|            0|

| SER_LOGIC_I_i_clkgen_mmcm_clk_|             |             |             |             |             |             |             |

| s                             |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     81.379ns|      3.562ns|          N/A|            0|            0|           57|            0|

| erator_0_SIG_MMCM1_CLKOUT0    |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 19 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 54 secs 

Total CPU time to PAR completion: 50 secs 



Peak Memory Usage:  822 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 21

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>


Loading device for application Rf_Device from file '7z020.nph' in environment


D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.4 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc7z020,-1 (ADVANCED 1.04 2012-12-04)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 414323 paths, 0 nets, and 27779 connections





Design statistics:


   Minimum period:  10.000ns (Maximum frequency: 100.000MHz)








Analysis completed Wed Aug 28 10:28:16 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 19 secs 






xflow done!

touch __xps/system_routed

xilperl D:/Xilinx/14.4/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.4 - Bitgen P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1

Opened constraints file system.pcf.



Wed Aug 28 10:28:30 2013



Running DRC.

WARNING:PhysDesignRules:367 - The signal <hdmi_int_IBUF> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3>> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfif

   o.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/

   grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

INFO:PhysDesignRules:2288 - The read port and write port clocks of BRAM

   instance,

   axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_S

   OF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.V6.I_LINEBUFFER_FIFO/fg91_inst/U0/xst_fifo_g

   enerator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/g

   nativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WI

   DE_PRIM36.ram, are using the same clock signal (synchronous clocking) with

   WRITE_FIRST mode specified. This configuration may encounter address

   collisions if the same address appears on both ports. It is suggested for

   this configuration to use READ_FIRST mode to avoid any conditions for address

   collision. See the FPGA Memory Resources User Guide for additional

   information.

DRC detected 0 errors and 19 warnings.  Please see the previously displayed

individual error or warning messages for more details.

Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!

********************************************************************************
At Local date and time: Wed Aug 28 10:29:04 2013
 xsdk.exe -hwspec D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\SDK\SDK_Export\hw\system.xml started...
Xilinx Software Development Kit

Xilinx EDK 14.4 Build EDK_P.49d

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Done!
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Overriding Xilinx file <TextEditor.cfg> with local file <D:/Xilinx/14.4/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Overriding Xilinx file <TextEditor.cfg> with local file <D:/Xilinx/14.4/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Overriding Xilinx file <TextEditor.cfg> with local file <D:/Xilinx/14.4/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


********************************************************************************
At Local date and time: Mon Sep 09 11:31:12 2013
 make -f system.make clean started...
rm -f implementation/system.ngc

rm -f implementation/system_processing_system7_0_wrapper.ngc implementation/system_axi_vdma_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_axi_interconnect_2_wrapper.ngc implementation/system_axi_hdmi_tx_16b_0_wrapper.ngc implementation/system_axi_spdif_tx_0_wrapper.ngc implementation/system_axi_iic_0_wrapper.ngc implementation/system_axi_clkgen_0_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_util_vector_logic_0_wrapper.ngc implementation/system_axi_i2s_adi_0_wrapper.ngc implementation/system_util_i2c_mixer_0_wrapper.ngc implementation/system_axi_iic_1_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

rm -f implementation/system.bit

rm -f implementation/system.ncd

rm -f implementation/system_bd.bmm 

rm -f implementation/system_map.ncd 

rm -f implementation/download.bit 

rm -f __xps/system_bits

rm -rf implementation synthesis xst hdl

rm -rf xst.srp system.srp

rm -f __xps/ise/_xmsgs/bitinit.xmsgs

rm -rf __xps/ps7_instance.mhs

rm -rf simulation/behavioral

rm -f simgen.log

rm -f __xps/ise/_xmsgs/simgen.xmsgs

rm -f _impact.cmd

Done!

********************************************************************************
At Local date and time: Mon Sep 09 11:31:26 2013
 make -f system.make exporttosdk started...
"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp D:/Temp/fpgahdl_xilinx/cf_lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.4 - platgen Xilinx EDK 14.4 Build EDK_P.49d

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp

D:/Temp/fpgahdl_xilinx/cf_lib/ -msg __xps/ise/xmsgprops.lst system.mhs 



Parse D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/system.mhs ...



Read MPD definitions ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 300 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 304 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 308 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 312 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 7 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 319 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock

   'processing_system7_0_PS_CLK' is not specified. Clock DRCs will not be

   performed for IPs connected to that clock port, unless they are connected

   through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   axi_clkgen_0:clk. Clock DRCs will not be performed on this core and cores

   connected to it. 



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

INFO:EDK - INFO: DDR Base and High address in current configuration is

   0x00000000 and 0x1FFFFFFF respectively. 

INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable

   Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a

   master on processing_system7 AXI slave interfaces, please use the top half of

   the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For

   all other master, any subset of the DDR address can be used. See Xilinx

   Answer 47167 for more information. 

Address Map for Processor processing_system7_0

  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1

  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1

  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1

  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1

  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1



Checking platform address map ...



Checking platform configuration ...

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 7

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - 1 master(s) : 1

slave(s) 



Checking port drivers...

WARNING:EDK:4181 - PORT: hdmi_int, CONNECTOR: hdmi_int - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 32 

WARNING:EDK:4181 - PORT: util_vector_logic_0_Op1_pin, CONNECTOR:

   net_util_vector_logic_0_Op1_pin - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 35 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_0_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 



Performing Clock DRCs...



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 353 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_2; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

ZynqConfig: Terminated for tcl mode



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.


INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.




Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...



Managing cache ...



Elaborating instances ...

IPNAME:clock_generator INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 1.00 seconds



Constructing platform-level connectivity ...

Completion time: 0.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:processing_system7_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 60 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_vdma_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199

- Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_interconnect_1 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 222 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_interconnect_2 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 230 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_hdmi_tx_16b_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 238 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_spdif_tx_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

259 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_iic_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_clkgen_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

296 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:clock_generator_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 307 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:util_vector_logic_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 317 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_i2s_adi_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

326 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:util_i2c_mixer_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 361 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_iic_1 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Running NGCBUILD ...

IPNAME:system_axi_vdma_0_wrapper INSTANCE:axi_vdma_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_vdma_0_wrapper.ngc

../system_axi_vdma_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_vdma_0_wrapper/system_

axi_vdma_0_wrapper.ngc" ...

Loading design module

"../system_axi_vdma_0_wrapper_fifo_generator_v9_1_2.ngc"...

Loading design module

"../system_axi_vdma_0_wrapper_fifo_generator_v9_1_1.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_vdma_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_vdma_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_interconnect_1_wrapper INSTANCE:axi_interconnect_1 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_interconnect_1_wrapper.ngc

../system_axi_interconnect_1_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_interconnect_1_wrapper

/system_axi_interconnect_1_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_interconnect_1_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_interconnect_1_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_interconnect_2_wrapper INSTANCE:axi_interconnect_2 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_interconnect_2_wrapper.ngc

../system_axi_interconnect_2_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_interconnect_2_wrapper

/system_axi_interconnect_2_wrapper.ngc" ...

Loading design module

"../system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1.ngc"...

Loading design module

"../system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_interconnect_2_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_interconnect_2_wrapper.blc"...



NGCBUILD done.

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/clock_generator_0_wrapper/

system_clock_generator_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 628.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc

Release 14.4 - Xflow P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc 

 

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

.... Copying flowfile D:/Xilinx/14.4/ISE_DS/ISE/xilinx/data/fpga.flw into

working directory D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation 



Using Flow File: D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/fpga.flw 

Using Option File(s): 

 D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc7z020clg484-1 -nt timestamp -bm system.bmm

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc" -uc system.ucf

system.ngd 

#----------------------------------------------#

Release 14.4 - ngdbuild P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>





Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc7z020clg484-1 -nt timestamp -bm system.bmm


D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc -uc system.ucf


system.ngd





Reading NGO file


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc" ...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_processing_system7_


0_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_util_vector_logic_0


_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_i2s_adi_0_wrapp


er.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_1_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_2_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_spdif_tx_0_wrap


per.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_clkgen_0_wrappe


r.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_clock_generator_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_vdma_0_wrapper.


ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_hdmi_tx_16b_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_iic_0_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_iic_1_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_util_i2c_mixer_0_wr


apper.ngc"...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_processing_system7_


0_wrapper.ncf" to module "processing_system7_0"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_1_


wrapper.ncf" to module "axi_interconnect_1"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_2_


wrapper.ncf" to module "axi_interconnect_2"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_vdma_0_wrapper.


ncf" to module "axi_vdma_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_PORB_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_CLK_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_SRSTB_IBUF'.  All constraints associated with this


   symbol will be ignored.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.s_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_lev

el_out_d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.p_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_lev

el_in_d1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.s_level_out_d1_cdc_to_GN...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_out_

d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.p_level_in_d1_cdc_from_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_in_d

1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.s_level_in_d1_cdc_from_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_

d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out

_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_lev

el_in_d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.p_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_lev

el_out_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out


   _d1_cdc_to_GND_148_o_MUX_596_o11 TNM =...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_MUX_5

96_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_


   d1_cdc_from_GND_148_o_MUX_595_o11 TNM ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o_MUX_

595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   p_out_d1_cdc_to_GND_148_o_MUX_596_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_

MUX_596_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   s_in_d1_cdc_from_GND_148_o_MUX_595_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o

_MUX_595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_132_o_MUX_591_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_132_o

_MUX_591_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.s_out_d1_cdc_to_GND_70_o_MUX_51_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o

_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.p_in_d1_cdc_from_GND_70_o_MUX_50_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_

o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_70_o_MUX_51_o11 T...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_

MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_70_o_MUX_50_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o

_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_34_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_34_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_26_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_26_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_10_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_10_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_2/axi_interconnect_2\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_2_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_2/axi_interconnect_2/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_PORB_IBUF" LOC = B5>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_CLK_IBUF" LOC = F7>' could not be found and so


   the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_SRSTB_IBUF" LOC = C9>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_2_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_2_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   axi_clkgen_0/USER_LOGIC_I/i_clkgen/i_mmcm. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC


   TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s = PERIOD


   "axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s" TS_clk_fpga_2 *


   0.742424242 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   clock_generator_0/MMCM1_INST/MMCM_ADV_inst. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0" TS_clk_fpga_2


   * 0.061440678 HIGH 50>





Done...





Processing BMM file "system.bmm" ...





WARNING::53 - File 'system.bmm' is empty or has no BMM content.








Checking expanded design ...


WARNING:NgdBuild:486 - Attribute "CLOCK_HOLD" is not allowed on symbol


   "clock_generator_0/MMCM1_INST/MMCM_ADV_inst" of type "MMCME2_ADV".  This


   attribute will be ignored.


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_0/axi_iic_0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_1/axi_iic_1/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:452 - logical net 'N165' has no driver


WARNING:NgdBuild:452 - logical net 'N166' has no driver


WARNING:NgdBuild:452 - logical net 'N167' has no driver


WARNING:NgdBuild:452 - logical net 'N168' has no driver


WARNING:NgdBuild:452 - logical net 'N169' has no driver


WARNING:NgdBuild:452 - logical net 'N170' has no driver


WARNING:NgdBuild:452 - logical net 'N171' has no driver


WARNING:NgdBuild:452 - logical net 'N172' has no driver


WARNING:NgdBuild:452 - logical net 'N173' has no driver


WARNING:NgdBuild:452 - logical net 'N174' has no driver


WARNING:NgdBuild:452 - logical net 'N175' has no driver


WARNING:NgdBuild:452 - logical net 'N176' has no driver


WARNING:NgdBuild:452 - logical net 'N177' has no driver


WARNING:NgdBuild:452 - logical net 'N178' has no driver


WARNING:NgdBuild:452 - logical net 'N179' has no driver


WARNING:NgdBuild:452 - logical net 'N180' has no driver


WARNING:NgdBuild:452 - logical net 'N181' has no driver


WARNING:NgdBuild:452 - logical net 'N182' has no driver


WARNING:NgdBuild:452 - logical net 'N183' has no driver


WARNING:NgdBuild:452 - logical net 'N184' has no driver


WARNING:NgdBuild:452 - logical net 'N185' has no driver


WARNING:NgdBuild:452 - logical net 'N186' has no driver


WARNING:NgdBuild:452 - logical net 'N187' has no driver


WARNING:NgdBuild:452 - logical net 'N188' has no driver


WARNING:NgdBuild:452 - logical net 'N189' has no driver


WARNING:NgdBuild:452 - logical net 'N190' has no driver


WARNING:NgdBuild:452 - logical net 'N191' has no driver


WARNING:NgdBuild:452 - logical net 'N192' has no driver


WARNING:NgdBuild:452 - logical net 'N193' has no driver


WARNING:NgdBuild:452 - logical net 'N194' has no driver


WARNING:NgdBuild:452 - logical net 'N195' has no driver


WARNING:NgdBuild:452 - logical net 'N196' has no driver


WARNING:NgdBuild:452 - logical net 'N197' has no driver


WARNING:NgdBuild:452 - logical net 'N198' has no driver


WARNING:NgdBuild:452 - logical net 'N199' has no driver


WARNING:NgdBuild:452 - logical net 'N200' has no driver


WARNING:NgdBuild:452 - logical net 'N201' has no driver


WARNING:NgdBuild:452 - logical net 'N202' has no driver


WARNING:NgdBuild:452 - logical net 'N203' has no driver


WARNING:NgdBuild:452 - logical net 'N204' has no driver


WARNING:NgdBuild:452 - logical net 'N205' has no driver


WARNING:NgdBuild:452 - logical net 'N206' has no driver


WARNING:NgdBuild:452 - logical net 'N207' has no driver


WARNING:NgdBuild:452 - logical net 'N208' has no driver


WARNING:NgdBuild:452 - logical net 'N209' has no driver


WARNING:NgdBuild:452 - logical net 'N210' has no driver


WARNING:NgdBuild:452 - logical net 'N211' has no driver


WARNING:NgdBuild:452 - logical net 'N212' has no driver


WARNING:NgdBuild:452 - logical net 'N213' has no driver


WARNING:NgdBuild:452 - logical net 'N214' has no driver


WARNING:NgdBuild:452 - logical net 'N215' has no driver


WARNING:NgdBuild:452 - logical net 'N216' has no driver


WARNING:NgdBuild:452 - logical net 'N217' has no driver


WARNING:NgdBuild:452 - logical net 'N218' has no driver


WARNING:NgdBuild:452 - logical net 'N219' has no driver


WARNING:NgdBuild:452 - logical net 'N220' has no driver


WARNING:NgdBuild:452 - logical net 'N221' has no driver


WARNING:NgdBuild:452 - logical net 'N222' has no driver


WARNING:NgdBuild:452 - logical net 'N223' has no driver


WARNING:NgdBuild:452 - logical net 'N224' has no driver


WARNING:NgdBuild:452 - logical net 'N225' has no driver


WARNING:NgdBuild:452 - logical net 'N226' has no driver


WARNING:NgdBuild:452 - logical net 'N227' has no driver


WARNING:NgdBuild:452 - logical net 'N228' has no driver


WARNING:NgdBuild:452 - logical net 'N229' has no driver


WARNING:NgdBuild:452 - logical net 'N230' has no driver


WARNING:NgdBuild:452 - logical net 'N231' has no driver


WARNING:NgdBuild:452 - logical net 'N232' has no driver


WARNING:NgdBuild:452 - logical net 'N233' has no driver


WARNING:NgdBuild:452 - logical net 'N234' has no driver


WARNING:NgdBuild:452 - logical net 'N235' has no driver


WARNING:NgdBuild:452 - logical net 'N236' has no driver


WARNING:NgdBuild:452 - logical net 'N237' has no driver


WARNING:NgdBuild:452 - logical net 'N238' has no driver


WARNING:NgdBuild:452 - logical net 'N239' has no driver


WARNING:NgdBuild:452 - logical net 'N240' has no driver


WARNING:NgdBuild:452 - logical net 'N241' has no driver


WARNING:NgdBuild:452 - logical net 'N242' has no driver


WARNING:NgdBuild:452 - logical net 'N243' has no driver


WARNING:NgdBuild:452 - logical net 'N244' has no driver


WARNING:NgdBuild:452 - logical net 'N245' has no driver


WARNING:NgdBuild:452 - logical net 'N246' has no driver


WARNING:NgdBuild:452 - logical net 'N247' has no driver


WARNING:NgdBuild:452 - logical net 'N248' has no driver


WARNING:NgdBuild:452 - logical net 'N249' has no driver


WARNING:NgdBuild:452 - logical net 'N250' has no driver


WARNING:NgdBuild:452 - logical net 'N251' has no driver


WARNING:NgdBuild:452 - logical net 'N252' has no driver


WARNING:NgdBuild:452 - logical net 'N253' has no driver


WARNING:NgdBuild:452 - logical net 'N254' has no driver


WARNING:NgdBuild:452 - logical net 'N255' has no driver


WARNING:NgdBuild:452 - logical net 'N256' has no driver


WARNING:NgdBuild:452 - logical net 'N257' has no driver


WARNING:NgdBuild:452 - logical net 'N258' has no driver


WARNING:NgdBuild:452 - logical net 'N259' has no driver


WARNING:NgdBuild:452 - logical net 'N260' has no driver


WARNING:NgdBuild:452 - logical net 'N261' has no driver


WARNING:NgdBuild:452 - logical net 'N262' has no driver


WARNING:NgdBuild:452 - logical net 'N263' has no driver


WARNING:NgdBuild:452 - logical net 'N264' has no driver


WARNING:NgdBuild:452 - logical net 'N265' has no driver


WARNING:NgdBuild:452 - logical net 'N266' has no driver


WARNING:NgdBuild:452 - logical net 'N267' has no driver


WARNING:NgdBuild:452 - logical net 'N268' has no driver


WARNING:NgdBuild:452 - logical net 'N269' has no driver


WARNING:NgdBuild:452 - logical net 'N270' has no driver


WARNING:NgdBuild:452 - logical net 'N271' has no driver


WARNING:NgdBuild:452 - logical net 'N272' has no driver


WARNING:NgdBuild:452 - logical net 'N273' has no driver


WARNING:NgdBuild:452 - logical net 'N274' has no driver


WARNING:NgdBuild:452 - logical net 'N275' has no driver


WARNING:NgdBuild:452 - logical net 'N276' has no driver


WARNING:NgdBuild:452 - logical net 'N277' has no driver


WARNING:NgdBuild:452 - logical net 'N278' has no driver


WARNING:NgdBuild:452 - logical net 'N279' has no driver


WARNING:NgdBuild:452 - logical net 'N280' has no driver


WARNING:NgdBuild:452 - logical net 'N316' has no driver


WARNING:NgdBuild:452 - logical net 'N317' has no driver


WARNING:NgdBuild:452 - logical net 'N318' has no driver


WARNING:NgdBuild:452 - logical net 'N319' has no driver


WARNING:NgdBuild:452 - logical net 'N320' has no driver


WARNING:NgdBuild:452 - logical net 'N321' has no driver


WARNING:NgdBuild:452 - logical net 'N322' has no driver


WARNING:NgdBuild:452 - logical net 'N323' has no driver


WARNING:NgdBuild:452 - logical net 'N324' has no driver


WARNING:NgdBuild:452 - logical net 'N325' has no driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings: 198





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  31 sec


Total CPU time to NGDBUILD completion:   31 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.4 - Map P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<D:/Xilinx/14.4/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<D:/Xilinx/14.4/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "7z020clg484-1".


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB" is not constrained


   (LOC) to a specific location.


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 36 secs 


Total CPU  time at the beginning of Placer: 33 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:b46c4639) REAL time: 40 secs 





Phase 2.7  Design Feasibility Check


WARNING:Place:838 - An IO Bus with more than one IO standard is found.


   Components associated with this bus are as follows: 


   	 Comp: processing_system7_0_GPIO_pin<0>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<1>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<2>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<3>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<4>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<5>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<6>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<7>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<8>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<9>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<10>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<11>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<12>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<13>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<14>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<15>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<16>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<17>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<18>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<19>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<20>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<21>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<22>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<23>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<24>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<25>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<26>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<27>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<28>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<29>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<30>   IOSTANDARD = LVCMOS25








Phase 2.7  Design Feasibility Check (Checksum:b46c4639) REAL time: 41 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:b46c4639) REAL time: 41 secs 





Phase 4.2  Initial Placement for Architecture Specific Features





Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:bb0559f) REAL time: 49 secs 





Phase 5.30  Global Clock Region Assignment


Phase 5.30  Global Clock Region Assignment (Checksum:bb0559f) REAL time: 49 secs 





Phase 6.3  Local Placement Optimization


Phase 6.3  Local Placement Optimization (Checksum:bb0559f) REAL time: 49 secs 





Phase 7.5  Local Placement Optimization


Phase 7.5  Local Placement Optimization (Checksum:bb0559f) REAL time: 49 secs 





Phase 8.8  Global Placement


........................................


....


............................................................................................


..............................................................................................................................................................................................


............................................................................................................................................................


Phase 8.8  Global Placement (Checksum:164bf083) REAL time: 2 mins 11 secs 





Phase 9.5  Local Placement Optimization


Phase 9.5  Local Placement Optimization (Checksum:164bf083) REAL time: 2 mins 11 secs 





Phase 10.18  Placement Optimization


Phase 10.18  Placement Optimization (Checksum:bd2c5eac) REAL time: 2 mins 25 secs 





Phase 11.5  Local Placement Optimization


Phase 11.5  Local Placement Optimization (Checksum:bd2c5eac) REAL time: 2 mins 25 secs 





Phase 12.34  Placement Validation


Phase 12.34  Placement Validation (Checksum:bd2c5eac) REAL time: 2 mins 25 secs 





Total REAL time to Placer completion: 2 mins 26 secs 


Total CPU  time to Placer completion: 2 mins 22 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:   26


Slice Logic Utilization:


  Number of Slice Registers:                 4,935 out of 106,400    4


    Number used as Flip Flops:               4,925


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:               10


  Number of Slice LUTs:                      5,177 out of  53,200    9


    Number used as logic:                    4,586 out of  53,200    8


      Number using O6 output only:           3,217


      Number using O5 output only:             127


      Number using O5 and O6:                1,242


      Number used as ROM:                        0


    Number used as Memory:                     405 out of  17,400    2


      Number used as Dual Port RAM:             74


        Number using O6 output only:             6


        Number using O5 output only:             5


        Number using O5 and O6:                 63


      Number used as Single Port RAM:            0


      Number used as Shift Register:           331


        Number using O6 output only:           323


        Number using O5 output only:             0


        Number using O5 and O6:                  8


    Number used exclusively as route-thrus:    186


      Number with same-slice register load:     49


      Number with same-slice carry load:       137


      Number with other load:                    0





Slice Logic Distribution:


  Number of occupied Slices:                 2,544 out of  13,300   19


  Number of LUT Flip Flop pairs used:        6,990


    Number with an unused Flip Flop:         2,456 out of   6,990   35


    Number with an unused LUT:               1,813 out of   6,990   25


    Number of fully used LUT-FF pairs:       2,721 out of   6,990   38


    Number of unique control sets:             304


    Number of slice register sites lost


      to control set restrictions:           1,127 out of 106,400    1





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.


  OVERMAPPING of BRAM resources should be ignored if the design is


  over-mapped for a non-BRAM resource or if placement fails.





IO Utilization:


  Number of bonded IOBs:                        78 out of     200   39


    Number of LOCed IOBs:                       78 out of      78  100


  Number of bonded IOPAD:                      130 out of     130  100


    IOB Flip Flops:                             25





Specific Feature Utilization:


  Number of RAMB36E1/FIFO36E1s:                  3 out of     140    2


    Number using RAMB36E1 only:                  3


    Number using FIFO36E1 only:                  0


  Number of RAMB18E1/FIFO18E1s:                  0 out of     280    0


  Number of BUFG/BUFGCTRLs:                      6 out of      32   18


    Number used as BUFGs:                        6


    Number used as BUFGCTRLs:                    0


  Number of IDELAYE2/IDELAYE2_FINEDELAYs:        0 out of     200    0


  Number of ILOGICE2/ILOGICE3/ISERDESE2s:        1 out of     200    1


    Number used as ILOGICE2s:                    1


  Number used as  ILOGICE3s:                     0


    Number used as ISERDESE2s:                   0


  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0


  Number of OLOGICE2/OLOGICE3/OSERDESE2s:       55 out of     200   27


    Number used as OLOGICE2s:                   55


    Number used as OLOGICE3s:                    0


    Number used as OSERDESE2s:                   0


  Number of PHASER_IN/PHASER_IN_PHYs:            0 out of      16    0


  Number of PHASER_OUT/PHASER_OUT_PHYs:          0 out of      16    0


  Number of BSCANs:                              0 out of       4    0


  Number of BUFHCEs:                             0 out of      72    0


  Number of BUFRs:                               0 out of      16    0


  Number of CAPTUREs:                            0 out of       1    0


  Number of DNA_PORTs:                           0 out of       1    0


  Number of DSP48E1s:                            0 out of     220    0


  Number of EFUSE_USRs:                          0 out of       1    0


  Number of FRAME_ECCs:                          0 out of       1    0


  Number of ICAPs:                               0 out of       2    0


  Number of IDELAYCTRLs:                         0 out of       4    0


  Number of IN_FIFOs:                            0 out of      16    0


  Number of MMCME2_ADVs:                         2 out of       4   50


  Number of OUT_FIFOs:                           0 out of      16    0


  Number of PHASER_REFs:                         0 out of       4    0


  Number of PHY_CONTROLs:                        0 out of       4    0


  Number of PLLE2_ADVs:                          0 out of       4    0


  Number of PS7s:                                1 out of       1  100


  Number of STARTUPs:                            0 out of       1    0


  Number of XADCs:                               0 out of       1    0





Average Fanout of Non-Clock Nets:                3.36





Peak Memory Usage:  971 MB


Total REAL time to MAP completion:  2 mins 33 secs 


Total CPU time to MAP completion:   2 mins 29 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - par P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/data/parBmgr.acd> with local file

<D:/Xilinx/14.4/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)





Device speed data version:  "ADVANCED 1.04 2012-12-04".







Device Utilization Summary:



   Number of BUFGs                           6 out of 32     18

   Number of ILOGICE2s                       1 out of 200     1

   Number of External IOB33s                78 out of 200    39

      Number of LOCed IOB33s                78 out of 78    100



   Number of External IOPADs               130 out of 130   100

      Number of LOCed IOPADs               127 out of 130    97



   Number of MMCME2_ADVs                     2 out of 4      50

   Number of OLOGICE2s                      55 out of 200    27

   Number of PS7s                            1 out of 1     100

   Number of RAMB36E1s                       3 out of 140     2

   Number of Slices                       2544 out of 13300  19

   Number of Slice Registers              4935 out of 106400  4

      Number used as Flip Flops           4935

      Number used as Latches                 0

      Number used as LatchThrus              0



   Number of Slice LUTS                   5177 out of 53200   9

   Number of Slice LUT-Flip Flop pairs    6829 out of 53200  12





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 17 secs 

Finished initial Timing Analysis.  REAL time: 17 secs 



WARNING:Par:288 - The signal hdmi_int_IBUF has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3> has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mra

   m_RAM_RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route this

   signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM

   _RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

Starting Router





Phase  1  : 33344 unrouted;      REAL time: 19 secs 



Phase  2  : 26228 unrouted;      REAL time: 20 secs 



Phase  3  : 8558 unrouted;      REAL time: 30 secs 



Phase  4  : 8580 unrouted; (Setup:0, Hold:40229, Component Switching Limit:0)     REAL time: 35 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 44 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 44 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 44 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 44 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 46 secs 

Total REAL time to Router completion: 47 secs 

Total CPU time to Router completion: 48 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK0 |BUFGCTRL_X0Y31| No   |  774 |  0.427     |  2.054      |

+---------------------+--------------+------+------+------------+-------------+

|axi_hdmi_tx_16b_0_hd |              |      |      |            |             |

|          mi_ref_clk | BUFGCTRL_X0Y1| No   |  368 |  0.280     |  1.902      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK1 |BUFGCTRL_X0Y29| No   |  653 |  0.418     |  2.057      |

+---------------------+--------------+------+------+------------+-------------+

|axi_i2s_adi_0_MCLK_p |              |      |      |            |             |

|             in_OBUF |BUFGCTRL_X0Y28| No   |   16 |  0.247     |  1.890      |

+---------------------+--------------+------+------+------------+-------------+

|axi_clkgen_0/axi_clk |              |      |      |            |             |

|gen_0/USER_LOGIC_I/i |              |      |      |            |             |

|_clkgen/buf_fb_clk_s |              |      |      |            |             |

|                     | BUFGCTRL_X0Y0| No   |    1 |  0.000     |  1.759      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK2 |BUFGCTRL_X0Y30| No   |    2 |  0.218     |  1.980      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0/cl |              |      |      |            |             |

|ock_generator_0/SIG_ |              |      |      |            |             |

|      MMCM1_CLKFBOUT |         Local|      |    1 |  0.000     |  0.014      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.000ns|    10.000ns|       0|           0

  0" 100 MHz HIGH 50| HOLD        |     0.000ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_1 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.147ns|     6.853ns|       0|           0

  1" 142.857 MHz HIGH 50| HOLD        |     0.014ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I | SETUP       |     0.587ns|     6.147ns|       0|           0

  _i_clkgen_mmcm_clk_s = PERIOD TIMEGRP     | HOLD        |     0.106ns|            |       0|           0

       "axi_clkgen_0_axi_clkgen_0_USER_LOGI |             |            |            |        |            

  C_I_i_clkgen_mmcm_clk_s"         TS_clk_f |             |            |            |        |            

  pga_2 * 0.742424242 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_2 = PERIOD TIMEGRP "clk_fpga_ | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0

  2" 200 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |    77.817ns|     3.562ns|       0|           0

  G_MMCM1_CLKOUT0 = PERIOD TIMEGRP          | HOLD        |     0.034ns|            |       0|           0

  "clock_generator_0_clock_generator_0_SIG_ |             |            |            |        |            

  MMCM1_CLKOUT0" TS_clk_fpga_2         * 0. |             |            |            |        |            

  061440678 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_tig_v_path" TIG   | SETUP       |         N/A|     7.151ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_from_2_cdc_to_pat | SETUP       |         N/A|     3.196ns|     N/A|           0

  h" TIG                                    |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_2_reset_resync_ | SETUP       |         N/A|     1.177ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_1_reset_resync_ | SETUP       |         N/A|     1.081ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_clk_fpga_2

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_clk_fpga_2                  |      5.000ns|      2.800ns|      4.564ns|            0|            0|            0|        43851|

| TS_axi_clkgen_0_axi_clkgen_0_U|      6.735ns|      6.147ns|          N/A|            0|            0|        43794|            0|

| SER_LOGIC_I_i_clkgen_mmcm_clk_|             |             |             |             |             |             |             |

| s                             |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     81.379ns|      3.562ns|          N/A|            0|            0|           57|            0|

| erator_0_SIG_MMCM1_CLKOUT0    |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 19 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 52 secs 

Total CPU time to PAR completion: 50 secs 



Peak Memory Usage:  823 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 21

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>


Loading device for application Rf_Device from file '7z020.nph' in environment


D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.4 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc7z020,-1 (ADVANCED 1.04 2012-12-04)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 414323 paths, 0 nets, and 27779 connections





Design statistics:


   Minimum period:  10.000ns (Maximum frequency: 100.000MHz)








Analysis completed Mon Sep 09 11:46:48 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 19 secs 






xflow done!

touch __xps/system_routed

xilperl D:/Xilinx/14.4/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.4 - Bitgen P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1

Opened constraints file system.pcf.



Mon Sep 09 11:47:01 2013



Running DRC.

WARNING:PhysDesignRules:367 - The signal <hdmi_int_IBUF> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3>> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfif

   o.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/

   grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

INFO:PhysDesignRules:2288 - The read port and write port clocks of BRAM

   instance,

   axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_S

   OF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.V6.I_LINEBUFFER_FIFO/fg91_inst/U0/xst_fifo_g

   enerator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/g

   nativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WI

   DE_PRIM36.ram, are using the same clock signal (synchronous clocking) with

   WRITE_FIRST mode specified. This configuration may encounter address

   collisions if the same address appears on both ports. It is suggested for

   this configuration to use READ_FIRST mode to avoid any conditions for address

   collision. See the FPGA Memory Resources User Guide for additional

   information.

DRC detected 0 errors and 19 warnings.  Please see the previously displayed

individual error or warning messages for more details.

Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!

********************************************************************************
At Local date and time: Mon Sep 09 12:06:29 2013
 make -f system.make clean started...
rm -f implementation/system.ngc

rm -f implementation/system_processing_system7_0_wrapper.ngc implementation/system_axi_vdma_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_axi_interconnect_2_wrapper.ngc implementation/system_axi_hdmi_tx_16b_0_wrapper.ngc implementation/system_axi_spdif_tx_0_wrapper.ngc implementation/system_axi_iic_0_wrapper.ngc implementation/system_axi_clkgen_0_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_util_vector_logic_0_wrapper.ngc implementation/system_axi_i2s_adi_0_wrapper.ngc implementation/system_util_i2c_mixer_0_wrapper.ngc implementation/system_axi_iic_1_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

rm -f implementation/system.bit

rm -f implementation/system.ncd

rm -f implementation/system_bd.bmm 

rm -f implementation/system_map.ncd 

rm -f implementation/download.bit 

rm -f __xps/system_bits

rm -rf implementation synthesis xst hdl

rm -rf xst.srp system.srp

rm -f __xps/ise/_xmsgs/bitinit.xmsgs

rm -rf __xps/ps7_instance.mhs

rm -rf simulation/behavioral

rm -f simgen.log

rm -f __xps/ise/_xmsgs/simgen.xmsgs

rm -f _impact.cmd

Done!

********************************************************************************
At Local date and time: Mon Sep 09 12:06:38 2013
 make -f system.make exporttosdk started...
"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp D:/Temp/fpgahdl_xilinx/cf_lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.4 - platgen Xilinx EDK 14.4 Build EDK_P.49d

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp

D:/Temp/fpgahdl_xilinx/cf_lib/ -msg __xps/ise/xmsgprops.lst system.mhs 



Parse D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/system.mhs ...



Read MPD definitions ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 300 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 304 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 308 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 312 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 7 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 319 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock

   'processing_system7_0_PS_CLK' is not specified. Clock DRCs will not be

   performed for IPs connected to that clock port, unless they are connected

   through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   axi_clkgen_0:clk. Clock DRCs will not be performed on this core and cores

   connected to it. 



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

INFO:EDK - INFO: DDR Base and High address in current configuration is

   0x00000000 and 0x1FFFFFFF respectively. 

INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable

   Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a

   master on processing_system7 AXI slave interfaces, please use the top half of

   the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For

   all other master, any subset of the DDR address can be used. See Xilinx

   Answer 47167 for more information. 

Address Map for Processor processing_system7_0

  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1

  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1

  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1

  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1

  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1



Checking platform address map ...



Checking platform configuration ...

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 7

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - 1 master(s) : 1

slave(s) 



Checking port drivers...

WARNING:EDK:4181 - PORT: hdmi_int, CONNECTOR: hdmi_int - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 32 

WARNING:EDK:4181 - PORT: util_vector_logic_0_Op1_pin, CONNECTOR:

   net_util_vector_logic_0_Op1_pin - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 35 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_0_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 



Performing Clock DRCs...



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 353 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_2; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

ZynqConfig: Terminated for tcl mode



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.


INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.




Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...



Managing cache ...



Elaborating instances ...

IPNAME:clock_generator INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 0.00 seconds



Constructing platform-level connectivity ...

Completion time: 1.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:processing_system7_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 60 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_vdma_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199

- Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_interconnect_1 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 222 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_interconnect_2 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 230 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_hdmi_tx_16b_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 238 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_spdif_tx_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

259 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_iic_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 280 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_clkgen_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

296 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:clock_generator_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 307 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:util_vector_logic_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 317 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_i2s_adi_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line

326 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:util_i2c_mixer_0 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs

line 361 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_iic_1 - D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 374 -

Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Running NGCBUILD ...

IPNAME:system_axi_vdma_0_wrapper INSTANCE:axi_vdma_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 199 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_vdma_0_wrapper.ngc

../system_axi_vdma_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_vdma_0_wrapper/system_

axi_vdma_0_wrapper.ngc" ...

Loading design module

"../system_axi_vdma_0_wrapper_fifo_generator_v9_1_2.ngc"...

Loading design module

"../system_axi_vdma_0_wrapper_fifo_generator_v9_1_1.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_vdma_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_vdma_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_interconnect_1_wrapper INSTANCE:axi_interconnect_1 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 222 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_interconnect_1_wrapper.ngc

../system_axi_interconnect_1_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_interconnect_1_wrapper

/system_axi_interconnect_1_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_interconnect_1_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_interconnect_1_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_interconnect_2_wrapper INSTANCE:axi_interconnect_2 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 230 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_interconnect_2_wrapper.ngc

../system_axi_interconnect_2_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/axi_interconnect_2_wrapper

/system_axi_interconnect_2_wrapper.ngc" ...

Loading design module

"../system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1.ngc"...

Loading design module

"../system_axi_interconnect_2_wrapper_fifo_generator_v9_1_2.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_interconnect_2_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_interconnect_2_wrapper.blc"...



NGCBUILD done.

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\system.mhs line 307 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/clock_generator_0_wrapper/

system_clock_generator_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 613.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc

Release 14.4 - Xflow P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc 

 

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

.... Copying flowfile D:/Xilinx/14.4/ISE_DS/ISE/xilinx/data/fpga.flw into

working directory D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation 



Using Flow File: D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/fpga.flw 

Using Option File(s): 

 D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc7z020clg484-1 -nt timestamp -bm system.bmm

"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc" -uc system.ucf

system.ngd 

#----------------------------------------------#

Release 14.4 - ngdbuild P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>





Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc7z020clg484-1 -nt timestamp -bm system.bmm


D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc -uc system.ucf


system.ngd





Reading NGO file


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system.ngc" ...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_processing_system7_


0_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_util_vector_logic_0


_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_i2s_adi_0_wrapp


er.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_1_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_2_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_spdif_tx_0_wrap


per.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_clkgen_0_wrappe


r.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_clock_generator_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_vdma_0_wrapper.


ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_hdmi_tx_16b_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_iic_0_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_iic_1_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_util_i2c_mixer_0_wr


apper.ngc"...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_processing_system7_


0_wrapper.ncf" to module "processing_system7_0"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_1_


wrapper.ncf" to module "axi_interconnect_1"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_interconnect_2_


wrapper.ncf" to module "axi_interconnect_2"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_adv7511_zed/implementation/system_axi_vdma_0_wrapper.


ncf" to module "axi_vdma_0"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_PORB_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_CLK_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_SRSTB_IBUF'.  All constraints associated with this


   symbol will be ignored.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.s_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_lev

el_out_d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.p_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_lev

el_in_d1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.s_level_out_d1_cdc_to_GN...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_out_

d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.p_level_in_d1_cdc_from_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_in_d

1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.s_level_in_d1_cdc_from_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_

d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out

_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_lev

el_in_d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.p_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_lev

el_out_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out


   _d1_cdc_to_GND_148_o_MUX_596_o11 TNM =...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_MUX_5

96_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_


   d1_cdc_from_GND_148_o_MUX_595_o11 TNM ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o_MUX_

595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   p_out_d1_cdc_to_GND_148_o_MUX_596_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_

MUX_596_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   s_in_d1_cdc_from_GND_148_o_MUX_595_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o

_MUX_595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_132_o_MUX_591_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_132_o

_MUX_591_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.s_out_d1_cdc_to_GND_70_o_MUX_51_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o

_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.p_in_d1_cdc_from_GND_70_o_MUX_50_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_

o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_70_o_MUX_51_o11 T...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_

MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_70_o_MUX_50_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o

_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_34_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_34_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_26_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_26_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_10_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_10_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_2/axi_interconnect_2\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_2_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_2/axi_interconnect_2/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_PORB_IBUF" LOC = B5>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_CLK_IBUF" LOC = F7>' could not be found and so


   the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_SRSTB_IBUF" LOC = C9>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_2_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_2_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   axi_clkgen_0/USER_LOGIC_I/i_clkgen/i_mmcm. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC


   TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s = PERIOD


   "axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s" TS_clk_fpga_2 *


   0.742424242 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   clock_generator_0/MMCM1_INST/MMCM_ADV_inst. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0" TS_clk_fpga_2


   * 0.061440678 HIGH 50>





Done...





Processing BMM file "system.bmm" ...





WARNING::53 - File 'system.bmm' is empty or has no BMM content.








Checking expanded design ...


WARNING:NgdBuild:486 - Attribute "CLOCK_HOLD" is not allowed on symbol


   "clock_generator_0/MMCM1_INST/MMCM_ADV_inst" of type "MMCME2_ADV".  This


   attribute will be ignored.


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_0/axi_iic_0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_1/axi_iic_1/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:452 - logical net 'N165' has no driver


WARNING:NgdBuild:452 - logical net 'N166' has no driver


WARNING:NgdBuild:452 - logical net 'N167' has no driver


WARNING:NgdBuild:452 - logical net 'N168' has no driver


WARNING:NgdBuild:452 - logical net 'N169' has no driver


WARNING:NgdBuild:452 - logical net 'N170' has no driver


WARNING:NgdBuild:452 - logical net 'N171' has no driver


WARNING:NgdBuild:452 - logical net 'N172' has no driver


WARNING:NgdBuild:452 - logical net 'N173' has no driver


WARNING:NgdBuild:452 - logical net 'N174' has no driver


WARNING:NgdBuild:452 - logical net 'N175' has no driver


WARNING:NgdBuild:452 - logical net 'N176' has no driver


WARNING:NgdBuild:452 - logical net 'N177' has no driver


WARNING:NgdBuild:452 - logical net 'N178' has no driver


WARNING:NgdBuild:452 - logical net 'N179' has no driver


WARNING:NgdBuild:452 - logical net 'N180' has no driver


WARNING:NgdBuild:452 - logical net 'N181' has no driver


WARNING:NgdBuild:452 - logical net 'N182' has no driver


WARNING:NgdBuild:452 - logical net 'N183' has no driver


WARNING:NgdBuild:452 - logical net 'N184' has no driver


WARNING:NgdBuild:452 - logical net 'N185' has no driver


WARNING:NgdBuild:452 - logical net 'N186' has no driver


WARNING:NgdBuild:452 - logical net 'N187' has no driver


WARNING:NgdBuild:452 - logical net 'N188' has no driver


WARNING:NgdBuild:452 - logical net 'N189' has no driver


WARNING:NgdBuild:452 - logical net 'N190' has no driver


WARNING:NgdBuild:452 - logical net 'N191' has no driver


WARNING:NgdBuild:452 - logical net 'N192' has no driver


WARNING:NgdBuild:452 - logical net 'N193' has no driver


WARNING:NgdBuild:452 - logical net 'N194' has no driver


WARNING:NgdBuild:452 - logical net 'N195' has no driver


WARNING:NgdBuild:452 - logical net 'N196' has no driver


WARNING:NgdBuild:452 - logical net 'N197' has no driver


WARNING:NgdBuild:452 - logical net 'N198' has no driver


WARNING:NgdBuild:452 - logical net 'N199' has no driver


WARNING:NgdBuild:452 - logical net 'N200' has no driver


WARNING:NgdBuild:452 - logical net 'N201' has no driver


WARNING:NgdBuild:452 - logical net 'N202' has no driver


WARNING:NgdBuild:452 - logical net 'N203' has no driver


WARNING:NgdBuild:452 - logical net 'N204' has no driver


WARNING:NgdBuild:452 - logical net 'N205' has no driver


WARNING:NgdBuild:452 - logical net 'N206' has no driver


WARNING:NgdBuild:452 - logical net 'N207' has no driver


WARNING:NgdBuild:452 - logical net 'N208' has no driver


WARNING:NgdBuild:452 - logical net 'N209' has no driver


WARNING:NgdBuild:452 - logical net 'N210' has no driver


WARNING:NgdBuild:452 - logical net 'N211' has no driver


WARNING:NgdBuild:452 - logical net 'N212' has no driver


WARNING:NgdBuild:452 - logical net 'N213' has no driver


WARNING:NgdBuild:452 - logical net 'N214' has no driver


WARNING:NgdBuild:452 - logical net 'N215' has no driver


WARNING:NgdBuild:452 - logical net 'N216' has no driver


WARNING:NgdBuild:452 - logical net 'N217' has no driver


WARNING:NgdBuild:452 - logical net 'N218' has no driver


WARNING:NgdBuild:452 - logical net 'N219' has no driver


WARNING:NgdBuild:452 - logical net 'N220' has no driver


WARNING:NgdBuild:452 - logical net 'N221' has no driver


WARNING:NgdBuild:452 - logical net 'N222' has no driver


WARNING:NgdBuild:452 - logical net 'N223' has no driver


WARNING:NgdBuild:452 - logical net 'N224' has no driver


WARNING:NgdBuild:452 - logical net 'N225' has no driver


WARNING:NgdBuild:452 - logical net 'N226' has no driver


WARNING:NgdBuild:452 - logical net 'N227' has no driver


WARNING:NgdBuild:452 - logical net 'N228' has no driver


WARNING:NgdBuild:452 - logical net 'N229' has no driver


WARNING:NgdBuild:452 - logical net 'N230' has no driver


WARNING:NgdBuild:452 - logical net 'N231' has no driver


WARNING:NgdBuild:452 - logical net 'N232' has no driver


WARNING:NgdBuild:452 - logical net 'N233' has no driver


WARNING:NgdBuild:452 - logical net 'N234' has no driver


WARNING:NgdBuild:452 - logical net 'N235' has no driver


WARNING:NgdBuild:452 - logical net 'N236' has no driver


WARNING:NgdBuild:452 - logical net 'N237' has no driver


WARNING:NgdBuild:452 - logical net 'N238' has no driver


WARNING:NgdBuild:452 - logical net 'N239' has no driver


WARNING:NgdBuild:452 - logical net 'N240' has no driver


WARNING:NgdBuild:452 - logical net 'N241' has no driver


WARNING:NgdBuild:452 - logical net 'N242' has no driver


WARNING:NgdBuild:452 - logical net 'N243' has no driver


WARNING:NgdBuild:452 - logical net 'N244' has no driver


WARNING:NgdBuild:452 - logical net 'N245' has no driver


WARNING:NgdBuild:452 - logical net 'N246' has no driver


WARNING:NgdBuild:452 - logical net 'N247' has no driver


WARNING:NgdBuild:452 - logical net 'N248' has no driver


WARNING:NgdBuild:452 - logical net 'N249' has no driver


WARNING:NgdBuild:452 - logical net 'N250' has no driver


WARNING:NgdBuild:452 - logical net 'N251' has no driver


WARNING:NgdBuild:452 - logical net 'N252' has no driver


WARNING:NgdBuild:452 - logical net 'N253' has no driver


WARNING:NgdBuild:452 - logical net 'N254' has no driver


WARNING:NgdBuild:452 - logical net 'N255' has no driver


WARNING:NgdBuild:452 - logical net 'N256' has no driver


WARNING:NgdBuild:452 - logical net 'N257' has no driver


WARNING:NgdBuild:452 - logical net 'N258' has no driver


WARNING:NgdBuild:452 - logical net 'N259' has no driver


WARNING:NgdBuild:452 - logical net 'N260' has no driver


WARNING:NgdBuild:452 - logical net 'N261' has no driver


WARNING:NgdBuild:452 - logical net 'N262' has no driver


WARNING:NgdBuild:452 - logical net 'N263' has no driver


WARNING:NgdBuild:452 - logical net 'N264' has no driver


WARNING:NgdBuild:452 - logical net 'N265' has no driver


WARNING:NgdBuild:452 - logical net 'N266' has no driver


WARNING:NgdBuild:452 - logical net 'N267' has no driver


WARNING:NgdBuild:452 - logical net 'N268' has no driver


WARNING:NgdBuild:452 - logical net 'N269' has no driver


WARNING:NgdBuild:452 - logical net 'N270' has no driver


WARNING:NgdBuild:452 - logical net 'N271' has no driver


WARNING:NgdBuild:452 - logical net 'N272' has no driver


WARNING:NgdBuild:452 - logical net 'N273' has no driver


WARNING:NgdBuild:452 - logical net 'N274' has no driver


WARNING:NgdBuild:452 - logical net 'N275' has no driver


WARNING:NgdBuild:452 - logical net 'N276' has no driver


WARNING:NgdBuild:452 - logical net 'N277' has no driver


WARNING:NgdBuild:452 - logical net 'N278' has no driver


WARNING:NgdBuild:452 - logical net 'N279' has no driver


WARNING:NgdBuild:452 - logical net 'N280' has no driver


WARNING:NgdBuild:452 - logical net 'N316' has no driver


WARNING:NgdBuild:452 - logical net 'N317' has no driver


WARNING:NgdBuild:452 - logical net 'N318' has no driver


WARNING:NgdBuild:452 - logical net 'N319' has no driver


WARNING:NgdBuild:452 - logical net 'N320' has no driver


WARNING:NgdBuild:452 - logical net 'N321' has no driver


WARNING:NgdBuild:452 - logical net 'N322' has no driver


WARNING:NgdBuild:452 - logical net 'N323' has no driver


WARNING:NgdBuild:452 - logical net 'N324' has no driver


WARNING:NgdBuild:452 - logical net 'N325' has no driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings: 198





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  32 sec


Total CPU time to NGDBUILD completion:   32 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.4 - Map P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<D:/Xilinx/14.4/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<D:/Xilinx/14.4/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "7z020clg484-1".


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB" is not constrained


   (LOC) to a specific location.


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 34 secs 


Total CPU  time at the beginning of Placer: 34 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:b46c4639) REAL time: 39 secs 





Phase 2.7  Design Feasibility Check


WARNING:Place:838 - An IO Bus with more than one IO standard is found.


   Components associated with this bus are as follows: 


   	 Comp: processing_system7_0_GPIO_pin<0>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<1>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<2>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<3>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<4>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<5>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<6>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<7>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<8>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<9>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<10>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<11>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<12>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<13>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<14>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<15>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<16>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<17>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<18>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<19>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<20>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<21>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<22>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<23>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<24>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<25>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<26>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<27>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<28>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<29>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<30>   IOSTANDARD = LVCMOS25








Phase 2.7  Design Feasibility Check (Checksum:b46c4639) REAL time: 39 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:b46c4639) REAL time: 39 secs 





Phase 4.2  Initial Placement for Architecture Specific Features





Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:bb0559f) REAL time: 47 secs 





Phase 5.30  Global Clock Region Assignment


Phase 5.30  Global Clock Region Assignment (Checksum:bb0559f) REAL time: 47 secs 





Phase 6.3  Local Placement Optimization


Phase 6.3  Local Placement Optimization (Checksum:bb0559f) REAL time: 47 secs 





Phase 7.5  Local Placement Optimization


Phase 7.5  Local Placement Optimization (Checksum:bb0559f) REAL time: 47 secs 





Phase 8.8  Global Placement


........................................


....


............................................................................................


..............................................................................................................................................................................................


............................................................................................................................................................


Phase 8.8  Global Placement (Checksum:164bf083) REAL time: 2 mins 5 secs 





Phase 9.5  Local Placement Optimization


Phase 9.5  Local Placement Optimization (Checksum:164bf083) REAL time: 2 mins 5 secs 





Phase 10.18  Placement Optimization


Phase 10.18  Placement Optimization (Checksum:bd2c5eac) REAL time: 2 mins 18 secs 





Phase 11.5  Local Placement Optimization


Phase 11.5  Local Placement Optimization (Checksum:bd2c5eac) REAL time: 2 mins 18 secs 





Phase 12.34  Placement Validation


Phase 12.34  Placement Validation (Checksum:bd2c5eac) REAL time: 2 mins 18 secs 





Total REAL time to Placer completion: 2 mins 19 secs 


Total CPU  time to Placer completion: 2 mins 17 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:   26


Slice Logic Utilization:


  Number of Slice Registers:                 4,935 out of 106,400    4


    Number used as Flip Flops:               4,925


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:               10


  Number of Slice LUTs:                      5,177 out of  53,200    9


    Number used as logic:                    4,586 out of  53,200    8


      Number using O6 output only:           3,217


      Number using O5 output only:             127


      Number using O5 and O6:                1,242


      Number used as ROM:                        0


    Number used as Memory:                     405 out of  17,400    2


      Number used as Dual Port RAM:             74


        Number using O6 output only:             6


        Number using O5 output only:             5


        Number using O5 and O6:                 63


      Number used as Single Port RAM:            0


      Number used as Shift Register:           331


        Number using O6 output only:           323


        Number using O5 output only:             0


        Number using O5 and O6:                  8


    Number used exclusively as route-thrus:    186


      Number with same-slice register load:     49


      Number with same-slice carry load:       137


      Number with other load:                    0





Slice Logic Distribution:


  Number of occupied Slices:                 2,544 out of  13,300   19


  Number of LUT Flip Flop pairs used:        6,990


    Number with an unused Flip Flop:         2,456 out of   6,990   35


    Number with an unused LUT:               1,813 out of   6,990   25


    Number of fully used LUT-FF pairs:       2,721 out of   6,990   38


    Number of unique control sets:             304


    Number of slice register sites lost


      to control set restrictions:           1,127 out of 106,400    1





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.


  OVERMAPPING of BRAM resources should be ignored if the design is


  over-mapped for a non-BRAM resource or if placement fails.





IO Utilization:


  Number of bonded IOBs:                        78 out of     200   39


    Number of LOCed IOBs:                       78 out of      78  100


  Number of bonded IOPAD:                      130 out of     130  100


    IOB Flip Flops:                             25





Specific Feature Utilization:


  Number of RAMB36E1/FIFO36E1s:                  3 out of     140    2


    Number using RAMB36E1 only:                  3


    Number using FIFO36E1 only:                  0


  Number of RAMB18E1/FIFO18E1s:                  0 out of     280    0


  Number of BUFG/BUFGCTRLs:                      6 out of      32   18


    Number used as BUFGs:                        6


    Number used as BUFGCTRLs:                    0


  Number of IDELAYE2/IDELAYE2_FINEDELAYs:        0 out of     200    0


  Number of ILOGICE2/ILOGICE3/ISERDESE2s:        1 out of     200    1


    Number used as ILOGICE2s:                    1


  Number used as  ILOGICE3s:                     0


    Number used as ISERDESE2s:                   0


  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0


  Number of OLOGICE2/OLOGICE3/OSERDESE2s:       55 out of     200   27


    Number used as OLOGICE2s:                   55


    Number used as OLOGICE3s:                    0


    Number used as OSERDESE2s:                   0


  Number of PHASER_IN/PHASER_IN_PHYs:            0 out of      16    0


  Number of PHASER_OUT/PHASER_OUT_PHYs:          0 out of      16    0


  Number of BSCANs:                              0 out of       4    0


  Number of BUFHCEs:                             0 out of      72    0


  Number of BUFRs:                               0 out of      16    0


  Number of CAPTUREs:                            0 out of       1    0


  Number of DNA_PORTs:                           0 out of       1    0


  Number of DSP48E1s:                            0 out of     220    0


  Number of EFUSE_USRs:                          0 out of       1    0


  Number of FRAME_ECCs:                          0 out of       1    0


  Number of ICAPs:                               0 out of       2    0


  Number of IDELAYCTRLs:                         0 out of       4    0


  Number of IN_FIFOs:                            0 out of      16    0


  Number of MMCME2_ADVs:                         2 out of       4   50


  Number of OUT_FIFOs:                           0 out of      16    0


  Number of PHASER_REFs:                         0 out of       4    0


  Number of PHY_CONTROLs:                        0 out of       4    0


  Number of PLLE2_ADVs:                          0 out of       4    0


  Number of PS7s:                                1 out of       1  100


  Number of STARTUPs:                            0 out of       1    0


  Number of XADCs:                               0 out of       1    0





Average Fanout of Non-Clock Nets:                3.36





Peak Memory Usage:  971 MB


Total REAL time to MAP completion:  2 mins 25 secs 


Total CPU time to MAP completion:   2 mins 23 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - par P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/data/parBmgr.acd> with local file

<D:/Xilinx/14.4/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)





Device speed data version:  "ADVANCED 1.04 2012-12-04".







Device Utilization Summary:



   Number of BUFGs                           6 out of 32     18

   Number of ILOGICE2s                       1 out of 200     1

   Number of External IOB33s                78 out of 200    39

      Number of LOCed IOB33s                78 out of 78    100



   Number of External IOPADs               130 out of 130   100

      Number of LOCed IOPADs               127 out of 130    97



   Number of MMCME2_ADVs                     2 out of 4      50

   Number of OLOGICE2s                      55 out of 200    27

   Number of PS7s                            1 out of 1     100

   Number of RAMB36E1s                       3 out of 140     2

   Number of Slices                       2544 out of 13300  19

   Number of Slice Registers              4935 out of 106400  4

      Number used as Flip Flops           4935

      Number used as Latches                 0

      Number used as LatchThrus              0



   Number of Slice LUTS                   5177 out of 53200   9

   Number of Slice LUT-Flip Flop pairs    6829 out of 53200  12





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 16 secs 

Finished initial Timing Analysis.  REAL time: 17 secs 



WARNING:Par:288 - The signal hdmi_int_IBUF has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3> has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mra

   m_RAM_RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route this

   signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM

   _RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

Starting Router





Phase  1  : 33344 unrouted;      REAL time: 18 secs 



Phase  2  : 26228 unrouted;      REAL time: 19 secs 



Phase  3  : 8558 unrouted;      REAL time: 28 secs 



Phase  4  : 8580 unrouted; (Setup:0, Hold:40229, Component Switching Limit:0)     REAL time: 33 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 42 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 42 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 42 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:35306, Component Switching Limit:0)     REAL time: 42 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 44 secs 

Total REAL time to Router completion: 44 secs 

Total CPU time to Router completion: 46 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK0 |BUFGCTRL_X0Y31| No   |  774 |  0.427     |  2.054      |

+---------------------+--------------+------+------+------------+-------------+

|axi_hdmi_tx_16b_0_hd |              |      |      |            |             |

|          mi_ref_clk | BUFGCTRL_X0Y1| No   |  368 |  0.280     |  1.902      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK1 |BUFGCTRL_X0Y29| No   |  653 |  0.418     |  2.057      |

+---------------------+--------------+------+------+------------+-------------+

|axi_i2s_adi_0_MCLK_p |              |      |      |            |             |

|             in_OBUF |BUFGCTRL_X0Y28| No   |   16 |  0.247     |  1.890      |

+---------------------+--------------+------+------+------------+-------------+

|axi_clkgen_0/axi_clk |              |      |      |            |             |

|gen_0/USER_LOGIC_I/i |              |      |      |            |             |

|_clkgen/buf_fb_clk_s |              |      |      |            |             |

|                     | BUFGCTRL_X0Y0| No   |    1 |  0.000     |  1.759      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK2 |BUFGCTRL_X0Y30| No   |    2 |  0.218     |  1.980      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0/cl |              |      |      |            |             |

|ock_generator_0/SIG_ |              |      |      |            |             |

|      MMCM1_CLKFBOUT |         Local|      |    1 |  0.000     |  0.014      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.000ns|    10.000ns|       0|           0

  0" 100 MHz HIGH 50| HOLD        |     0.000ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_1 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.147ns|     6.853ns|       0|           0

  1" 142.857 MHz HIGH 50| HOLD        |     0.014ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I | SETUP       |     0.587ns|     6.147ns|       0|           0

  _i_clkgen_mmcm_clk_s = PERIOD TIMEGRP     | HOLD        |     0.106ns|            |       0|           0

       "axi_clkgen_0_axi_clkgen_0_USER_LOGI |             |            |            |        |            

  C_I_i_clkgen_mmcm_clk_s"         TS_clk_f |             |            |            |        |            

  pga_2 * 0.742424242 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_2 = PERIOD TIMEGRP "clk_fpga_ | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0

  2" 200 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |    77.817ns|     3.562ns|       0|           0

  G_MMCM1_CLKOUT0 = PERIOD TIMEGRP          | HOLD        |     0.034ns|            |       0|           0

  "clock_generator_0_clock_generator_0_SIG_ |             |            |            |        |            

  MMCM1_CLKOUT0" TS_clk_fpga_2         * 0. |             |            |            |        |            

  061440678 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_tig_v_path" TIG   | SETUP       |         N/A|     7.151ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_from_2_cdc_to_pat | SETUP       |         N/A|     3.196ns|     N/A|           0

  h" TIG                                    |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_2_reset_resync_ | SETUP       |         N/A|     1.177ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_1_reset_resync_ | SETUP       |         N/A|     1.081ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_clk_fpga_2

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_clk_fpga_2                  |      5.000ns|      2.800ns|      4.564ns|            0|            0|            0|        43851|

| TS_axi_clkgen_0_axi_clkgen_0_U|      6.735ns|      6.147ns|          N/A|            0|            0|        43794|            0|

| SER_LOGIC_I_i_clkgen_mmcm_clk_|             |             |             |             |             |             |             |

| s                             |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     81.379ns|      3.562ns|          N/A|            0|            0|           57|            0|

| erator_0_SIG_MMCM1_CLKOUT0    |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 19 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 48 secs 

Total CPU time to PAR completion: 48 secs 



Peak Memory Usage:  823 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 21

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>


Loading device for application Rf_Device from file '7z020.nph' in environment


D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.4 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc7z020,-1 (ADVANCED 1.04 2012-12-04)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 414323 paths, 0 nets, and 27779 connections





Design statistics:


   Minimum period:  10.000ns (Maximum frequency: 100.000MHz)








Analysis completed Mon Sep 09 12:21:34 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 19 secs 






xflow done!

touch __xps/system_routed

xilperl D:/Xilinx/14.4/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.4 - Bitgen P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1

Opened constraints file system.pcf.



Mon Sep 09 12:21:47 2013



Running DRC.

WARNING:PhysDesignRules:367 - The signal <hdmi_int_IBUF> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3>> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfif

   o.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/

   grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

INFO:PhysDesignRules:2288 - The read port and write port clocks of BRAM

   instance,

   axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_S

   OF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.V6.I_LINEBUFFER_FIFO/fg91_inst/U0/xst_fifo_g

   enerator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/g

   nativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WI

   DE_PRIM36.ram, are using the same clock signal (synchronous clocking) with

   WRITE_FIRST mode specified. This configuration may encounter address

   collisions if the same address appears on both ports. It is suggested for

   this configuration to use READ_FIRST mode to avoid any conditions for address

   collision. See the FPGA Memory Resources User Guide for additional

   information.

DRC detected 0 errors and 19 warnings.  Please see the previously displayed

individual error or warning messages for more details.

Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!

********************************************************************************
At Local date and time: Mon Sep 09 12:22:21 2013
 xsdk.exe -hwspec D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\SDK\SDK_Export\hw\system.xml started...
Xilinx Software Development Kit

Xilinx EDK 14.4 Build EDK_P.49d

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Done!
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Overriding Xilinx file <TextEditor.cfg> with local file <D:/Xilinx/14.4/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Overriding Xilinx file <TextEditor.cfg> with local file <D:/Xilinx/14.4/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_adv7511_zed\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 14.4 Build EDK_P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Assigned Driver generic 1.00.a for instance axi_interconnect_0
axi_interconnect_0 has been added to the project
WARNING:EDK:3712 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - Frequency of the interconnect's clock port could not be determined. All IPs in the design will be considered to be asynchronous with respect to the interconnect. This will lead to more resource usage. You can avoid this by specifying the clock frequency on the port that the interconnect's clock is connected to.
ERROR:EDK:4125 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0, PORT: INTERCONNECT_ARESETN - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
WARNING:EDK:3712 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0 - Frequency of the interconnect's clock port could not be determined. All IPs in the design will be considered to be asynchronous with respect to the interconnect. This will lead to more resource usage. You can avoid this by specifying the clock frequency on the port that the interconnect's clock is connected to.
ERROR:EDK:4125 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_0, PORT: INTERCONNECT_ARESETN - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
WARNING:EDK:3712 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Frequency of the interconnect's clock port could not be determined. All IPs in the design will be considered to be asynchronous with respect to the interconnect. This will lead to more resource usage. You can avoid this by specifying the clock frequency on the port that the interconnect's clock is connected to.
ERROR:EDK:4125 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3, PORT: INTERCONNECT_ARESETN - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
ERROR:EDK:4125 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3, PORT: INTERCONNECT_ARESETN - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
Overriding Xilinx file <TextEditor.cfg> with local file <D:/Xilinx/14.4/ISE_DS/EDK/data/TextEditor.cfg>
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\etc\system.gui

********************************************************************************
At Local date and time: Tue Sep 24 15:23:55 2013
 make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"

pscgen -mhs system.mhs -expdir SDK\SDK_Export\hw

ZynqConfig: Terminated for pscgen mode

psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml 

Release 14.4 - psf2Edward EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 200 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 223 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 231 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 281 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 308 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 375 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 200 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 223 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 231 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 281 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 308 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 375 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 200 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 223 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 231 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 281 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 308 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 375 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 200 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 223 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 231 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 281 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 308 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 375 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 



Overriding IP level properties ...



Computing clock values...



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor ps7_cortexa9_0

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0

Address Map for Processor ps7_cortexa9_1

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0



Checking platform address map ...

WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000fe81 is greater than

   32

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

Conversion to XML complete.

xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html  -make_docs_local

Release 14.4 - xdsgen EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Generated Block Diagram.

Rasterizing processing_system7_0.jpg.....

Rasterizing axi_vdma_0.jpg.....

Rasterizing axi_interconnect_1.jpg.....

Rasterizing axi_interconnect_2.jpg.....

Rasterizing axi_hdmi_tx_16b_0.jpg.....

Rasterizing axi_spdif_tx_0.jpg.....

Rasterizing axi_iic_0.jpg.....

Rasterizing axi_clkgen_0.jpg.....

Rasterizing clock_generator_0.jpg.....

Rasterizing util_vector_logic_0.jpg.....

Rasterizing axi_i2s_adi_0.jpg.....

Rasterizing util_i2c_mixer_0.jpg.....

Rasterizing axi_iic_1.jpg.....

Rasterizing axi_interconnect_3.jpg.....

Rasterizing system_blkd.jpg.....

Report generated.

Report generation completed.

"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp D:/Temp/fpgahdl_xilinx/cf_lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.4 - platgen Xilinx EDK 14.4 Build EDK_P.49d

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp

D:/Temp/fpgahdl_xilinx/cf_lib/ -msg __xps/ise/xmsgprops.lst system.mhs 



Parse D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/system.mhs ...



Read MPD definitions ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 200 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 223 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 231 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 281 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 308 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 375 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 200 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 223 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 231 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 281 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 308 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 375 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 300 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 304 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 308 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 312 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 7 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 319 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_3 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock

   'processing_system7_0_PS_CLK' is not specified. Clock DRCs will not be

   performed for IPs connected to that clock port, unless they are connected

   through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   axi_clkgen_0:clk. Clock DRCs will not be performed on this core and cores

   connected to it. 



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

INFO:EDK - INFO: DDR Base and High address in current configuration is

   0x00000000 and 0x1FFFFFFF respectively. 

INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable

   Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a

   master on processing_system7 AXI slave interfaces, please use the top half of

   the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For

   all other master, any subset of the DDR address can be used. See Xilinx

   Answer 47167 for more information. 

Address Map for Processor processing_system7_0

  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1

  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1

  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1

  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1

  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1



Checking platform address map ...



Checking platform configuration ...

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 7

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - 1 master(s) : 1

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - 0 master(s) : 0

slave(s) 

ERROR:EDK:4119 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - must

   have atleast 1 master assigned -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 

ERROR:EDK:4133 - IPNAME:axi_interconnect, INSTANCE:axi_interconnect_3 - must

   have atleast 1 slave assigned -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 

ERROR:EDK:440 - platgen failed with errors!

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 200 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 223 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 231 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 281 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 308 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 375 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 387 

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_

   generator.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

make: *** [implementation/system.bmm] Error 2

Done!
Assigned Driver axivdma 4.02.a for instance axi_vdma_1
axi_vdma_1 has been added to the project
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: m_axis_mm2s_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: s_axis_s2mm_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PARAMETER: C_BASEADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PARAMETER: C_HIGHADDR - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a value in the MHS. 
WARNING:EDK:2137 - Peripheral axi_vdma_1 is not accessible from any processor in the system. Check Bus Interface connections and address parameters. 
Address Map for Processor processing_system7_0
  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1
  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1
  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1
  (0x43040000-0x4304ffff) axi_vdma_1	axi_interconnect_1
  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1
  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1
  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1
  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1
WARNING:EDK:4058 - INSTANCE: axi_vdma_0, BUS_INTERFACE: M_AXI_MM2S -  is not connected to any slave. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: m_axis_mm2s_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
WARNING:EDK:4058 - INSTANCE: axi_vdma_0, BUS_INTERFACE: M_AXI_MM2S -  is not connected to any slave. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: m_axis_mm2s_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
WARNING:EDK:4058 - INSTANCE: axi_vdma_0, BUS_INTERFACE: M_AXI_MM2S -  is not connected to any slave. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: m_axis_mm2s_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI_LITE to axi_interconnect_1
INFO:EDK - Connect clock port s_axi_lite_aclk to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - Connect bus interface M_AXI_MM2S to axi_interconnect_2
INFO:EDK - Connect clock port m_axi_mm2s_aclk to processing_system7_0_FCLK_CLK1
INFO:EDK - Set master of S_AXI_HP0 in processing_system7_0 to axi_vdma_1.M_AXI_MM2S
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: axi_vdma_1
WARNING:EDK:4058 - INSTANCE: axi_vdma_0, BUS_INTERFACE: M_AXI_MM2S -  is not connected to any slave. 
WARNING:EDK:4058 - INSTANCE: axi_vdma_1, BUS_INTERFACE: M_AXI_MM2S -  is not connected to any slave. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: m_axis_mm2s_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
WARNING:EDK:4058 - INSTANCE: axi_vdma_0, BUS_INTERFACE: M_AXI_MM2S -  is not connected to any slave. 
WARNING:EDK:4058 - INSTANCE: axi_vdma_1, BUS_INTERFACE: M_AXI_MM2S -  is not connected to any slave. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: m_axis_mm2s_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
WARNING:EDK:4058 - INSTANCE: axi_vdma_1, BUS_INTERFACE: M_AXI_MM2S -  is not connected to any slave. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: m_axis_mm2s_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
ERROR:EDK:4125 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1, PORT: m_axis_mm2s_aclk - ASSIGNMENT=REQUIRE is defined in the MPD. You must specify a connection in the MHS. 
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 

********************************************************************************
At Local date and time: Tue Sep 24 15:29:31 2013
 make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"

pscgen -mhs system.mhs -expdir SDK\SDK_Export\hw

ZynqConfig: Terminated for pscgen mode

psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml 

Release 14.4 - psf2Edward EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 



Overriding IP level properties ...



Computing clock values...



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor ps7_cortexa9_0

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0

Address Map for Processor ps7_cortexa9_1

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0



Checking platform address map ...

WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000fe81 is greater than

   32

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

Conversion to XML complete.

xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html  -make_docs_local

Release 14.4 - xdsgen EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Generated Block Diagram.

Rasterizing processing_system7_0.jpg.....

Rasterizing axi_vdma_0.jpg.....

Rasterizing axi_interconnect_1.jpg.....

Rasterizing axi_interconnect_2.jpg.....

Rasterizing axi_hdmi_tx_16b_0.jpg.....

Rasterizing axi_spdif_tx_0.jpg.....

Rasterizing axi_iic_0.jpg.....

Rasterizing axi_clkgen_0.jpg.....

Rasterizing clock_generator_0.jpg.....

Rasterizing util_vector_logic_0.jpg.....

Rasterizing axi_i2s_adi_0.jpg.....

Rasterizing util_i2c_mixer_0.jpg.....

Rasterizing axi_iic_1.jpg.....

Rasterizing axi_interconnect_3.jpg.....

Rasterizing axi_vdma_1.jpg.....

Rasterizing system_blkd.jpg.....

org.apache.batik.transcoder.TranscoderException: nul

Enclosed Exception

file:/D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/__xps/.dswkshop/system_blkd.svg:-

The attribute "width" of the element <rect> can not be negative

	at org.apache.batik.transcoder.SVGAbstractTranscoder.transcode(Unknown Source)

	at org.apache.batik.transcoder.image.ImageTranscoder.transcode(Unknown Source)

	at org.apache.batik.transcoder.XMLAbstractTranscoder.transcode(Unknown Source)

	at org.apache.batik.transcoder.SVGAbstractTranscoder.transcode(Unknown Source)

	at MdtSvgDiag_Rasterize._rasterizeIMG(MdtSvgDiag_Rasterize.java:156)

	at MdtSvgDiag_Rasterize.batchMode(MdtSvgDiag_Rasterize.java:91)

	at MdtSvgDiag_Rasterize.main(MdtSvgDiag_Rasterize.java:24)

Report generated.

Report generation completed.

"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp D:/Temp/fpgahdl_xilinx/cf_lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.4 - platgen Xilinx EDK 14.4 Build EDK_P.49d

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp

D:/Temp/fpgahdl_xilinx/cf_lib/ -msg __xps/ise/xmsgprops.lst system.mhs 



Parse D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/system.mhs ...



Read MPD definitions ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 300 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 304 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 308 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 312 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 7 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 319 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_3 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock

   'processing_system7_0_PS_CLK' is not specified. Clock DRCs will not be

   performed for IPs connected to that clock port, unless they are connected

   through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   axi_clkgen_0:clk. Clock DRCs will not be performed on this core and cores

   connected to it. 



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

INFO:EDK - INFO: DDR Base and High address in current configuration is

   0x00000000 and 0x1FFFFFFF respectively. 

INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable

   Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a

   master on processing_system7 AXI slave interfaces, please use the top half of

   the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For

   all other master, any subset of the DDR address can be used. See Xilinx

   Answer 47167 for more information. 

Address Map for Processor processing_system7_0

  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	axi_interconnect_1

  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1

  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1

  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1

  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1



Checking platform address map ...

ERROR:EDK:3830 - CLK S_AXI_HP1_ACLK on INSTANCE processing_system7_0 is not

   connected. All AXI master/slaves are required to be clocked.



Checking platform configuration ...

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 8

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - 1 master(s) : 1

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - 1 master(s) : 1

slave(s) 

ERROR:EDK:2159 - Point-2-point interface connector 'axi_vdma_1_m_axis_mm2s' must

   have only 2 connection points:

   	IPNAME:axi_vdma INSTANCE:axi_vdma_1 BUS_INTERFACE:M_AXIS_MM2S-

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396

ERROR:EDK:1420 - For point-2-point interface connector 'axi_vdma_1_m_axis_mm2s',

   the BUS_TYPE value of the connection points must have a TARGET and an

   INITIATOR:

   	IPNAME:axi_vdma INSTANCE:axi_vdma_1 BUS_INTERFACE:M_AXIS_MM2S

   BUS_TYPE=INITIATOR - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

   396

ERROR:EDK:440 - platgen failed with errors!

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 202 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 225 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 233 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 283 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 310 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 377 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 389 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 396 

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_

   generator.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf

make: *** [implementation/system.bmm] Error 2

Done!
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 
Assigned Driver generic 1.00.a for instance axi_ssm2518_0
axi_ssm2518_0 has been added to the project
WARNING:EDK:2137 - Peripheral axi_ssm2518_0 is not accessible from any processor in the system. Check Bus Interface connections and address parameters. 
Address Map for Processor processing_system7_0
  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1
  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1
  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1
  (0x43040000-0x4304ffff) axi_vdma_1	axi_interconnect_1
  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1
  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1
  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1
  (0x77620000-0x7762ffff) axi_ssm2518_0	axi_interconnect_1
  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1
INFO:EDK - Do connection by refering to bus interface of a processing_system7_0 in design
INFO:EDK - Connect bus interface S_AXI to axi_interconnect_1
INFO:EDK - Connect clock port s_axi_aclk to processing_system7_0_FCLK_CLK0
INFO:EDK - Successfully did connection by refering to M_AXI_GP0 bus interface in processing_system7_0
INFO:EDK - External IO port grouping doneINFO:EDK - Generate address successfully
INFO:EDK - Successfully finished auto bus connection for IP instance: axi_ssm2518_0

********************************************************************************
At Local date and time: Tue Sep 24 15:34:21 2013
 make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"

pscgen -mhs system.mhs -expdir SDK\SDK_Export\hw

ZynqConfig: Terminated for pscgen mode

psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml 

Release 14.4 - psf2Edward EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 



Overriding IP level properties ...



Computing clock values...



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor ps7_cortexa9_0

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77620000-0x7762ffff)

axi_ssm2518_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0

Address Map for Processor ps7_cortexa9_1

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77620000-0x7762ffff)

axi_ssm2518_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0



Checking platform address map ...

WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000fe81 is greater than

   32

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

Conversion to XML complete.

xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html  -make_docs_local

Release 14.4 - xdsgen EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Generated Block Diagram.

Rasterizing processing_system7_0.jpg.....

Rasterizing axi_vdma_0.jpg.....

Rasterizing axi_interconnect_1.jpg.....

Rasterizing axi_interconnect_2.jpg.....

Rasterizing axi_hdmi_tx_16b_0.jpg.....

Rasterizing axi_spdif_tx_0.jpg.....

Rasterizing axi_iic_0.jpg.....

Rasterizing axi_clkgen_0.jpg.....

Rasterizing clock_generator_0.jpg.....

Rasterizing util_vector_logic_0.jpg.....

Rasterizing axi_i2s_adi_0.jpg.....

Rasterizing util_i2c_mixer_0.jpg.....

Rasterizing axi_iic_1.jpg.....

Rasterizing axi_interconnect_3.jpg.....

Rasterizing axi_vdma_1.jpg.....

Rasterizing axi_ssm2518_0.jpg.....

Rasterizing system_blkd.jpg.....

Report generated.

Report generation completed.

"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp D:/Temp/fpgahdl_xilinx/cf_lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.4 - platgen Xilinx EDK 14.4 Build EDK_P.49d

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp

D:/Temp/fpgahdl_xilinx/cf_lib/ -msg __xps/ise/xmsgprops.lst system.mhs 



Parse D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/system.mhs ...



Read MPD definitions ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 300 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 304 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 308 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 312 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 7 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 319 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_3 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock

   'processing_system7_0_PS_CLK' is not specified. Clock DRCs will not be

   performed for IPs connected to that clock port, unless they are connected

   through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   axi_clkgen_0:clk. Clock DRCs will not be performed on this core and cores

   connected to it. 



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

INFO:EDK - INFO: DDR Base and High address in current configuration is

   0x00000000 and 0x1FFFFFFF respectively. 

INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable

   Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a

   master on processing_system7 AXI slave interfaces, please use the top half of

   the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For

   all other master, any subset of the DDR address can be used. See Xilinx

   Answer 47167 for more information. 

Address Map for Processor processing_system7_0

  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	axi_interconnect_1

  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1

  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1

  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1

  (0x77620000-0x7762ffff) axi_ssm2518_0	axi_interconnect_1

  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1



Checking platform address map ...



Checking platform configuration ...

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 9

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - 1 master(s) : 1

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - 1 master(s) : 1

slave(s) 



Checking port drivers...

WARNING:EDK:4181 - PORT: hdmi_int, CONNECTOR: hdmi_int - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 32 

WARNING:EDK:4181 - PORT: util_vector_logic_0_Op1_pin, CONNECTOR:

   net_util_vector_logic_0_Op1_pin - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 35 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_0_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_1_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 



Performing Clock DRCs...



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 353 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_2; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_3; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_3 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_

   generator.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf

ERROR:EDK:3900 - issued from TCL procedure "zynqconfig_do" line 34

   processing_system7_0 (processing_system7) - MHS file editing for Zynq related

   parameters is not allowed. Please use Zynq tab in XPS for PS configuration.

    Value of parameter C_FCLK_CLK3_FREQ (50000000) in MHS conflicts with the

   setting in Zynq tab. Value of C_FCLK_CLK3_FREQ should be 62500000  

ERROR:EDK:440 - platgen failed with errors!

make: *** [implementation/system.bmm] Error 2

Done!

********************************************************************************
At Local date and time: Tue Sep 24 15:36:07 2013
 make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"

pscgen -mhs system.mhs -expdir SDK\SDK_Export\hw

ZynqConfig: Terminated for pscgen mode

psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml 

Release 14.4 - psf2Edward EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 



Overriding IP level properties ...



Computing clock values...



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor ps7_cortexa9_0

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77620000-0x7762ffff)

axi_ssm2518_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0

Address Map for Processor ps7_cortexa9_1

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77620000-0x7762ffff)

axi_ssm2518_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0



Checking platform address map ...

WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000fe81 is greater than

   32

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

Conversion to XML complete.

xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html  -make_docs_local

Release 14.4 - xdsgen EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Generated Block Diagram.

Rasterizing processing_system7_0.jpg.....

Rasterizing axi_vdma_0.jpg.....

Rasterizing axi_interconnect_1.jpg.....

Rasterizing axi_interconnect_2.jpg.....

Rasterizing axi_hdmi_tx_16b_0.jpg.....

Rasterizing axi_spdif_tx_0.jpg.....

Rasterizing axi_iic_0.jpg.....

Rasterizing axi_clkgen_0.jpg.....

Rasterizing clock_generator_0.jpg.....

Rasterizing util_vector_logic_0.jpg.....

Rasterizing axi_i2s_adi_0.jpg.....

Rasterizing util_i2c_mixer_0.jpg.....

Rasterizing axi_iic_1.jpg.....

Rasterizing axi_interconnect_3.jpg.....

Rasterizing axi_vdma_1.jpg.....

Rasterizing axi_ssm2518_0.jpg.....

Rasterizing system_blkd.jpg.....

Report generated.

Report generation completed.

"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp D:/Temp/fpgahdl_xilinx/cf_lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.4 - platgen Xilinx EDK 14.4 Build EDK_P.49d

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp

D:/Temp/fpgahdl_xilinx/cf_lib/ -msg __xps/ise/xmsgprops.lst system.mhs 



Parse D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/system.mhs ...



Read MPD definitions ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 300 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 304 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 308 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 312 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 7 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 319 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_3 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock

   'processing_system7_0_PS_CLK' is not specified. Clock DRCs will not be

   performed for IPs connected to that clock port, unless they are connected

   through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   axi_clkgen_0:clk. Clock DRCs will not be performed on this core and cores

   connected to it. 



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

INFO:EDK - INFO: DDR Base and High address in current configuration is

   0x00000000 and 0x1FFFFFFF respectively. 

INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable

   Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a

   master on processing_system7 AXI slave interfaces, please use the top half of

   the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For

   all other master, any subset of the DDR address can be used. See Xilinx

   Answer 47167 for more information. 

Address Map for Processor processing_system7_0

  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	axi_interconnect_1

  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1

  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1

  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1

  (0x77620000-0x7762ffff) axi_ssm2518_0	axi_interconnect_1

  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1



Checking platform address map ...



Checking platform configuration ...

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 9

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - 1 master(s) : 1

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - 1 master(s) : 1

slave(s) 



Checking port drivers...

WARNING:EDK:4181 - PORT: hdmi_int, CONNECTOR: hdmi_int - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 32 

WARNING:EDK:4181 - PORT: util_vector_logic_0_Op1_pin, CONNECTOR:

   net_util_vector_logic_0_Op1_pin - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 35 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_0_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_1_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 



Performing Clock DRCs...



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 353 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_2; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_3; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_3 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

ZynqConfig: Terminated for tcl mode



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_

   generator.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf

ZynqConfig: Terminated for tcl mode

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.


INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.


INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_3.




Modify defaults ...



Creating stub ...



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...



Managing cache ...

IPNAME:axi_vdma INSTANCE:axi_vdma_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 - Copying cache

implementation netlist

IPNAME:axi_interconnect INSTANCE:axi_interconnect_2 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 - Copying cache

implementation netlist

IPNAME:axi_hdmi_tx_16b INSTANCE:axi_hdmi_tx_16b_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 242 - Copying cache

implementation netlist

IPNAME:axi_spdif_tx INSTANCE:axi_spdif_tx_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 263 - Copying cache

implementation netlist

IPNAME:axi_iic INSTANCE:axi_iic_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 - Copying cache

implementation netlist

IPNAME:axi_clkgen INSTANCE:axi_clkgen_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 300 - Copying cache

implementation netlist

IPNAME:util_vector_logic INSTANCE:util_vector_logic_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 321 - Copying cache

implementation netlist

IPNAME:axi_i2s_adi INSTANCE:axi_i2s_adi_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 330 - Copying cache

implementation netlist

IPNAME:util_i2c_mixer INSTANCE:util_i2c_mixer_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 365 - Copying cache

implementation netlist

IPNAME:axi_iic INSTANCE:axi_iic_1 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 - Copying cache

implementation netlist



Elaborating instances ...

IPNAME:clock_generator INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 0.00 seconds



Constructing platform-level connectivity ...

Completion time: 1.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:processing_system7_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 60 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_interconnect_1 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 226 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_hdmi_tx_16b_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 242 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_spdif_tx_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

263 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_clkgen_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

300 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:clock_generator_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 311 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_i2s_adi_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

330 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:util_i2c_mixer_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 365 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_interconnect_3 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 390 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_vdma_1 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397

- Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_ssm2518_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

413 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Running NGCBUILD ...

IPNAME:system_axi_interconnect_1_wrapper INSTANCE:axi_interconnect_1 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_interconnect_1_wrapper.ngc

../system_axi_interconnect_1_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/axi_interconnect_1_wrapper

/system_axi_interconnect_1_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_interconnect_1_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_interconnect_1_wrapper.blc"...



NGCBUILD done.

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/clock_generator_0_wrapper/

system_clock_generator_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_interconnect_3_wrapper INSTANCE:axi_interconnect_3 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_interconnect_3_wrapper.ngc

../system_axi_interconnect_3_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/axi_interconnect_3_wrapper

/system_axi_interconnect_3_wrapper.ngc" ...

Loading design module

"../system_axi_interconnect_3_wrapper_fifo_generator_v9_1_1.ngc"...

Loading design module

"../system_axi_interconnect_3_wrapper_fifo_generator_v9_1_2.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_interconnect_3_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_interconnect_3_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_vdma_1_wrapper INSTANCE:axi_vdma_1 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_vdma_1_wrapper.ngc

../system_axi_vdma_1_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/axi_vdma_1_wrapper/system_

axi_vdma_1_wrapper.ngc" ...

Loading design module

"../system_axi_vdma_1_wrapper_fifo_generator_v9_1_2.ngc"...

Loading design module

"../system_axi_vdma_1_wrapper_fifo_generator_v9_1_1.ngc"...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_vdma_1_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_vdma_1_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_ssm2518_0_wrapper INSTANCE:axi_ssm2518_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 413 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_ssm2518_0_wrapper.ngc

../system_axi_ssm2518_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/axi_ssm2518_0_wrapper/syst

em_axi_ssm2518_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_ssm2518_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_ssm2518_0_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 592.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc

Release 14.4 - Xflow P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc 

 

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Using Flow File: D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/fpga.flw 

Using Option File(s): 

 D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc7z020clg484-1 -nt timestamp -bm system.bmm

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system.ngc" -uc system.ucf

system.ngd 

#----------------------------------------------#

Release 14.4 - ngdbuild P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>





Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc7z020clg484-1 -nt timestamp -bm system.bmm


D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system.ngc -uc system.ucf


system.ngd





Reading NGO file


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system.ngc" ...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_processing_system7_


0_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_util_vector_logic_0


_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_i2s_adi_0_wrapp


er.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_1_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_2_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_3_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_spdif_tx_0_wrap


per.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_clkgen_0_wrappe


r.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_clock_generator_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_vdma_0_wrapper.


ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_hdmi_tx_16b_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_vdma_1_wrapper.


ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_ssm2518_0_wrapp


er.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_iic_0_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_iic_1_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_util_i2c_mixer_0_wr


apper.ngc"...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_processing_system7_


0_wrapper.ncf" to module "processing_system7_0"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_1_


wrapper.ncf" to module "axi_interconnect_1"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_2_


wrapper.ncf" to module "axi_interconnect_2"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_3_


wrapper.ncf" to module "axi_interconnect_3"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_vdma_0_wrapper.


ncf" to module "axi_vdma_0"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_vdma_1_wrapper.


ncf" to module "axi_vdma_1"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_PORB_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_CLK_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_SRSTB_IBUF'.  All constraints associated with this


   symbol will be ignored.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GENER


   ATE_LEVEL_P_S_CDC.s_level_out_d1_cdc_t...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_

out_d1_cdc_to_GND_620_o_MUX_640_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GENER


   ATE_LEVEL_P_S_CDC.p_level_in_d1_cdc_fr...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF


   .GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_


   in_d1_cdc_from_GND_620_o_MUX_639_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_LEV


   EL_P_S_CDC.s_level_out_d1_cdc_to_GND_6...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_out_d1_

cdc_to_GND_620_o_MUX_640_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_LEV


   EL_P_S_CDC.p_level_in_d1_cdc_from_GND_...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_in_d1_c

dc_from_GND_620_o_MUX_639_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_P_C


   DC.s_level_in_d1_cdc_from_GND_631_o_MU...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_from_

GND_631_o_MUX_642_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_P_C


   DC.p_level_out_d1_cdc_to_GND_631_o_MUX...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G

ND_631_o_MUX_643_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_P_C


   DC.s_level_in_d1_cdc_from_GND_631_o_MU...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_from_

GND_631_o_MUX_642_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GENER


   ATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_

out_d1_cdc_to_GND_631_o_MUX_643_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_P_C


   DC.p_level_out_d1_cdc_to_GND_631_o_MUX...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G

ND_631_o_MUX_643_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GENER


   ATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_

in_d1_cdc_from_GND_631_o_MUX_642_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out


   _d1_cdc_to_GND_150_o_MUX_590_o11 TNM =...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_150_o_MUX_5

90_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_


   d1_cdc_from_GND_150_o_MUX_589_o11 TNM ...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_150_o_MUX_

589_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   p_out_d1_cdc_to_GND_150_o_MUX_590_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_150_o_

MUX_590_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   s_in_d1_cdc_from_GND_150_o_MUX_589_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_150_o

_MUX_589_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_134_o_MUX_584_o1...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_134_

o_MUX_584_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_134_o_MUX_585_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_134_o

_MUX_585_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.s_out_d1_cdc_to_GND_70_o_MUX_51_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o

_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.p_in_d1_cdc_from_GND_70_o_MUX_50_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_

o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_70_o_MUX_51_o11 T...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_

MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_70_o_MUX_50_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o

_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_34_o<7>11 TNM = FFS:TNM_axi_vdma_1...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_34_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_26_o<7>11 TNM = FFS:TNM_axi_vdma_1...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_26_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_10_o<7>11 TNM = FFS:TNM_axi_vdma_1...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_10_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.s_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_lev

el_out_d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.p_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_lev

el_in_d1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.s_level_out_d1_cdc_to_GN...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_out_

d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.p_level_in_d1_cdc_from_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_in_d

1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.s_level_in_d1_cdc_from_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_

d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out

_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_lev

el_in_d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.p_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_lev

el_out_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out


   _d1_cdc_to_GND_148_o_MUX_596_o11 TNM =...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_MUX_5

96_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_


   d1_cdc_from_GND_148_o_MUX_595_o11 TNM ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o_MUX_

595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   p_out_d1_cdc_to_GND_148_o_MUX_596_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_

MUX_596_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   s_in_d1_cdc_from_GND_148_o_MUX_595_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o

_MUX_595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_132_o_MUX_591_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_132_o

_MUX_591_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.s_out_d1_cdc_to_GND_70_o_MUX_51_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o

_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.p_in_d1_cdc_from_GND_70_o_MUX_50_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_

o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_70_o_MUX_51_o11 T...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_

MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_70_o_MUX_50_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o

_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_34_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_34_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_26_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_26_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_10_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_10_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_3/axi_interconnect_3\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_3_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_3/axi_interconnect_3/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_2/axi_interconnect_2\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_2_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_2/axi_interconnect_2/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_PORB_IBUF" LOC = B5>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_CLK_IBUF" LOC = F7>' could not be found and so


   the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_SRSTB_IBUF" LOC = C9>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_2_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_3_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_3_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_2_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   axi_clkgen_0/USER_LOGIC_I/i_clkgen/i_mmcm. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC


   TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s = PERIOD


   "axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s" TS_clk_fpga_2 *


   0.742424242 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   clock_generator_0/MMCM1_INST/MMCM_ADV_inst. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0" TS_clk_fpga_2


   * 0.061440678 HIGH 50>





Done...





Processing BMM file "system.bmm" ...





WARNING::53 - File 'system.bmm' is empty or has no BMM content.








Checking expanded design ...


WARNING:NgdBuild:486 - Attribute "CLOCK_HOLD" is not allowed on symbol


   "clock_generator_0/MMCM1_INST/MMCM_ADV_inst" of type "MMCME2_ADV".  This


   attribute will be ignored.


WARNING:NgdBuild:440 - FF primitive


   'axi_ssm2518_0/axi_ssm2518_0/up_dac_common_i/i_drp_rst_reg' has unconnected


   output pin


WARNING:NgdBuild:441 - FF primitive


   'axi_ssm2518_0/axi_ssm2518_0/up_dac_common_i/i_drp_rst_reg' has unconnected


   clock pin


WARNING:NgdBuild:440 - FF primitive


   'axi_ssm2518_0/axi_ssm2518_0/up_dac_common_i/i_mmcm_rst_reg' has unconnected


   output pin


WARNING:NgdBuild:441 - FF primitive


   'axi_ssm2518_0/axi_ssm2518_0/up_dac_common_i/i_mmcm_rst_reg' has unconnected


   clock pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_0/axi_iic_0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_1/axi_iic_1/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:452 - logical net 'N165' has no driver


WARNING:NgdBuild:452 - logical net 'N166' has no driver


WARNING:NgdBuild:452 - logical net 'N167' has no driver


WARNING:NgdBuild:452 - logical net 'N168' has no driver


WARNING:NgdBuild:452 - logical net 'N169' has no driver


WARNING:NgdBuild:452 - logical net 'N170' has no driver


WARNING:NgdBuild:452 - logical net 'N171' has no driver


WARNING:NgdBuild:452 - logical net 'N172' has no driver


WARNING:NgdBuild:452 - logical net 'N173' has no driver


WARNING:NgdBuild:452 - logical net 'N174' has no driver


WARNING:NgdBuild:452 - logical net 'N175' has no driver


WARNING:NgdBuild:452 - logical net 'N176' has no driver


WARNING:NgdBuild:452 - logical net 'N177' has no driver


WARNING:NgdBuild:452 - logical net 'N178' has no driver


WARNING:NgdBuild:452 - logical net 'N179' has no driver


WARNING:NgdBuild:452 - logical net 'N180' has no driver


WARNING:NgdBuild:452 - logical net 'N181' has no driver


WARNING:NgdBuild:452 - logical net 'N182' has no driver


WARNING:NgdBuild:452 - logical net 'N183' has no driver


WARNING:NgdBuild:452 - logical net 'N184' has no driver


WARNING:NgdBuild:452 - logical net 'N185' has no driver


WARNING:NgdBuild:452 - logical net 'N186' has no driver


WARNING:NgdBuild:452 - logical net 'N187' has no driver


WARNING:NgdBuild:452 - logical net 'N188' has no driver


WARNING:NgdBuild:452 - logical net 'N189' has no driver


WARNING:NgdBuild:452 - logical net 'N190' has no driver


WARNING:NgdBuild:452 - logical net 'N191' has no driver


WARNING:NgdBuild:452 - logical net 'N192' has no driver


WARNING:NgdBuild:452 - logical net 'N193' has no driver


WARNING:NgdBuild:452 - logical net 'N194' has no driver


WARNING:NgdBuild:452 - logical net 'N195' has no driver


WARNING:NgdBuild:452 - logical net 'N196' has no driver


WARNING:NgdBuild:452 - logical net 'N197' has no driver


WARNING:NgdBuild:452 - logical net 'N198' has no driver


WARNING:NgdBuild:452 - logical net 'N199' has no driver


WARNING:NgdBuild:452 - logical net 'N200' has no driver


WARNING:NgdBuild:452 - logical net 'N201' has no driver


WARNING:NgdBuild:452 - logical net 'N202' has no driver


WARNING:NgdBuild:452 - logical net 'N203' has no driver


WARNING:NgdBuild:452 - logical net 'N204' has no driver


WARNING:NgdBuild:452 - logical net 'N205' has no driver


WARNING:NgdBuild:452 - logical net 'N206' has no driver


WARNING:NgdBuild:452 - logical net 'N207' has no driver


WARNING:NgdBuild:452 - logical net 'N208' has no driver


WARNING:NgdBuild:452 - logical net 'N209' has no driver


WARNING:NgdBuild:452 - logical net 'N210' has no driver


WARNING:NgdBuild:452 - logical net 'N211' has no driver


WARNING:NgdBuild:452 - logical net 'N212' has no driver


WARNING:NgdBuild:452 - logical net 'N213' has no driver


WARNING:NgdBuild:452 - logical net 'N214' has no driver


WARNING:NgdBuild:452 - logical net 'N215' has no driver


WARNING:NgdBuild:452 - logical net 'N216' has no driver


WARNING:NgdBuild:452 - logical net 'N217' has no driver


WARNING:NgdBuild:452 - logical net 'N218' has no driver


WARNING:NgdBuild:452 - logical net 'N219' has no driver


WARNING:NgdBuild:452 - logical net 'N220' has no driver


WARNING:NgdBuild:452 - logical net 'N221' has no driver


WARNING:NgdBuild:452 - logical net 'N222' has no driver


WARNING:NgdBuild:452 - logical net 'N223' has no driver


WARNING:NgdBuild:452 - logical net 'N224' has no driver


WARNING:NgdBuild:452 - logical net 'N225' has no driver


WARNING:NgdBuild:452 - logical net 'N226' has no driver


WARNING:NgdBuild:452 - logical net 'N227' has no driver


WARNING:NgdBuild:452 - logical net 'N228' has no driver


WARNING:NgdBuild:452 - logical net 'N229' has no driver


WARNING:NgdBuild:452 - logical net 'N230' has no driver


WARNING:NgdBuild:452 - logical net 'N231' has no driver


WARNING:NgdBuild:452 - logical net 'N232' has no driver


WARNING:NgdBuild:452 - logical net 'N233' has no driver


WARNING:NgdBuild:452 - logical net 'N234' has no driver


WARNING:NgdBuild:452 - logical net 'N235' has no driver


WARNING:NgdBuild:452 - logical net 'N236' has no driver


WARNING:NgdBuild:452 - logical net 'N237' has no driver


WARNING:NgdBuild:452 - logical net 'N238' has no driver


WARNING:NgdBuild:452 - logical net 'N239' has no driver


WARNING:NgdBuild:452 - logical net 'N240' has no driver


WARNING:NgdBuild:452 - logical net 'N241' has no driver


WARNING:NgdBuild:452 - logical net 'N242' has no driver


WARNING:NgdBuild:452 - logical net 'N243' has no driver


WARNING:NgdBuild:452 - logical net 'N244' has no driver


WARNING:NgdBuild:452 - logical net 'N245' has no driver


WARNING:NgdBuild:452 - logical net 'N246' has no driver


WARNING:NgdBuild:452 - logical net 'N247' has no driver


WARNING:NgdBuild:452 - logical net 'N248' has no driver


WARNING:NgdBuild:452 - logical net 'N249' has no driver


WARNING:NgdBuild:452 - logical net 'N250' has no driver


WARNING:NgdBuild:452 - logical net 'N251' has no driver


WARNING:NgdBuild:452 - logical net 'N252' has no driver


WARNING:NgdBuild:452 - logical net 'N253' has no driver


WARNING:NgdBuild:452 - logical net 'N254' has no driver


WARNING:NgdBuild:452 - logical net 'N255' has no driver


WARNING:NgdBuild:452 - logical net 'N256' has no driver


WARNING:NgdBuild:452 - logical net 'N257' has no driver


WARNING:NgdBuild:452 - logical net 'N258' has no driver


WARNING:NgdBuild:452 - logical net 'N259' has no driver


WARNING:NgdBuild:452 - logical net 'N260' has no driver


WARNING:NgdBuild:452 - logical net 'N261' has no driver


WARNING:NgdBuild:452 - logical net 'N262' has no driver


WARNING:NgdBuild:452 - logical net 'N263' has no driver


WARNING:NgdBuild:452 - logical net 'N264' has no driver


WARNING:NgdBuild:452 - logical net 'N265' has no driver


WARNING:NgdBuild:452 - logical net 'N266' has no driver


WARNING:NgdBuild:452 - logical net 'N267' has no driver


WARNING:NgdBuild:452 - logical net 'N268' has no driver


WARNING:NgdBuild:452 - logical net 'N269' has no driver


WARNING:NgdBuild:452 - logical net 'N270' has no driver


WARNING:NgdBuild:452 - logical net 'N271' has no driver


WARNING:NgdBuild:452 - logical net 'N272' has no driver


WARNING:NgdBuild:452 - logical net 'N273' has no driver


WARNING:NgdBuild:452 - logical net 'N274' has no driver


WARNING:NgdBuild:452 - logical net 'N275' has no driver


WARNING:NgdBuild:452 - logical net 'N276' has no driver


WARNING:NgdBuild:452 - logical net 'N277' has no driver


WARNING:NgdBuild:452 - logical net 'N278' has no driver


WARNING:NgdBuild:452 - logical net 'N279' has no driver


WARNING:NgdBuild:452 - logical net 'N280' has no driver


WARNING:NgdBuild:452 - logical net 'N316' has no driver


WARNING:NgdBuild:452 - logical net 'N317' has no driver


WARNING:NgdBuild:452 - logical net 'N318' has no driver


WARNING:NgdBuild:452 - logical net 'N319' has no driver


WARNING:NgdBuild:452 - logical net 'N320' has no driver


WARNING:NgdBuild:452 - logical net 'N321' has no driver


WARNING:NgdBuild:452 - logical net 'N322' has no driver


WARNING:NgdBuild:452 - logical net 'N323' has no driver


WARNING:NgdBuild:452 - logical net 'N324' has no driver


WARNING:NgdBuild:452 - logical net 'N325' has no driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings: 255





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  42 sec


Total CPU time to NGDBUILD completion:   41 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.4 - Map P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<D:/Xilinx/14.4/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<D:/Xilinx/14.4/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "7z020clg484-1".


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<53>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<53>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<52>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<52>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<51>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<51>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<50>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<50>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<49>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<49>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<48>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<48>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<47>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<47>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<46>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<46>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<45>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<45>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<44>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<44>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<43>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<43>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<42>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<42>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<41>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<41>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<40>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<40>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<39>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<39>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<38>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<38>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<37>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<37>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<36>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<36>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<35>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<35>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<34>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<34>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<33>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<33>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<32>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<32>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<31>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<31>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<30>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<30>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<29>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<29>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<28>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<28>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<27>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<27>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<26>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<26>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<25>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<25>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<24>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<24>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<23>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<23>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<22>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<22>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<21>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<21>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<20>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<20>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<19>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<19>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<18>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<18>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<17>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<17>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<16>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<16>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<15>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<15>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<14>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<14>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<13>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<13>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<12>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<12>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<11>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<11>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<10>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<10>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<9>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<9>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<8>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<8>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<7>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<7>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<6>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<6>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<5>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<5>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<4>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<4>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<3>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<2>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<1>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<0>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_BankAddr<2>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_BankAddr<2>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_BankAddr<1>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_BankAddr<1>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_BankAddr<0>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_BankAddr<0>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<14>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<14>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<13>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<13>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<12>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<12>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<11>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<11>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<10>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<10>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<9>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<9>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<8>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<8>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<7>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<7>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<6>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<6>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<5>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<5>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<4>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<4>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<3>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<2>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<1>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<0>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<31>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<31>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<30>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<30>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<29>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<29>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<28>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<28>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<27>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<27>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<26>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<26>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<25>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<25>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<24>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<24>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<23>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<23>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<22>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<22>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<21>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<21>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<20>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<20>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<19>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<19>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<18>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<18>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<17>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<17>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<16>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<16>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<15>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<15>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<14>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<14>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<13>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<13>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<12>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<12>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<11>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<11>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<10>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<10>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<9>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<9>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<8>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<8>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<7>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<7>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<6>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<6>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<5>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<5>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<4>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<4>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<3>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<2>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<1>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<0>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DM<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DM<3>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DM<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DM<2>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DM<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DM<1>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DM<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DM<0>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS<3>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS<2>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS<1>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS<0>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS_n<3>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS_n<3>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS_n<2>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS_n<2>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS_n<1>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS_n<1>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS_n<0>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS_n<0>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Clk" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Clk" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Clk_n" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Clk_n" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_CKE" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_CKE" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_CS_n" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_CS_n" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_RAS_n" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_RAS_n" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_CAS_n" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_CAS_n" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_WEB_pin" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_WEB_pin" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_ODT" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_ODT" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DRSTB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DRSTB" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_VRN" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_VRN" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_VRP" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_VRP" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB" is not constrained


   (LOC) to a specific location.


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 42 secs 


Total CPU  time at the beginning of Placer: 39 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:8bc3bcf8) REAL time: 48 secs 





Phase 2.7  Design Feasibility Check


WARNING:Place:838 - An IO Bus with more than one IO standard is found.


   Components associated with this bus are as follows: 


   	 Comp: processing_system7_0_GPIO_pin<0>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<1>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<2>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<3>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<4>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<5>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<6>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<7>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<8>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<9>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<10>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<11>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<12>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<13>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<14>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<15>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<16>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<17>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<18>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<19>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<20>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<21>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<22>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<23>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<24>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<25>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<26>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<27>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<28>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<29>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<30>   IOSTANDARD = LVCMOS25








Phase 2.7  Design Feasibility Check (Checksum:8bc3bcf8) REAL time: 49 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:71611654) REAL time: 49 secs 





Phase 4.2  Initial Placement for Architecture Specific Features





Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:3d515bd4) REAL time: 58 secs 





Phase 5.30  Global Clock Region Assignment


Phase 5.30  Global Clock Region Assignment (Checksum:3d515bd4) REAL time: 58 secs 





Phase 6.3  Local Placement Optimization


Phase 6.3  Local Placement Optimization (Checksum:3d515bd4) REAL time: 59 secs 





Phase 7.5  Local Placement Optimization


Phase 7.5  Local Placement Optimization (Checksum:3d515bd4) REAL time: 59 secs 





Phase 8.8  Global Placement


...............................


...............................................................


................................................................................................................................................................


.......................................................................................................................................


Phase 8.8  Global Placement (Checksum:fa0dfcb2) REAL time: 2 mins 49 secs 





Phase 9.5  Local Placement Optimization


Phase 9.5  Local Placement Optimization (Checksum:fa0dfcb2) REAL time: 2 mins 50 secs 





Phase 10.18  Placement Optimization


Phase 10.18  Placement Optimization (Checksum:2fcbb0f9) REAL time: 3 mins 7 secs 





Phase 11.5  Local Placement Optimization


Phase 11.5  Local Placement Optimization (Checksum:2fcbb0f9) REAL time: 3 mins 7 secs 





Phase 12.34  Placement Validation


Phase 12.34  Placement Validation (Checksum:2fcbb0f9) REAL time: 3 mins 7 secs 





Total REAL time to Placer completion: 3 mins 8 secs 


Total CPU  time to Placer completion: 3 mins 3 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:  282


Slice Logic Utilization:


  Number of Slice Registers:                 7,236 out of 106,400    6


    Number used as Flip Flops:               7,221


    Number used as Latches:                      0


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:               15


  Number of Slice LUTs:                      7,029 out of  53,200   13


    Number used as logic:                    6,246 out of  53,200   11


      Number using O6 output only:           4,406


      Number using O5 output only:             152


      Number using O5 and O6:                1,688


      Number used as ROM:                        0


    Number used as Memory:                     557 out of  17,400    3


      Number used as Dual Port RAM:             84


        Number using O6 output only:             8


        Number using O5 output only:             7


        Number using O5 and O6:                 69


      Number used as Single Port RAM:            0


      Number used as Shift Register:           473


        Number using O6 output only:           465


        Number using O5 output only:             0


        Number using O5 and O6:                  8


    Number used exclusively as route-thrus:    226


      Number with same-slice register load:     73


      Number with same-slice carry load:       149


      Number with other load:                    4





Slice Logic Distribution:


  Number of occupied Slices:                 3,604 out of  13,300   27


  Number of LUT Flip Flop pairs used:        9,794


    Number with an unused Flip Flop:         3,152 out of   9,794   32


    Number with an unused LUT:               2,765 out of   9,794   28


    Number of fully used LUT-FF pairs:       3,877 out of   9,794   39


    Number of unique control sets:             415


    Number of slice register sites lost


      to control set restrictions:           1,521 out of 106,400    1





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.


  OVERMAPPING of BRAM resources should be ignored if the design is


  over-mapped for a non-BRAM resource or if placement fails.





IO Utilization:


  Number of bonded IOBs:                        78 out of     200   39


    Number of LOCed IOBs:                       78 out of      78  100


  Number of bonded IOPAD:                      130 out of     130  100


    IOB Flip Flops:                             25





Specific Feature Utilization:


  Number of RAMB36E1/FIFO36E1s:                  3 out of     140    2


    Number using RAMB36E1 only:                  3


    Number using FIFO36E1 only:                  0


  Number of RAMB18E1/FIFO18E1s:                  1 out of     280    1


    Number using RAMB18E1 only:                  1


    Number using FIFO18E1 only:                  0


  Number of BUFG/BUFGCTRLs:                      6 out of      32   18


    Number used as BUFGs:                        6


    Number used as BUFGCTRLs:                    0


  Number of IDELAYE2/IDELAYE2_FINEDELAYs:        0 out of     200    0


  Number of ILOGICE2/ILOGICE3/ISERDESE2s:        1 out of     200    1


    Number used as ILOGICE2s:                    1


  Number used as  ILOGICE3s:                     0


    Number used as ISERDESE2s:                   0


  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0


  Number of OLOGICE2/OLOGICE3/OSERDESE2s:       55 out of     200   27


    Number used as OLOGICE2s:                   55


    Number used as OLOGICE3s:                    0


    Number used as OSERDESE2s:                   0


  Number of PHASER_IN/PHASER_IN_PHYs:            0 out of      16    0


  Number of PHASER_OUT/PHASER_OUT_PHYs:          0 out of      16    0


  Number of BSCANs:                              0 out of       4    0


  Number of BUFHCEs:                             0 out of      72    0


  Number of BUFRs:                               0 out of      16    0


  Number of CAPTUREs:                            0 out of       1    0


  Number of DNA_PORTs:                           0 out of       1    0


  Number of DSP48E1s:                            0 out of     220    0


  Number of EFUSE_USRs:                          0 out of       1    0


  Number of FRAME_ECCs:                          0 out of       1    0


  Number of ICAPs:                               0 out of       2    0


  Number of IDELAYCTRLs:                         0 out of       4    0


  Number of IN_FIFOs:                            0 out of      16    0


  Number of MMCME2_ADVs:                         2 out of       4   50


  Number of OUT_FIFOs:                           0 out of      16    0


  Number of PHASER_REFs:                         0 out of       4    0


  Number of PHY_CONTROLs:                        0 out of       4    0


  Number of PLLE2_ADVs:                          0 out of       4    0


  Number of PS7s:                                1 out of       1  100


  Number of STARTUPs:                            0 out of       1    0


  Number of XADCs:                               0 out of       1    0





Average Fanout of Non-Clock Nets:                3.47





Peak Memory Usage:  1019 MB


Total REAL time to MAP completion:  3 mins 17 secs 


Total CPU time to MAP completion:   3 mins 11 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - par P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/data/parBmgr.acd> with local file

<D:/Xilinx/14.4/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)





Device speed data version:  "ADVANCED 1.04 2012-12-04".







Device Utilization Summary:



   Number of BUFGs                           6 out of 32     18

   Number of ILOGICE2s                       1 out of 200     1

   Number of External IOB33s                78 out of 200    39

      Number of LOCed IOB33s                78 out of 78    100



   Number of External IOPADs               130 out of 130   100

      Number of LOCed IOPADs                 0 out of 130     0



   Number of MMCME2_ADVs                     2 out of 4      50

   Number of OLOGICE2s                      55 out of 200    27

   Number of PS7s                            1 out of 1     100

   Number of RAMB18E1s                       1 out of 280     1

   Number of RAMB36E1s                       3 out of 140     2

   Number of Slices                       3604 out of 13300  27

   Number of Slice Registers              7236 out of 106400  6

      Number used as Flip Flops           7236

      Number used as Latches                 0

      Number used as LatchThrus              0



   Number of Slice LUTS                   7029 out of 53200  13

   Number of Slice LUT-Flip Flop pairs    9523 out of 53200  17





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 19 secs 

Finished initial Timing Analysis.  REAL time: 19 secs 



WARNING:Par:288 - The signal hdmi_int_IBUF has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3> has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM

   _RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mra

   m_RAM_RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_3/axi_interconnect_3/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mra

   m_RAM_RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_3/axi_interconnect_3/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM

   _RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route this

   signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

Starting Router





Phase  1  : 45685 unrouted;      REAL time: 22 secs 



Phase  2  : 36701 unrouted;      REAL time: 24 secs 



Phase  3  : 11924 unrouted;      REAL time: 35 secs 



Phase  4  : 11936 unrouted; (Setup:0, Hold:65363, Component Switching Limit:0)     REAL time: 41 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:57431, Component Switching Limit:0)     REAL time: 53 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:57431, Component Switching Limit:0)     REAL time: 53 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:57431, Component Switching Limit:0)     REAL time: 53 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:57431, Component Switching Limit:0)     REAL time: 53 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 56 secs 

Total REAL time to Router completion: 57 secs 

Total CPU time to Router completion: 57 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK0 |BUFGCTRL_X0Y31| No   |  938 |  0.336     |  1.961      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK1 |BUFGCTRL_X0Y29| No   | 1292 |  0.437     |  2.058      |

+---------------------+--------------+------+------+------------+-------------+

|axi_hdmi_tx_16b_0_hd |              |      |      |            |             |

|          mi_ref_clk | BUFGCTRL_X0Y1| No   |  365 |  0.250     |  1.902      |

+---------------------+--------------+------+------+------------+-------------+

|axi_i2s_adi_0_MCLK_p |              |      |      |            |             |

|             in_OBUF |BUFGCTRL_X0Y28| No   |   16 |  0.252     |  1.890      |

+---------------------+--------------+------+------+------------+-------------+

|axi_clkgen_0/axi_clk |              |      |      |            |             |

|gen_0/USER_LOGIC_I/i |              |      |      |            |             |

|_clkgen/buf_fb_clk_s |              |      |      |            |             |

|                     | BUFGCTRL_X0Y0| No   |    1 |  0.000     |  1.759      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK2 |BUFGCTRL_X0Y30| No   |    2 |  0.218     |  1.980      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0/cl |              |      |      |            |             |

|ock_generator_0/SIG_ |              |      |      |            |             |

|      MMCM1_CLKFBOUT |         Local|      |    1 |  0.000     |  0.014      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_1 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.084ns|     6.916ns|       0|           0

  1" 142.857 MHz HIGH 50| HOLD        |     0.003ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.190ns|     9.810ns|       0|           0

  0" 100 MHz HIGH 50| HOLD        |     0.007ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I | SETUP       |     0.316ns|     6.418ns|       0|           0

  _i_clkgen_mmcm_clk_s = PERIOD TIMEGRP     | HOLD        |     0.085ns|            |       0|           0

       "axi_clkgen_0_axi_clkgen_0_USER_LOGI |             |            |            |        |            

  C_I_i_clkgen_mmcm_clk_s"         TS_clk_f |             |            |            |        |            

  pga_2 * 0.742424242 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_2 = PERIOD TIMEGRP "clk_fpga_ | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0

  2" 200 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |    77.821ns|     3.558ns|       0|           0

  G_MMCM1_CLKOUT0 = PERIOD TIMEGRP          | HOLD        |     0.065ns|            |       0|           0

  "clock_generator_0_clock_generator_0_SIG_ |             |            |            |        |            

  MMCM1_CLKOUT0" TS_clk_fpga_2         * 0. |             |            |            |        |            

  061440678 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_1_cdc_tig_v_path" TIG   | SETUP       |         N/A|     7.649ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_1_cdc_from_2_cdc_to_pat | SETUP       |         N/A|     3.144ns|     N/A|           0

  h" TIG                                    |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_tig_v_path" TIG   | SETUP       |         N/A|     6.346ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_from_2_cdc_to_pat | SETUP       |         N/A|     2.054ns|     N/A|           0

  h" TIG                                    |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_3_reset_resync_ | SETUP       |         N/A|     1.123ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_2_reset_resync_ | SETUP       |         N/A|     1.055ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_1_reset_resync_ | SETUP       |         N/A|     1.305ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_clk_fpga_2

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_clk_fpga_2                  |      5.000ns|      2.800ns|      4.765ns|            0|            0|            0|        43851|

| TS_axi_clkgen_0_axi_clkgen_0_U|      6.735ns|      6.418ns|          N/A|            0|            0|        43794|            0|

| SER_LOGIC_I_i_clkgen_mmcm_clk_|             |             |             |             |             |             |             |

| s                             |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     81.379ns|      3.558ns|          N/A|            0|            0|           57|            0|

| erator_0_SIG_MMCM1_CLKOUT0    |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 21 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 1 mins 2 secs 

Total CPU time to PAR completion: 1 mins 



Peak Memory Usage:  901 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 23

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>


Loading device for application Rf_Device from file '7z020.nph' in environment


D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.4 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc7z020,-1 (ADVANCED 1.04 2012-12-04)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 478320 paths, 0 nets, and 39052 connections





Design statistics:


   Minimum period:   9.810ns (Maximum frequency: 101.937MHz)








Analysis completed Tue Sep 24 15:52:36 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 21 secs 






xflow done!

touch __xps/system_routed

xilperl D:/Xilinx/14.4/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.4 - Bitgen P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1

Opened constraints file system.pcf.



Tue Sep 24 15:52:51 2013



Running DRC.

WARNING:PhysDesignRules:367 - The signal <hdmi_int_IBUF> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3>> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/

   grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfif

   o.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_3/axi_interconnect_3/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfif

   o.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_3/axi_interconnect_3/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/

   grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

INFO:PhysDesignRules:2288 - The read port and write port clocks of BRAM

   instance,

   axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_S

   OF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.V6.I_LINEBUFFER_FIFO/fg91_inst/U0/xst_fifo_g

   enerator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/g

   nativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WI

   DE_PRIM36.ram, are using the same clock signal (synchronous clocking) with

   WRITE_FIRST mode specified. This configuration may encounter address

   collisions if the same address appears on both ports. It is suggested for

   this configuration to use READ_FIRST mode to avoid any conditions for address

   collision. See the FPGA Memory Resources User Guide for additional

   information.

DRC detected 0 errors and 21 warnings.  Please see the previously displayed

individual error or warning messages for more details.

Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 60 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 203 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 226 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 234 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 284 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 311 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 378 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 390 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 397 
The project's MHS file has changed on disk.
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 63 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 206 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 229 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 237 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 287 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 314 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 381 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 393 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 400 
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 63 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 206 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 229 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 237 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 287 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 314 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 381 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 393 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 400 
WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 63 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 206 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 229 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 237 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 287 
WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 314 
WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 381 
WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 393 
WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production version not verified on hardware for architecture 'zynq' - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 400 

********************************************************************************
At Local date and time: Tue Sep 24 15:58:26 2013
 make -f system.make exporttosdk started...
IF NOT EXIST "SDK\SDK_Export\hw" @mkdir "SDK\SDK_Export\hw"

pscgen -mhs system.mhs -expdir SDK\SDK_Export\hw

ZynqConfig: Terminated for pscgen mode

psf2Edward -inp system.xmp -flat_zynq -dont_run_checkhwsys -dont_add_loginfo -make_inst_lower -edwver 1.2 -xml SDK\SDK_Export\hw/system.xml 

Release 14.4 - psf2Edward EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 64 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 207 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 238 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 288 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 382 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 394 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 401 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 64 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 207 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 238 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 288 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 382 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 394 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 401 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 64 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 207 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 238 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 288 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 382 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 394 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 401 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 64 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 207 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 238 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 288 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 382 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 394 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 401 



Overriding IP level properties ...



Computing clock values...



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

Address Map for Processor ps7_cortexa9_0

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77620000-0x7762ffff)

axi_ssm2518_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0

Address Map for Processor ps7_cortexa9_1

  (0000000000-0x0002ffff) ps7_ram_0	ps7_axi_interconnect_0

  (0x00100000-0x1fffffff) ps7_ddr_0	ps7_axi_interconnect_0

  (0x41600000-0x4160ffff) axi_iic_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	ps7_axi_interconnect_0->axi_interconnect_1

  (0x70e00000-0x70e0ffff)

axi_hdmi_tx_16b_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x75c00000-0x75c0ffff)

axi_spdif_tx_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77600000-0x7760ffff)

axi_i2s_adi_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x77620000-0x7762ffff)

axi_ssm2518_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0x79000000-0x7900ffff)

axi_clkgen_0	ps7_axi_interconnect_0->axi_interconnect_1

  (0xe0001000-0xe0001fff) ps7_uart_1	ps7_axi_interconnect_0

  (0xe0002000-0xe0002fff) ps7_usb_0	ps7_axi_interconnect_0

  (0xe0006000-0xe0006fff) ps7_spi_0	ps7_axi_interconnect_0

  (0xe0007000-0xe0007fff) ps7_spi_1	ps7_axi_interconnect_0

  (0xe000a000-0xe000afff) ps7_gpio_0	ps7_axi_interconnect_0

  (0xe000b000-0xe000bfff) ps7_ethernet_0	ps7_axi_interconnect_0

  (0xe000d000-0xe000dfff) ps7_qspi_0	ps7_axi_interconnect_0

  (0xe0100000-0xe0100fff) ps7_sd_0	ps7_axi_interconnect_0

  (0xe0200000-0xe0200fff) ps7_iop_bus_config_0	ps7_axi_interconnect_0

  (0xf8000000-0xf8000fff) ps7_slcr_0	ps7_axi_interconnect_0

  (0xf8003000-0xf8003fff) ps7_dma_s	ps7_axi_interconnect_0

  (0xf8004000-0xf8004fff) ps7_dma_ns	ps7_axi_interconnect_0

  (0xf8006000-0xf8006fff) ps7_ddrc_0	ps7_axi_interconnect_0

  (0xf8007000-0xf8007fff) ps7_dev_cfg_0	ps7_axi_interconnect_0

  (0xf8008000-0xf8008fff) ps7_afi_0	ps7_axi_interconnect_0

  (0xf8009000-0xf8009fff) ps7_afi_1	ps7_axi_interconnect_0

  (0xf800a000-0xf800afff) ps7_afi_2	ps7_axi_interconnect_0

  (0xf800b000-0xf800bfff) ps7_afi_3	ps7_axi_interconnect_0

  (0xf8f00100-0xf8f001ff) ps7_scugic_0	ps7_axi_interconnect_0

  (0xf8f00600-0xf8f0061f) ps7_scutimer_0	ps7_axi_interconnect_0

  (0xf8f00620-0xf8f006ff) ps7_scuwdt_0	ps7_axi_interconnect_0

  (0xfc000000-0xfcffffff) ps7_qspi_linear_0	ps7_axi_interconnect_0

  (0xffff0000-0xfffffdff) ps7_ram_1	ps7_axi_interconnect_0



Checking platform address map ...

WARNING:EDK:2486 - The bitwidth 52 of new value 0xc00000000fe81 is greater than

   32

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_BASE_ID -

   Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   19 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_IS_ACLK_ASYNC - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   20 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_ACLK_RATIO

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   21 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_ARB_PRIORITY - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   22 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AW_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   23 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_AR_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   24 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_W_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   25 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_R_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   26 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: C_INTERCONNECT_M_AXI_B_REGISTER

   - Failure in evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   27 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_FIFO_DEPTH - Failure in evaluting ISVALID

   expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   28 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_FIFO_DEPTH - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   29 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_WRITE_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   30 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY:

   C_INTERCONNECT_M_AXI_READ_ISSUING - Failure in evaluting ISVALID expresion

   "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\EDK\data\coremodel\axi\data\tools_axi_v1_01_a.txt line

   31 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ACLK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 119 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARESETN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 120 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 121 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 122 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 123 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 124 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 125 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 126 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 127 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 128 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 129 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_AWREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 130 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 131 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WSTRB - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 132 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 133 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 134 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_WREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 135 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 136 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 137 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 138 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_BREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 139 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 140 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARADDR - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 141 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLEN - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 142 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARSIZE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 143 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARBURST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 144 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARCACHE - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 145 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARPROT - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 146 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARLOCK - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 147 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 148 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_ARREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 149 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RID - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 150 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RDATA - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 151 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RRESP - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 152 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RLAST - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 153 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RVALID - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 154 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI_RREADY - Failure in

   evaluting ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 155 

WARNING:EDK:4131 - IPNAME: ps7_usb_0, PROPERTY: M_AXI - Failure in evaluting

   ISVALID expresion "(C_INCLUDE_DMA == 1)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_usb_v1_00_

   a\data\ps7_usb_v2_1_0.mpd line 73 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_I - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 102 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_O - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 103 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK_T - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 104 

WARNING:EDK:4131 - IPNAME: ps7_qspi_0, PROPERTY: SCK - Failure in evaluting

   ISVALID expresion "(C_USE_STARTUP==0)" -

   D:\Xilinx\14.4\ISE_DS\ISE\data\zynqconfig\ps7_internals\pcores\ps7_qspi_v1_00

   _a\data\ps7_qspi_v2_1_0.mpd line 122 

Conversion to XML complete.

xdsgen -inp system.xmp -report SDK\SDK_Export\hw/system.html  -make_docs_local

Release 14.4 - xdsgen EDK_P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Generated Block Diagram.

Rasterizing processing_system7_0.jpg.....

Rasterizing axi_vdma_0.jpg.....

Rasterizing axi_interconnect_1.jpg.....

Rasterizing axi_interconnect_2.jpg.....

Rasterizing axi_hdmi_tx_16b_0.jpg.....

Rasterizing axi_spdif_tx_0.jpg.....

Rasterizing axi_iic_0.jpg.....

Rasterizing axi_clkgen_0.jpg.....

Rasterizing clock_generator_0.jpg.....

Rasterizing util_vector_logic_0.jpg.....

Rasterizing axi_i2s_adi_0.jpg.....

Rasterizing util_i2c_mixer_0.jpg.....

Rasterizing axi_iic_1.jpg.....

Rasterizing axi_interconnect_3.jpg.....

Rasterizing axi_vdma_1.jpg.....

Rasterizing axi_ssm2518_0.jpg.....

Rasterizing system_blkd.jpg.....

Report generated.

Report generation completed.

"****************************************************"

"Creating system netlist for hardware specification.."

"****************************************************"

platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp D:/Temp/fpgahdl_xilinx/cf_lib/   -msg __xps/ise/xmsgprops.lst system.mhs



Release 14.4 - platgen Xilinx EDK 14.4 Build EDK_P.49d

 (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





Command Line: platgen -p xc7z020clg484-1 -lang vhdl -intstyle default -lp

D:/Temp/fpgahdl_xilinx/cf_lib/ -msg __xps/ise/xmsgprops.lst system.mhs 



Parse D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/system.mhs ...



Read MPD definitions ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 64 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 207 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 238 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 288 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 382 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 394 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 401 

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 64 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 207 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 238 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 288 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 382 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 394 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 401 



Overriding IP level properties ...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP0_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 300 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP1_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 304 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP2_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 308 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_S_AXI_HP3_HIGHADDR value to 0x1FFFFFFF -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 312 

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_NUM_F2P_INTR_INPUTS value to 8 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 319 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 

INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_3 - tcl is

   overriding PARAMETER C_BASEFAMILY value to zynq -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 81 



Computing clock values...

INFO:EDK:1432 - Frequency for Top-Level Input Clock

   'processing_system7_0_PS_CLK' is not specified. Clock DRCs will not be

   performed for IPs connected to that clock port, unless they are connected

   through the clock generator IP. 



INFO:EDK:740 - Cannot determine the input clock associated with port :

   axi_clkgen_0:clk. Clock DRCs will not be performed on this core and cores

   connected to it. 



Performing IP level DRCs on properties...



Running DRC Tcl procedures for OPTION IPLEVEL_DRC_PROC...

INFO:EDK - INFO: DDR Base and High address in current configuration is

   0x00000000 and 0x1FFFFFFF respectively. 

INFO:EDK - INFO: You can modify the DDR address range accessed by Programmable

   Logic through the processing_system7 AXI slave interfaces. If MicroBlaze is a

   master on processing_system7 AXI slave interfaces, please use the top half of

   the address range (Base Address = 0x10000000; High Address = 0x1FFFFFFF). For

   all other master, any subset of the DDR address can be used. See Xilinx

   Answer 47167 for more information. 

Address Map for Processor processing_system7_0

  (0x41600000-0x4160ffff) axi_iic_0	axi_interconnect_1

  (0x41640000-0x4164ffff) axi_iic_1	axi_interconnect_1

  (0x43000000-0x4300ffff) axi_vdma_0	axi_interconnect_1

  (0x43040000-0x4304ffff) axi_vdma_1	axi_interconnect_1

  (0x70e00000-0x70e0ffff) axi_hdmi_tx_16b_0	axi_interconnect_1

  (0x75c00000-0x75c0ffff) axi_spdif_tx_0	axi_interconnect_1

  (0x77600000-0x7760ffff) axi_i2s_adi_0	axi_interconnect_1

  (0x77620000-0x7762ffff) axi_ssm2518_0	axi_interconnect_1

  (0x79000000-0x7900ffff) axi_clkgen_0	axi_interconnect_1



Checking platform address map ...



Checking platform configuration ...

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 - 1 master(s) : 9

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 - 1 master(s) : 1

slave(s) 

IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 - 1 master(s) : 1

slave(s) 



Checking port drivers...

WARNING:EDK:4181 - PORT: hdmi_int, CONNECTOR: hdmi_int - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 32 

WARNING:EDK:4181 - PORT: util_vector_logic_0_Op1_pin, CONNECTOR:

   net_util_vector_logic_0_Op1_pin - floating connection -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 35 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_0_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 

WARNING:EDK:4181 - PORT: m_axis_mm2s_tuser, CONNECTOR:

   axi_vdma_1_M_AXIS_MM2S_TUSER - floating connection -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_vdma_v5_04_a\dat

   a\axi_vdma_v2_1_0.mpd line 212 



Performing Clock DRCs...



Performing Reset DRCs...



Overriding system level properties...

INFO:EDK:4130 - IPNAME: processing_system7, INSTANCE:processing_system7_0 - tcl

   is overriding PARAMETER C_FCLK_CLK3_BUF value to FALSE -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v

   4_02_a\data\processing_system7_v2_1_0.mpd line 353 




INFO: Setting C_RANGE_CHECK = ON for axi_interconnect axi_interconnect_1.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_1 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 1 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_2; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_2 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 




INFO: Setting C_RANGE_CHECK = OFF for axi_interconnect axi_interconnect_3; no

DECERR checking will be performed.


INFO:EDK:4130 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_3 - tcl is

   overriding PARAMETER C_RANGE_CHECK value to 0 -

   D:\Xilinx\14.4\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_

   06_a\data\axi_interconnect_v2_1_0.mpd line 149 



Running system level update procedures...



Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode



Running system level DRCs...



Performing System level DRCs on properties...



Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...

ZynqConfig: Terminated for tcl mode



Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...

ZynqConfig: Terminated for tcl mode

INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.


INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.


INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_3.




Modify defaults ...



Creating stub ...

WARNING:EDK:4092 - IPNAME: processing_system7, INSTANCE: processing_system7_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 64 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_0 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 207 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_1 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 230 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_2 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 238 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_0 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 288 

WARNING:EDK:4092 - IPNAME: clock_generator, INSTANCE: clock_generator_0 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 

WARNING:EDK:4092 - IPNAME: axi_iic, INSTANCE: axi_iic_1 - Pre-Production version

   not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 382 

WARNING:EDK:4092 - IPNAME: axi_interconnect, INSTANCE: axi_interconnect_3 -

   Pre-Production version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 394 

WARNING:EDK:4092 - IPNAME: axi_vdma, INSTANCE: axi_vdma_1 - Pre-Production

   version not verified on hardware for architecture 'zynq' -

   D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 401 

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clock_generator;v=v4_03_a;d=clock_

   generator.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_iic;v=v1_02_a;d=axi_iic_ds756.

   pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v1_06_a;d=ds768

   _axi_interconnect.pdf

WARNING:EDK:878 - Could not find IP doc

   http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_vdma;v=v5_04_a;d=pg020_axi_vdm

   a.pdf



Processing licensed instances ...

Completion time: 0.00 seconds



Creating hardware output directories ...



Managing hardware (BBD-specified) netlist files ...



Managing cache ...

IPNAME:axi_vdma INSTANCE:axi_vdma_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 207 - Copying cache

implementation netlist

IPNAME:axi_interconnect INSTANCE:axi_interconnect_1 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 230 - Copying cache

implementation netlist

IPNAME:axi_interconnect INSTANCE:axi_interconnect_2 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 238 - Copying cache

implementation netlist

IPNAME:axi_hdmi_tx_16b INSTANCE:axi_hdmi_tx_16b_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 246 - Copying cache

implementation netlist

IPNAME:axi_spdif_tx INSTANCE:axi_spdif_tx_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 267 - Copying cache

implementation netlist

IPNAME:axi_iic INSTANCE:axi_iic_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 288 - Copying cache

implementation netlist

IPNAME:axi_clkgen INSTANCE:axi_clkgen_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 304 - Copying cache

implementation netlist

IPNAME:util_vector_logic INSTANCE:util_vector_logic_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 325 - Copying cache

implementation netlist

IPNAME:axi_i2s_adi INSTANCE:axi_i2s_adi_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 334 - Copying cache

implementation netlist

IPNAME:util_i2c_mixer INSTANCE:util_i2c_mixer_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 369 - Copying cache

implementation netlist

IPNAME:axi_iic INSTANCE:axi_iic_1 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 382 - Copying cache

implementation netlist

IPNAME:axi_interconnect INSTANCE:axi_interconnect_3 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 394 - Copying cache

implementation netlist

IPNAME:axi_vdma INSTANCE:axi_vdma_1 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 401 - Copying cache

implementation netlist

IPNAME:axi_ssm2518 INSTANCE:axi_ssm2518_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 419 - Copying cache

implementation netlist



Elaborating instances ...

IPNAME:clock_generator INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 - elaborating IP

ClkGen elaborate status: PASSED


----------------------------------------


----------------------------------------




Writing HDL for elaborated instances ...



Inserting wrapper level ...

Completion time: 1.00 seconds



Constructing platform-level connectivity ...

Completion time: 0.00 seconds



Writing (top-level) BMM ...



Writing (top-level and wrappers) HDL ...



Generating synthesis project file ...



Running XST synthesis ...



INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option

   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST

   synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. 

INSTANCE:processing_system7_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 64 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_hdmi_tx_16b_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 246 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_spdif_tx_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

267 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_clkgen_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

304 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:clock_generator_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 315 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_i2s_adi_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

334 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:util_i2c_mixer_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs

line 369 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

INSTANCE:axi_ssm2518_0 - D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line

419 - Running XST synthesis

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Running NGCBUILD ...

IPNAME:system_clock_generator_0_wrapper INSTANCE:clock_generator_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 315 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_clock_generator_0_wrapper.ngc

../system_clock_generator_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/clock_generator_0_wrapper/

system_clock_generator_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_clock_generator_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_clock_generator_0_wrapper.blc"...



NGCBUILD done.

IPNAME:system_axi_ssm2518_0_wrapper INSTANCE:axi_ssm2518_0 -

D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\system.mhs line 419 - Running NGCBUILD

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngcbuild.exe -p

xc7z020clg484-1 -intstyle silent -i -sd .. system_axi_ssm2518_0_wrapper.ngc

../system_axi_ssm2518_0_wrapper



Reading NGO file

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/axi_ssm2518_0_wrapper/syst

em_axi_ssm2518_0_wrapper.ngc" ...



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



NGCBUILD Design Results Summary:

  Number of errors:     0

  Number of warnings:   0



Writing NGC file "../system_axi_ssm2518_0_wrapper.ngc" ...

Total REAL time to NGCBUILD completion:  4 sec

Total CPU time to NGCBUILD completion:   4 sec



Writing NGCBUILD log file "../system_axi_ssm2518_0_wrapper.blc"...



NGCBUILD done.

INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.

   If any constraint needs to be overridden, this should be done by modifying

   the data/system.ucf file.



Rebuilding cache ...



Total run time: 121.00 seconds

"Running synthesis..."

cd synthesis & synthesis.cmd

"xst -ifn "system_xst.scr" -intstyle silent"

"Running XST synthesis ..."

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

"XST completed"

"*********************************************"

"Running Xilinx Implementation tools.."

"*********************************************"

xflow -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc

Release 14.4 - Xflow P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

xflow.exe -wd implementation -p xc7z020clg484-1 -implement xflow.opt system.ngc 

 

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>



Using Flow File: D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/fpga.flw 

Using Option File(s): 

 D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/xflow.opt 



Creating Script File ... 



#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc7z020clg484-1 -nt timestamp -bm system.bmm

"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system.ngc" -uc system.ucf

system.ngd 

#----------------------------------------------#

Release 14.4 - ngdbuild P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>





Command Line: D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -p


xc7z020clg484-1 -nt timestamp -bm system.bmm


D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system.ngc -uc system.ucf


system.ngd





Reading NGO file


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system.ngc" ...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_processing_system7_


0_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_util_vector_logic_0


_wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_i2s_adi_0_wrapp


er.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_1_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_2_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_3_


wrapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_spdif_tx_0_wrap


per.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_clkgen_0_wrappe


r.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_clock_generator_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_vdma_0_wrapper.


ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_hdmi_tx_16b_0_w


rapper.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_vdma_1_wrapper.


ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_ssm2518_0_wrapp


er.ngc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_iic_0_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_iic_1_wrapper.n


gc"...


Loading design module


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_util_i2c_mixer_0_wr


apper.ngc"...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_processing_system7_


0_wrapper.ncf" to module "processing_system7_0"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_1_


wrapper.ncf" to module "axi_interconnect_1"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_2_


wrapper.ncf" to module "axi_interconnect_2"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_interconnect_3_


wrapper.ncf" to module "axi_interconnect_3"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_vdma_0_wrapper.


ncf" to module "axi_vdma_0"...


Checking Constraint Associations...


Applying constraints in


"D:/Temp/fpgahdl_xilinx/cf_ssm2518_zed/implementation/system_axi_vdma_1_wrapper.


ncf" to module "axi_vdma_1"...


Checking Constraint Associations...


Gathering constraint information from source properties...


Done.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_PORB_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_CLK_IBUF'.  All constraints associated with this


   symbol will be ignored.


INFO:NgdBuild:649 - Removing redundant 'IBUF' symbol


   'processing_system7_0_PS_SRSTB_IBUF'.  All constraints associated with this


   symbol will be ignored.





Annotating constraints to design from ucf file "system.ucf" ...


Resolving constraint associations...


Checking Constraint Associations...


WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GENER


   ATE_LEVEL_P_S_CDC.s_level_out_d1_cdc_t...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_

out_d1_cdc_to_GND_620_o_MUX_640_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GENER


   ATE_LEVEL_P_S_CDC.p_level_in_d1_cdc_fr...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_

in_d1_cdc_from_GND_620_o_MUX_639_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_LEV


   EL_P_S_CDC.s_level_out_d1_cdc_to_GND_6...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_out_d1_

cdc_to_GND_620_o_MUX_640_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_LEV


   EL_P_S_CDC.p_level_in_d1_cdc_from_GND_...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_in_d1_c

dc_from_GND_620_o_MUX_639_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_P_C


   DC.s_level_in_d1_cdc_from_GND_631_o_MU...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_from_

GND_631_o_MUX_642_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_P_C


   DC.p_level_out_d1_cdc_to_GND_631_o_MUX...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G

ND_631_o_MUX_643_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_P_C


   DC.s_level_in_d1_cdc_from_GND_631_o_MU...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_from_

GND_631_o_MUX_642_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GENER


   ATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_

out_d1_cdc_to_GND_631_o_MUX_643_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_P_C


   DC.p_level_out_d1_cdc_to_GND_631_o_MUX...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G

ND_631_o_MUX_643_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_NO_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GENER


   ATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF

.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_

in_d1_cdc_from_GND_631_o_MUX_642_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out


   _d1_cdc_to_GND_150_o_MUX_590_o11 TNM =...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_150_o_MUX_5

90_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_


   d1_cdc_from_GND_150_o_MUX_589_o11 TNM ...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_150_o_MUX_

589_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   p_out_d1_cdc_to_GND_150_o_MUX_590_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_150_o_

MUX_590_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   s_in_d1_cdc_from_GND_150_o_MUX_589_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_150_o

_MUX_589_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_134_o_MUX_584_o1...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_134_

o_MUX_584_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_134_o_MUX_585_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_134_o

_MUX_585_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.s_out_d1_cdc_to_GND_70_o_MUX_51_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o

_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.p_in_d1_cdc_from_GND_70_o_MUX_50_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_

o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_70_o_MUX_51_o11 T...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_

MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_70_o_MUX_50_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o

_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_34_o<7>11 TNM = FFS:TNM_axi_vdma_1...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_34_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_26_o<7>11 TNM = FFS:TNM_axi_vdma_1...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_26_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_1/axi_vdma_1\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_10_o<7>11 TNM = FFS:TNM_axi_vdma_1...>: No instances of type FFS were


   found under block


   "axi_vdma_1/axi_vdma_1/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_10_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.s_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_lev

el_out_d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I\/Mmux_GE


   NERATE_LEVEL_P_S_CDC.p_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_P_S_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_lev

el_in_d1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.s_level_out_d1_cdc_to_GN...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.s_level_out_

d1_cdc_to_GND_618_o_MUX_710_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I\/Mmux_GENERATE_


   LEVEL_P_S_CDC.p_level_in_d1_cdc_from_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.SHUTDOWN_RST_CDC_I/Mmux_GENERATE_LEVEL_P_S_CDC.p_level_in_d

1_cdc_from_GND_618_o_MUX_709_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.HALT_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.HALT_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.s_level_in_d1_cdc_from_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_

d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I\/Mmux_GENERATE


   _LEVEL_S_P_CDC.p_level_out_d1_cdc_to_G...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_RUN_STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out

_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.s_level_in_d1_cdc_from_GND_629_o...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc_fr

om_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.STOP_CDC_I\/Mmux_GENERATE_LEVEL_S_


   P_CDC.p_level_out_d1_cdc_to_GND_629_o_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.STOP_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_level_out_d1_cdc_t

o_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.s_level_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.s_lev

el_in_d1_cdc_from_GND_629_o_MUX_712_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I\/Mmux_GE


   NERATE_LEVEL_S_P_CDC.p_level_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.ALL_LINES_XFRED_S_P_CDC_I/Mmux_GENERATE_LEVEL_S_P_CDC.p_lev

el_out_d1_cdc_to_GND_629_o_MUX_713_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF\/Mm


   ux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF/Mmux_GENERATE_PULSE_P_S_CDC_

OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cd...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.s_out_d1_cdc_to_GND_70_o_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_LINEBUF


   FER_I\/GEN_LINEBUF_FLUSH_SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I\/Mmux_GENERAT


   E_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_

SOF.GEN_FOR_ASYNC.MM2S_FSIZE_ERR_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED

.p_in_d1_cdc_from_GND_70_o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out


   _d1_cdc_to_GND_148_o_MUX_596_o11 TNM =...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_MUX_5

96_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.SOF_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_


   d1_cdc_from_GND_148_o_MUX_595_o11 TNM ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.SOF

_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o_MUX_

595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   p_out_d1_cdc_to_GND_148_o_MUX_596_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.p_out_d1_cdc_to_GND_148_o_

MUX_596_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_IN_CDC_I\/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.


   s_in_d1_cdc_from_GND_148_o_MUX_595_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_IN_CDC_I/Mmux_GENERATE_PULSE_S_P_CDC_OPEN_ENDED.s_in_d1_cdc_from_GND_148_o

_MUX_595_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.M_PTR_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_132_o_MUX_591_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.M_P

TR_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_132_o

_MUX_591_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.s_out_d1_cdc_to_GND_70_o_MUX_51_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o

_MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.PRMTR_UPDT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDE


   D.p_in_d1_cdc_from_GND_70_o_MUX_50_o11...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.PRM

TR_UPDT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_

o_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .s_out_d1_cdc_to_GND_70_o_MUX_51_o11 T...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_

MUX_51_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC


   _I\/GEN_CDC_FOR_ASYNC.FSYNC_OUT_CDC_I\/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED


   .p_in_d1_cdc_from_GND_70_o_MUX_50_o11 ...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_VID_CDC_I/GEN_CDC_FOR_ASYNC.FSY

NC_OUT_CDC_I/Mmux_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o

_MUX_50_o11" (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.p_in_d1_cdc_from_GND_70_o_MUX_50_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.


   LITE_WVALID_MM2S_CDC_I\/Mmux_GENERATE_...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GEN_LITE_IS_ASYNC.GEN_MM2S_ONLY_ASYNC_LITE_ACCESS.LITE_WVALID_MM2S_CDC_I/Mmu

x_GENERATE_PULSE_P_S_CDC_OPEN_ENDED.s_out_d1_cdc_to_GND_70_o_MUX_51_o11"


   (type=LUT2).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_34_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_34_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_26_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_26_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_vdma_0/axi_vdma_0\/AXI_LITE_REG_INTERFACE_I\/GEN_


   AXI_LITE_IF.AXI_LITE_IF_I\/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_eq


   ual_10_o<7>11 TNM = FFS:TNM_axi_vdma_0...>: No instances of type FFS were


   found under block


   "axi_vdma_0/axi_vdma_0/AXI_LITE_REG_INTERFACE_I/GEN_AXI_LITE_IF.AXI_LITE_IF_I

/GND_69_o_axi2ip_wraddr_captured_mm2s_cdc_tig[7]_equal_10_o<7>11"


   (type=LUT3).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_3/axi_interconnect_3\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_3_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_3/axi_interconnect_3/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_2/axi_interconnect_2\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_2_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_2/axi_interconnect_2/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem:135 - Constraint <INST


   /system/EXPANDED/system/axi_interconnect_1/axi_interconnect_1\/si_converter_b


   ank\/gen_conv_slot[0].clock_conv_inst\/interconnect_aresetn_resync<2>_inv1_IN


   V_0 TNM = FFS:axi_interconnect_1_reset...>: No instances of type FFS were


   found under block


   "axi_interconnect_1/axi_interconnect_1/si_converter_bank/gen_conv_slot[0].clo

ck_conv_inst/interconnect_aresetn_resync<2>_inv1_INV_0" (type=INV).





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_PORB_IBUF" LOC = B5>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_CLK_IBUF" LOC = F7>' could not be found and so


   the Locate constraint will be removed.





WARNING:ConstraintSystem - A target design object for the Locate constraint


   '<NET "processing_system7_0_PS_SRSTB_IBUF" LOC = C9>' could not be found and


   so the Locate constraint will be removed.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_1_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_2_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:58 - Constraint <TIMEGRP


   axi_interconnect_3_reset_source = FFS PADS CPUS;>: CPUS "*" does not match


   any design objects.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_1_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_from', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_to', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'TNM_axi_vdma_0_cdc_tig_v', does not


   directly or indirectly drive any flip-flops, latches and/or RAMs and is not


   actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_3_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_2_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





WARNING:ConstraintSystem:194 - The TNM 'axi_interconnect_1_reset_resync', does


   not directly or indirectly drive any flip-flops, latches and/or RAMs and is


   not actively used by any referencing constraint.





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   axi_clkgen_0/USER_LOGIC_I/i_clkgen/i_mmcm. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC


   TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s = PERIOD


   "axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I_i_clkgen_mmcm_clk_s" TS_clk_fpga_2 *


   0.742424242 HIGH 50>





INFO:ConstraintSystem:178 - TNM 'clk_fpga_2', used in period specification


   'TS_clk_fpga_2', was traced into MMCME2_ADV instance


   clock_generator_0/MMCM1_INST/MMCM_ADV_inst. The following new TNM groups and


   period specifications were generated at the MMCME2_ADV output(s): 


   CLKOUT0: <TIMESPEC TS_clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0 =


   PERIOD "clock_generator_0_clock_generator_0_SIG_MMCM1_CLKOUT0" TS_clk_fpga_2


   * 0.061440678 HIGH 50>





Done...





Processing BMM file "system.bmm" ...





WARNING::53 - File 'system.bmm' is empty or has no BMM content.








Checking expanded design ...


WARNING:NgdBuild:486 - Attribute "CLOCK_HOLD" is not allowed on symbol


   "clock_generator_0/MMCM1_INST/MMCM_ADV_inst" of type "MMCME2_ADV".  This


   attribute will be ignored.


WARNING:NgdBuild:440 - FF primitive


   'axi_ssm2518_0/axi_ssm2518_0/up_dac_common_i/i_drp_rst_reg' has unconnected


   output pin


WARNING:NgdBuild:441 - FF primitive


   'axi_ssm2518_0/axi_ssm2518_0/up_dac_common_i/i_drp_rst_reg' has unconnected


   clock pin


WARNING:NgdBuild:440 - FF primitive


   'axi_ssm2518_0/axi_ssm2518_0/up_dac_common_i/i_mmcm_rst_reg' has unconnected


   output pin


WARNING:NgdBuild:441 - FF primitive


   'axi_ssm2518_0/axi_ssm2518_0/up_dac_common_i/i_mmcm_rst_reg' has unconnected


   clock pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_0/axi_iic_0/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:443 - SFF primitive


   'axi_iic_1/axi_iic_1/X_IIC/X_AXI_IPIF_SSP1/X_SOFT_RESET/FF_WRACK' has


   unconnected output pin


WARNING:NgdBuild:452 - logical net 'N165' has no driver


WARNING:NgdBuild:452 - logical net 'N166' has no driver


WARNING:NgdBuild:452 - logical net 'N167' has no driver


WARNING:NgdBuild:452 - logical net 'N168' has no driver


WARNING:NgdBuild:452 - logical net 'N169' has no driver


WARNING:NgdBuild:452 - logical net 'N170' has no driver


WARNING:NgdBuild:452 - logical net 'N171' has no driver


WARNING:NgdBuild:452 - logical net 'N172' has no driver


WARNING:NgdBuild:452 - logical net 'N173' has no driver


WARNING:NgdBuild:452 - logical net 'N174' has no driver


WARNING:NgdBuild:452 - logical net 'N175' has no driver


WARNING:NgdBuild:452 - logical net 'N176' has no driver


WARNING:NgdBuild:452 - logical net 'N177' has no driver


WARNING:NgdBuild:452 - logical net 'N178' has no driver


WARNING:NgdBuild:452 - logical net 'N179' has no driver


WARNING:NgdBuild:452 - logical net 'N180' has no driver


WARNING:NgdBuild:452 - logical net 'N181' has no driver


WARNING:NgdBuild:452 - logical net 'N182' has no driver


WARNING:NgdBuild:452 - logical net 'N183' has no driver


WARNING:NgdBuild:452 - logical net 'N184' has no driver


WARNING:NgdBuild:452 - logical net 'N185' has no driver


WARNING:NgdBuild:452 - logical net 'N186' has no driver


WARNING:NgdBuild:452 - logical net 'N187' has no driver


WARNING:NgdBuild:452 - logical net 'N188' has no driver


WARNING:NgdBuild:452 - logical net 'N189' has no driver


WARNING:NgdBuild:452 - logical net 'N190' has no driver


WARNING:NgdBuild:452 - logical net 'N191' has no driver


WARNING:NgdBuild:452 - logical net 'N192' has no driver


WARNING:NgdBuild:452 - logical net 'N193' has no driver


WARNING:NgdBuild:452 - logical net 'N194' has no driver


WARNING:NgdBuild:452 - logical net 'N195' has no driver


WARNING:NgdBuild:452 - logical net 'N196' has no driver


WARNING:NgdBuild:452 - logical net 'N197' has no driver


WARNING:NgdBuild:452 - logical net 'N198' has no driver


WARNING:NgdBuild:452 - logical net 'N199' has no driver


WARNING:NgdBuild:452 - logical net 'N200' has no driver


WARNING:NgdBuild:452 - logical net 'N201' has no driver


WARNING:NgdBuild:452 - logical net 'N202' has no driver


WARNING:NgdBuild:452 - logical net 'N203' has no driver


WARNING:NgdBuild:452 - logical net 'N204' has no driver


WARNING:NgdBuild:452 - logical net 'N205' has no driver


WARNING:NgdBuild:452 - logical net 'N206' has no driver


WARNING:NgdBuild:452 - logical net 'N207' has no driver


WARNING:NgdBuild:452 - logical net 'N208' has no driver


WARNING:NgdBuild:452 - logical net 'N209' has no driver


WARNING:NgdBuild:452 - logical net 'N210' has no driver


WARNING:NgdBuild:452 - logical net 'N211' has no driver


WARNING:NgdBuild:452 - logical net 'N212' has no driver


WARNING:NgdBuild:452 - logical net 'N213' has no driver


WARNING:NgdBuild:452 - logical net 'N214' has no driver


WARNING:NgdBuild:452 - logical net 'N215' has no driver


WARNING:NgdBuild:452 - logical net 'N216' has no driver


WARNING:NgdBuild:452 - logical net 'N217' has no driver


WARNING:NgdBuild:452 - logical net 'N218' has no driver


WARNING:NgdBuild:452 - logical net 'N219' has no driver


WARNING:NgdBuild:452 - logical net 'N220' has no driver


WARNING:NgdBuild:452 - logical net 'N221' has no driver


WARNING:NgdBuild:452 - logical net 'N222' has no driver


WARNING:NgdBuild:452 - logical net 'N223' has no driver


WARNING:NgdBuild:452 - logical net 'N224' has no driver


WARNING:NgdBuild:452 - logical net 'N225' has no driver


WARNING:NgdBuild:452 - logical net 'N226' has no driver


WARNING:NgdBuild:452 - logical net 'N227' has no driver


WARNING:NgdBuild:452 - logical net 'N228' has no driver


WARNING:NgdBuild:452 - logical net 'N229' has no driver


WARNING:NgdBuild:452 - logical net 'N230' has no driver


WARNING:NgdBuild:452 - logical net 'N231' has no driver


WARNING:NgdBuild:452 - logical net 'N232' has no driver


WARNING:NgdBuild:452 - logical net 'N233' has no driver


WARNING:NgdBuild:452 - logical net 'N234' has no driver


WARNING:NgdBuild:452 - logical net 'N235' has no driver


WARNING:NgdBuild:452 - logical net 'N236' has no driver


WARNING:NgdBuild:452 - logical net 'N237' has no driver


WARNING:NgdBuild:452 - logical net 'N238' has no driver


WARNING:NgdBuild:452 - logical net 'N239' has no driver


WARNING:NgdBuild:452 - logical net 'N240' has no driver


WARNING:NgdBuild:452 - logical net 'N241' has no driver


WARNING:NgdBuild:452 - logical net 'N242' has no driver


WARNING:NgdBuild:452 - logical net 'N243' has no driver


WARNING:NgdBuild:452 - logical net 'N244' has no driver


WARNING:NgdBuild:452 - logical net 'N245' has no driver


WARNING:NgdBuild:452 - logical net 'N246' has no driver


WARNING:NgdBuild:452 - logical net 'N247' has no driver


WARNING:NgdBuild:452 - logical net 'N248' has no driver


WARNING:NgdBuild:452 - logical net 'N249' has no driver


WARNING:NgdBuild:452 - logical net 'N250' has no driver


WARNING:NgdBuild:452 - logical net 'N251' has no driver


WARNING:NgdBuild:452 - logical net 'N252' has no driver


WARNING:NgdBuild:452 - logical net 'N253' has no driver


WARNING:NgdBuild:452 - logical net 'N254' has no driver


WARNING:NgdBuild:452 - logical net 'N255' has no driver


WARNING:NgdBuild:452 - logical net 'N256' has no driver


WARNING:NgdBuild:452 - logical net 'N257' has no driver


WARNING:NgdBuild:452 - logical net 'N258' has no driver


WARNING:NgdBuild:452 - logical net 'N259' has no driver


WARNING:NgdBuild:452 - logical net 'N260' has no driver


WARNING:NgdBuild:452 - logical net 'N261' has no driver


WARNING:NgdBuild:452 - logical net 'N262' has no driver


WARNING:NgdBuild:452 - logical net 'N263' has no driver


WARNING:NgdBuild:452 - logical net 'N264' has no driver


WARNING:NgdBuild:452 - logical net 'N265' has no driver


WARNING:NgdBuild:452 - logical net 'N266' has no driver


WARNING:NgdBuild:452 - logical net 'N267' has no driver


WARNING:NgdBuild:452 - logical net 'N268' has no driver


WARNING:NgdBuild:452 - logical net 'N269' has no driver


WARNING:NgdBuild:452 - logical net 'N270' has no driver


WARNING:NgdBuild:452 - logical net 'N271' has no driver


WARNING:NgdBuild:452 - logical net 'N272' has no driver


WARNING:NgdBuild:452 - logical net 'N273' has no driver


WARNING:NgdBuild:452 - logical net 'N274' has no driver


WARNING:NgdBuild:452 - logical net 'N275' has no driver


WARNING:NgdBuild:452 - logical net 'N276' has no driver


WARNING:NgdBuild:452 - logical net 'N277' has no driver


WARNING:NgdBuild:452 - logical net 'N278' has no driver


WARNING:NgdBuild:452 - logical net 'N279' has no driver


WARNING:NgdBuild:452 - logical net 'N280' has no driver


WARNING:NgdBuild:452 - logical net 'N316' has no driver


WARNING:NgdBuild:452 - logical net 'N317' has no driver


WARNING:NgdBuild:452 - logical net 'N318' has no driver


WARNING:NgdBuild:452 - logical net 'N319' has no driver


WARNING:NgdBuild:452 - logical net 'N320' has no driver


WARNING:NgdBuild:452 - logical net 'N321' has no driver


WARNING:NgdBuild:452 - logical net 'N322' has no driver


WARNING:NgdBuild:452 - logical net 'N323' has no driver


WARNING:NgdBuild:452 - logical net 'N324' has no driver


WARNING:NgdBuild:452 - logical net 'N325' has no driver





Partition Implementation Status


-------------------------------





  No Partitions were found in this design.





-------------------------------





NGDBUILD Design Results Summary:


  Number of errors:     0


  Number of warnings: 255





Writing NGD file "system.ngd" ...


Total REAL time to NGDBUILD completion:  40 sec


Total CPU time to NGDBUILD completion:   40 sec





Writing NGDBUILD log file "system.bld"...





NGDBUILD done.








#----------------------------------------------#

# Starting program map

# map -o system_map.ncd -w -pr b -ol high -timing -detail system.ngd system.pcf 

#----------------------------------------------#

Release 14.4 - Map P.49d (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.


PMSPEC -- Overriding Xilinx file


<D:/Xilinx/14.4/ISE_DS/EDK/data/Xdh_PrimTypeLib.xda> with local file


<D:/Xilinx/14.4/ISE_DS/ISE/data/Xdh_PrimTypeLib.xda>


Using target part "7z020clg484-1".


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<53>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<53>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<52>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<52>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<51>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<51>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<50>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<50>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<49>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<49>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<48>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<48>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<47>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<47>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<46>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<46>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<45>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<45>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<44>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<44>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<43>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<43>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<42>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<42>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<41>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<41>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<40>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<40>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<39>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<39>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<38>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<38>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<37>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<37>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<36>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<36>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<35>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<35>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<34>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<34>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<33>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<33>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<32>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<32>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<31>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<31>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<30>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<30>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<29>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<29>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<28>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<28>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<27>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<27>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<26>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<26>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<25>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<25>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<24>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<24>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<23>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<23>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<22>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<22>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<21>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<21>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<20>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<20>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<19>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<19>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<18>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<18>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<17>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<17>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<16>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<16>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<15>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<15>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<14>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<14>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<13>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<13>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<12>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<12>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<11>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<11>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<10>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<10>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<9>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<9>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<8>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<8>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<7>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<7>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<6>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<6>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<5>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<5>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<4>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<4>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<3>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<2>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<1>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_MIO<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_MIO<0>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_BankAddr<2>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_BankAddr<2>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_BankAddr<1>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_BankAddr<1>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_BankAddr<0>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_BankAddr<0>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<14>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<14>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<13>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<13>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<12>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<12>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<11>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<11>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<10>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<10>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<9>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<9>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<8>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<8>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<7>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<7>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<6>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<6>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<5>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<5>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<4>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<4>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<3>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<2>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<1>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Addr<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Addr<0>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<31>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<31>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<30>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<30>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<29>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<29>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<28>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<28>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<27>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<27>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<26>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<26>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<25>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<25>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<24>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<24>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<23>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<23>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<22>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<22>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<21>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<21>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<20>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<20>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<19>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<19>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<18>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<18>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<17>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<17>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<16>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<16>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<15>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<15>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<14>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<14>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<13>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<13>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<12>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<12>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<11>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<11>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<10>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<10>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<9>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<9>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<8>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<8>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<7>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<7>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<6>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<6>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<5>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<5>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<4>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<4>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<3>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<2>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<1>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQ<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQ<0>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DM<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DM<3>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DM<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DM<2>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DM<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DM<1>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DM<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DM<0>" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS<3>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS<3>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS<2>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS<2>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS<1>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS<1>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS<0>" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS<0>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS_n<3>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS_n<3>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS_n<2>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS_n<2>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS_n<1>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS_n<1>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DQS_n<0>" has an


   undefined IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DQS_n<0>" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Clk" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Clk" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_Clk_n" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_Clk_n" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_CKE" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_CKE" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_CS_n" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_CS_n" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_RAS_n" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_RAS_n" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_CAS_n" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_CAS_n" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_WEB_pin" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_WEB_pin" is not


   constrained (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_ODT" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_ODT" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_DRSTB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_DRSTB" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_VRN" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_VRN" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_DDR_VRP" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_DDR_VRP" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_SRSTB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_SRSTB" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_CLK" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_CLK" is not constrained


   (LOC) to a specific location.


WARNING:LIT:701 - PAD symbol "processing_system7_0_PS_PORB" has an undefined


   IOSTANDARD.


WARNING:LIT:702 - PAD symbol "processing_system7_0_PS_PORB" is not constrained


   (LOC) to a specific location.


Mapping design into LUTs...


Writing file system_map.ngm...


Running directed packing...


Running delay-based LUT packing...


Updating timing models...


INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report


   (.mrp).


Running timing-driven placement...


Total REAL time at the beginning of Placer: 38 secs 


Total CPU  time at the beginning of Placer: 38 secs 





Phase 1.1  Initial Placement Analysis


Phase 1.1  Initial Placement Analysis (Checksum:30c36b04) REAL time: 42 secs 





Phase 2.7  Design Feasibility Check


WARNING:Place:838 - An IO Bus with more than one IO standard is found.


   Components associated with this bus are as follows: 


   	 Comp: processing_system7_0_GPIO_pin<0>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<1>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<2>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<3>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<4>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<5>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<6>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<7>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<8>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<9>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<10>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<11>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<12>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<13>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<14>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<15>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<16>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<17>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<18>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<19>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<20>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<21>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<22>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<23>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<24>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<25>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<26>   IOSTANDARD = LVCMOS33


   	 Comp: processing_system7_0_GPIO_pin<27>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<28>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<29>   IOSTANDARD = LVCMOS25


   	 Comp: processing_system7_0_GPIO_pin<30>   IOSTANDARD = LVCMOS25








Phase 2.7  Design Feasibility Check (Checksum:30c36b04) REAL time: 43 secs 





Phase 3.31  Local Placement Optimization


Phase 3.31  Local Placement Optimization (Checksum:7000a95f) REAL time: 43 secs 





Phase 4.2  Initial Placement for Architecture Specific Features





Phase 4.2  Initial Placement for Architecture Specific Features


(Checksum:1466f4e6) REAL time: 52 secs 





Phase 5.30  Global Clock Region Assignment


Phase 5.30  Global Clock Region Assignment (Checksum:1466f4e6) REAL time: 52 secs 





Phase 6.3  Local Placement Optimization


Phase 6.3  Local Placement Optimization (Checksum:1466f4e6) REAL time: 52 secs 





Phase 7.5  Local Placement Optimization


Phase 7.5  Local Placement Optimization (Checksum:1466f4e6) REAL time: 53 secs 





Phase 8.8  Global Placement


...............................


...................................................................................................................


.....................................................................................................................


......................................................................................................................................................................


Phase 8.8  Global Placement (Checksum:d0dd5fe6) REAL time: 2 mins 50 secs 





Phase 9.5  Local Placement Optimization


Phase 9.5  Local Placement Optimization (Checksum:d0dd5fe6) REAL time: 2 mins 51 secs 





Phase 10.18  Placement Optimization


Phase 10.18  Placement Optimization (Checksum:c88ec4ad) REAL time: 3 mins 8 secs 





Phase 11.5  Local Placement Optimization


Phase 11.5  Local Placement Optimization (Checksum:c88ec4ad) REAL time: 3 mins 8 secs 





Phase 12.34  Placement Validation


Phase 12.34  Placement Validation (Checksum:c88ec4ad) REAL time: 3 mins 8 secs 





Total REAL time to Placer completion: 3 mins 9 secs 


Total CPU  time to Placer completion: 3 mins 9 secs 


Running post-placement packing...


Writing output files...





Design Summary:


Number of errors:      0


Number of warnings:  315


Slice Logic Utilization:


  Number of Slice Registers:                 7,583 out of 106,400    7


    Number used as Flip Flops:               7,536


    Number used as Latches:                     32


    Number used as Latch-thrus:                  0


    Number used as AND/OR logics:               15


  Number of Slice LUTs:                      7,286 out of  53,200   13


    Number used as logic:                    6,492 out of  53,200   12


      Number using O6 output only:           4,534


      Number using O5 output only:             155


      Number using O5 and O6:                1,803


      Number used as ROM:                        0


    Number used as Memory:                     558 out of  17,400    3


      Number used as Dual Port RAM:             84


        Number using O6 output only:             8


        Number using O5 output only:             7


        Number using O5 and O6:                 69


      Number used as Single Port RAM:            0


      Number used as Shift Register:           474


        Number using O6 output only:           466


        Number using O5 output only:             0


        Number using O5 and O6:                  8


    Number used exclusively as route-thrus:    236


      Number with same-slice register load:     84


      Number with same-slice carry load:       150


      Number with other load:                    2





Slice Logic Distribution:


  Number of occupied Slices:                 3,842 out of  13,300   28


  Number of LUT Flip Flop pairs used:       10,170


    Number with an unused Flip Flop:         3,213 out of  10,170   31


    Number with an unused LUT:               2,884 out of  10,170   28


    Number of fully used LUT-FF pairs:       4,073 out of  10,170   40


    Number of unique control sets:             523


    Number of slice register sites lost


      to control set restrictions:           2,253 out of 106,400    2





  A LUT Flip Flop pair for this architecture represents one LUT paired with


  one Flip Flop within a slice.  A control set is a unique combination of


  clock, reset, set, and enable signals for a registered element.


  The Slice Logic Distribution report is not meaningful if the design is


  over-mapped for a non-slice resource or if Placement fails.


  OVERMAPPING of BRAM resources should be ignored if the design is


  over-mapped for a non-BRAM resource or if placement fails.





IO Utilization:


  Number of bonded IOBs:                        82 out of     200   41


    Number of LOCed IOBs:                       82 out of      82  100


  Number of bonded IOPAD:                      130 out of     130  100


    IOB Flip Flops:                             25





Specific Feature Utilization:


  Number of RAMB36E1/FIFO36E1s:                  3 out of     140    2


    Number using RAMB36E1 only:                  3


    Number using FIFO36E1 only:                  0


  Number of RAMB18E1/FIFO18E1s:                  3 out of     280    1


    Number using RAMB18E1 only:                  3


    Number using FIFO18E1 only:                  0


  Number of BUFG/BUFGCTRLs:                      7 out of      32   21


    Number used as BUFGs:                        7


    Number used as BUFGCTRLs:                    0


  Number of IDELAYE2/IDELAYE2_FINEDELAYs:        0 out of     200    0


  Number of ILOGICE2/ILOGICE3/ISERDESE2s:        1 out of     200    1


    Number used as ILOGICE2s:                    1


  Number used as  ILOGICE3s:                     0


    Number used as ISERDESE2s:                   0


  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0


  Number of OLOGICE2/OLOGICE3/OSERDESE2s:       55 out of     200   27


    Number used as OLOGICE2s:                   55


    Number used as OLOGICE3s:                    0


    Number used as OSERDESE2s:                   0


  Number of PHASER_IN/PHASER_IN_PHYs:            0 out of      16    0


  Number of PHASER_OUT/PHASER_OUT_PHYs:          0 out of      16    0


  Number of BSCANs:                              0 out of       4    0


  Number of BUFHCEs:                             0 out of      72    0


  Number of BUFRs:                               0 out of      16    0


  Number of CAPTUREs:                            0 out of       1    0


  Number of DNA_PORTs:                           0 out of       1    0


  Number of DSP48E1s:                            0 out of     220    0


  Number of EFUSE_USRs:                          0 out of       1    0


  Number of FRAME_ECCs:                          0 out of       1    0


  Number of ICAPs:                               0 out of       2    0


  Number of IDELAYCTRLs:                         0 out of       4    0


  Number of IN_FIFOs:                            0 out of      16    0


  Number of MMCME2_ADVs:                         2 out of       4   50


  Number of OUT_FIFOs:                           0 out of      16    0


  Number of PHASER_REFs:                         0 out of       4    0


  Number of PHY_CONTROLs:                        0 out of       4    0


  Number of PLLE2_ADVs:                          0 out of       4    0


  Number of PS7s:                                1 out of       1  100


  Number of STARTUPs:                            0 out of       1    0


  Number of XADCs:                               0 out of       1    0





Average Fanout of Non-Clock Nets:                3.42





Peak Memory Usage:  1041 MB


Total REAL time to MAP completion:  3 mins 17 secs 


Total CPU time to MAP completion:   3 mins 17 secs 





Mapping completed.


See MAP report file "system_map.mrp" for details.








#----------------------------------------------#

# Starting program par

# par -w -ol high system_map.ncd system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - par P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/data/parBmgr.acd> with local file

<D:/Xilinx/14.4/ISE_DS/ISE/data/parBmgr.acd>







Constraints file: system.pcf.

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1



Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)





Device speed data version:  "ADVANCED 1.04 2012-12-04".







Device Utilization Summary:



   Number of BUFGs                           7 out of 32     21

   Number of ILOGICE2s                       1 out of 200     1

   Number of External IOB33s                82 out of 200    41

      Number of LOCed IOB33s                82 out of 82    100



   Number of External IOPADs               130 out of 130   100

      Number of LOCed IOPADs                 0 out of 130     0



   Number of MMCME2_ADVs                     2 out of 4      50

   Number of OLOGICE2s                      55 out of 200    27

   Number of PS7s                            1 out of 1     100

   Number of RAMB18E1s                       3 out of 280     1

   Number of RAMB36E1s                       3 out of 140     2

   Number of Slices                       3842 out of 13300  28

   Number of Slice Registers              7583 out of 106400  7

      Number used as Flip Flops           7551

      Number used as Latches                32

      Number used as LatchThrus              0



   Number of Slice LUTS                   7286 out of 53200  13

   Number of Slice LUT-Flip Flop pairs    9931 out of 53200  18





Overall effort level (-ol):   High 

Router effort level (-rl):    High 



INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx

   Command Line Tools User Guide for information on generating a TSI report.

Starting initial Timing Analysis.  REAL time: 20 secs 

Finished initial Timing Analysis.  REAL time: 20 secs 



WARNING:Par:288 - The signal hdmi_int_IBUF has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route

   this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3> has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O has no load.  PAR will not attempt to route this

   signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_3/axi_interconnect_3/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM

   _RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mra

   m_RAM_RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_3/axi_interconnect_3/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mra

   m_RAM_RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal

   axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slot[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRIT

   E.write_addr_inst/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM

   _RAMD_D1_O has no load.  PAR will not attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

WARNING:Par:288 - The signal axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D1_O has no load.  PAR will not

   attempt to route this signal.

Starting Router





Phase  1  : 47337 unrouted;      REAL time: 23 secs 



Phase  2  : 37962 unrouted;      REAL time: 24 secs 



Phase  3  : 12266 unrouted;      REAL time: 37 secs 



Phase  4  : 12285 unrouted; (Setup:0, Hold:79655, Component Switching Limit:0)     REAL time: 43 secs 



Updating file: system.ncd with current fully routed design.



Phase  5  : 0 unrouted; (Setup:0, Hold:69724, Component Switching Limit:0)     REAL time: 55 secs 



Phase  6  : 0 unrouted; (Setup:0, Hold:69724, Component Switching Limit:0)     REAL time: 55 secs 



Phase  7  : 0 unrouted; (Setup:0, Hold:69724, Component Switching Limit:0)     REAL time: 55 secs 



Phase  8  : 0 unrouted; (Setup:0, Hold:69724, Component Switching Limit:0)     REAL time: 55 secs 



Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 59 secs 

Total REAL time to Router completion: 59 secs 

Total CPU time to Router completion: 1 mins 1 secs 



Partition Implementation Status

-------------------------------



  No Partitions were found in this design.



-------------------------------



Generating "PAR" statistics.



**************************

Generating Clock Report

**************************



+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK1 |BUFGCTRL_X0Y29| No   | 1354 |  0.434     |  2.053      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK0 |BUFGCTRL_X0Y31| No   |  960 |  0.439     |  2.058      |

+---------------------+--------------+------+------+------------+-------------+

|axi_hdmi_tx_16b_0_hd |              |      |      |            |             |

|          mi_ref_clk | BUFGCTRL_X0Y1| No   |  370 |  0.247     |  1.902      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0_bclk_o |              |      |      |            |             |

|           _pin_OBUF | BUFGCTRL_X0Y2| No   |   74 |  0.344     |  2.061      |

+---------------------+--------------+------+------+------------+-------------+

|axi_i2s_adi_0_MCLK_p |              |      |      |            |             |

|             in_OBUF |BUFGCTRL_X0Y28| No   |   16 |  0.177     |  1.890      |

+---------------------+--------------+------+------+------------+-------------+

|axi_clkgen_0/axi_clk |              |      |      |            |             |

|gen_0/USER_LOGIC_I/i |              |      |      |            |             |

|_clkgen/buf_fb_clk_s |              |      |      |            |             |

|                     | BUFGCTRL_X0Y0| No   |    1 |  0.000     |  1.759      |

+---------------------+--------------+------+------+------------+-------------+

|processing_system7_0 |              |      |      |            |             |

|          _FCLK_CLK2 |BUFGCTRL_X0Y30| No   |    2 |  0.218     |  1.980      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        14]_AND_41_o |         Local|      |    2 |  0.000     |  0.821      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         8]_AND_53_o |         Local|      |    2 |  0.000     |  0.967      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        26]_AND_17_o |         Local|      |    2 |  0.000     |  0.545      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|           ad_data_s |         Local|      |   42 |  0.866     |  3.924      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        21]_AND_27_o |         Local|      |    2 |  0.000     |  0.558      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         30]_AND_9_o |         Local|      |    2 |  0.000     |  0.556      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         1]_AND_67_o |         Local|      |    2 |  0.000     |  0.830      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        10]_AND_49_o |         Local|      |    2 |  0.000     |  0.967      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        17]_AND_35_o |         Local|      |    2 |  0.000     |  0.595      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        20]_AND_29_o |         Local|      |    2 |  0.000     |  0.595      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         6]_AND_57_o |         Local|      |    2 |  0.000     |  0.664      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        18]_AND_33_o |         Local|      |    2 |  0.000     |  0.356      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         0]_AND_69_o |         Local|      |    2 |  0.000     |  0.595      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        11]_AND_47_o |         Local|      |    2 |  0.000     |  1.085      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         4]_AND_61_o |         Local|      |    2 |  0.000     |  0.962      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        27]_AND_15_o |         Local|      |    2 |  0.000     |  0.503      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        19]_AND_31_o |         Local|      |    2 |  0.000     |  0.593      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        12]_AND_45_o |         Local|      |    2 |  0.000     |  0.679      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        28]_AND_13_o |         Local|      |    2 |  0.000     |  0.595      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        16]_AND_37_o |         Local|      |    2 |  0.000     |  0.545      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         7]_AND_55_o |         Local|      |    2 |  0.000     |  0.405      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        13]_AND_43_o |         Local|      |    2 |  0.000     |  0.821      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        29]_AND_11_o |         Local|      |    2 |  0.000     |  0.760      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        22]_AND_25_o |         Local|      |    2 |  0.000     |  0.405      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         9]_AND_51_o |         Local|      |    2 |  0.000     |  0.794      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        15]_AND_39_o |         Local|      |    2 |  0.000     |  0.777      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        23]_AND_23_o |         Local|      |    2 |  0.000     |  0.821      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         2]_AND_65_o |         Local|      |    2 |  0.000     |  0.558      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        24]_AND_21_o |         Local|      |    2 |  0.000     |  0.356      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         3]_AND_63_o |         Local|      |    2 |  0.000     |  0.547      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|        25]_AND_19_o |         Local|      |    2 |  0.000     |  0.764      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         5]_AND_59_o |         Local|      |    2 |  0.000     |  0.687      |

+---------------------+--------------+------+------+------------+-------------+

|axi_ssm2518_0/axi_ss |              |      |      |            |             |

|m2518_0/ssm2518_i/lo |              |      |      |            |             |

|ad_data_s_tx_data_i[ |              |      |      |            |             |

|         31]_AND_7_o |         Local|      |    2 |  0.000     |  0.982      |

+---------------------+--------------+------+------+------------+-------------+

|clock_generator_0/cl |              |      |      |            |             |

|ock_generator_0/SIG_ |              |      |      |            |             |

|      MMCM1_CLKFBOUT |         Local|      |    1 |  0.000     |  0.014      |

+---------------------+--------------+------+------+------------+-------------+



* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.



* The fanout is the number of component pins not the individual BEL loads,

for example SLICE loads not FF loads.



Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Number of Timing Constraints that were not applied: 1



Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.



----------------------------------------------------------------------------------------------------------

  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   

                                            |             |    Slack   | Achievable | Errors |    Score   

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_1 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.110ns|     6.890ns|       0|           0

  1" 142.857 MHz HIGH 50| HOLD        |     0.012ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_ | SETUP       |     0.144ns|     9.856ns|       0|           0

  0" 100 MHz HIGH 50| HOLD        |     0.020ns|            |       0|           0

----------------------------------------------------------------------------------------------------------

  TS_axi_clkgen_0_axi_clkgen_0_USER_LOGIC_I | SETUP       |     0.553ns|     6.181ns|       0|           0

  _i_clkgen_mmcm_clk_s = PERIOD TIMEGRP     | HOLD        |     0.085ns|            |       0|           0

       "axi_clkgen_0_axi_clkgen_0_USER_LOGI |             |            |            |        |            

  C_I_i_clkgen_mmcm_clk_s"         TS_clk_f |             |            |            |        |            

  pga_2 * 0.742424242 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clk_fpga_2 = PERIOD TIMEGRP "clk_fpga_ | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0

  2" 200 MHz HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  TS_clock_generator_0_clock_generator_0_SI | SETUP       |    77.520ns|     3.859ns|       0|           0

  G_MMCM1_CLKOUT0 = PERIOD TIMEGRP          | HOLD        |     0.034ns|            |       0|           0

  "clock_generator_0_clock_generator_0_SIG_ |             |            |            |        |            

  MMCM1_CLKOUT0" TS_clk_fpga_2         * 0. |             |            |            |        |            

  061440678 HIGH 50|             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_1_cdc_tig_v_path" TIG   | SETUP       |         N/A|     8.008ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_1_cdc_from_2_cdc_to_pat | SETUP       |         N/A|     2.888ns|     N/A|           0

  h" TIG                                    |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_tig_v_path" TIG   | SETUP       |         N/A|     7.177ns|     N/A|           0

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_vdma_0_cdc_from_2_cdc_to_pat | SETUP       |         N/A|     2.486ns|     N/A|           0

  h" TIG                                    |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_3_reset_resync_ | SETUP       |         N/A|     1.118ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_2_reset_resync_ | SETUP       |         N/A|     1.123ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------

  PATH "TS_axi_interconnect_1_reset_resync_ | SETUP       |         N/A|     1.055ns|     N/A|           0

  path" TIG                                 |             |            |            |        |            

----------------------------------------------------------------------------------------------------------





Derived Constraint Report

Review Timing Report for more details on the following derived constraints.

To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"

or "Run Timing Analysis" from Timing Analyzer (timingan).

Derived Constraints for TS_clk_fpga_2

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |

|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|

|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

|TS_clk_fpga_2                  |      5.000ns|      2.800ns|      4.589ns|            0|            0|            0|        43851|

| TS_axi_clkgen_0_axi_clkgen_0_U|      6.735ns|      6.181ns|          N/A|            0|            0|        43794|            0|

| SER_LOGIC_I_i_clkgen_mmcm_clk_|             |             |             |             |             |             |             |

| s                             |             |             |             |             |             |             |             |

| TS_clock_generator_0_clock_gen|     81.379ns|      3.859ns|          N/A|            0|            0|           57|            0|

| erator_0_SIG_MMCM1_CLKOUT0    |             |             |             |             |             |             |             |

+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+



All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 

   constraint is not analyzed due to the following: No paths covered by this 

   constraint; Other constraints intersect with this constraint; or This 

   constraint was disabled by a Path Tracing Control. Please run the Timespec 

   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.





Generating Pad Report.



All signals are completely routed.



WARNING:Par:283 - There are 21 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.



Total REAL time to PAR completion: 1 mins 10 secs 

Total CPU time to PAR completion: 1 mins 4 secs 



Peak Memory Usage:  918 MB



Placer: Placement generated during map.

Routing: Completed - No errors found.

Timing: Completed - No errors found.



Number of error messages: 0

Number of warning messages: 23

Number of info messages: 1



Writing design to file system.ncd







PAR done!







#----------------------------------------------#

# Starting program post_par_trce

# trce -e 3 -xml system.twx system.ncd system.pcf 

#----------------------------------------------#

Release 14.4 - Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.








PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>


with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>


Loading device for application Rf_Device from file '7z020.nph' in environment


D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.


   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1


INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more


   information, see the TSI report.  Please consult the Xilinx Command Line


   Tools User Guide for information on generating a TSI report.


--------------------------------------------------------------------------------


Release 14.4 Trace  (nt64)


Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.





D:\Xilinx\14.4\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -e 3 -xml system.twx


system.ncd system.pcf








Design file:              system.ncd


Physical constraint file: system.pcf


Device,speed:             xc7z020,-1 (ADVANCED 1.04 2012-12-04)


Report level:             error report


--------------------------------------------------------------------------------





INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).


INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in


   the unconstrained paths section(s) of the report.


INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of


   this model, and for more information on accounting for different loading conditions, please see the device datasheet.








Timing summary:


---------------





Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)





Constraints cover 479866 paths, 0 nets, and 39799 connections





Design statistics:


   Minimum period:   9.856ns (Maximum frequency: 101.461MHz)








Analysis completed Tue Sep 24 16:07:08 2013


--------------------------------------------------------------------------------





Generating Report ...





Number of warnings: 0


Number of info messages: 4


Total time: 23 secs 






xflow done!

touch __xps/system_routed

xilperl D:/Xilinx/14.4/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par

Analyzing implementation/system.par

"*********************************************"

"Running Bitgen.."

"*********************************************"

cd implementation & bitgen -w -f bitgen.ut system & cd ..

Release 14.4 - Bitgen P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

PMSPEC -- Overriding Xilinx file <D:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>

with local file <D:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>

Loading device for application Rf_Device from file '7z020.nph' in environment

D:\Xilinx\14.4\ISE_DS\ISE\;D:\Xilinx\14.4\ISE_DS\EDK.

   "system" is an NCD, version 3.2, device xc7z020, package clg484, speed -1

Opened constraints file system.pcf.



Tue Sep 24 16:07:22 2013



Running DRC.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[14]_AND_41_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[8]_AND_53_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[26]_AND_17_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s is sourced by a

   combinatorial pin. This is not good design practice. Use the CE pin to

   control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[21]_AND_27_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[30]_AND_9_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[1]_AND_67_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[10]_AND_49_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[17]_AND_35_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[20]_AND_29_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[6]_AND_57_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[18]_AND_33_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[0]_AND_69_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[11]_AND_47_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[4]_AND_61_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[27]_AND_15_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[19]_AND_31_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[12]_AND_45_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[28]_AND_13_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[16]_AND_37_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[7]_AND_55_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[13]_AND_43_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[29]_AND_11_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[22]_AND_25_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[9]_AND_51_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[15]_AND_39_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[23]_AND_23_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[2]_AND_65_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[24]_AND_21_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[3]_AND_63_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[25]_AND_19_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[5]_AND_59_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:372 - Gated clock. Clock net

   axi_ssm2518_0/axi_ssm2518_0/ssm2518_i/load_data_s_tx_data_i[31]_AND_7_o is

   sourced by a combinatorial pin. This is not good design practice. Use the CE

   pin to control the loading of data into the flip-flop.

WARNING:PhysDesignRules:367 - The signal <hdmi_int_IBUF> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_gen.rx_sync/Mram_fifo_RAMD_D1_O> is

   incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/rx_sync_fifo_in<3>> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/ctrl/tx_sync/Mram_fifo_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_3/axi_interconnect_3/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/

   grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfif

   o.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_3/axi_interconnect_3/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfif

   o.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete.

   The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_interconnect_2/axi_interconnect_2/mi_protocol_conv_bank/gen_protocol_slo

   t[0].gen_prot_conv.conv_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_ins

   t/USE_BURSTS.cmd_queue/inst/fifo_gen_inst/U0/xst_fifo_generator/gconvfifo.rf/

   grf.rf/gntv_or_sync_fifo.mem/gdm.dm/Mram_RAM_RAMD_D1_O> is incomplete. The

   signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_rx_gen.rx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo1_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo4_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo2_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_i2s_adi_0/axi_i2s_adi_0/pl330_dma_tx_gen.tx_fifo/fifo/Mram_data_fifo3_RA

   MD_D1_O> is incomplete. The signal does not drive any load pins in the

   design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo4_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo3_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo1_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo5_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

WARNING:PhysDesignRules:367 - The signal

   <axi_spdif_tx_0/axi_spdif_tx_0/pl330_dma_gen.fifo/fifo/Mram_data_fifo2_RAMD_D

   1_O> is incomplete. The signal does not drive any load pins in the design.

INFO:PhysDesignRules:2288 - The read port and write port clocks of BRAM

   instance,

   axi_vdma_0/axi_vdma_0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_FLUSH_S

   OF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.V6.I_LINEBUFFER_FIFO/fg91_inst/U0/xst_fifo_g

   enerator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/g

   nativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WI

   DE_PRIM36.ram, are using the same clock signal (synchronous clocking) with

   WRITE_FIRST mode specified. This configuration may encounter address

   collisions if the same address appears on both ports. It is suggested for

   this configuration to use READ_FIRST mode to avoid any conditions for address

   collision. See the FPGA Memory Resources User Guide for additional

   information.

INFO:PhysDesignRules:2288 - The read port and write port clocks of BRAM

   instance,

   axi_vdma_1/axi_vdma_1/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.

   GEN_LINEBUFFER.GEN_ASYNC_FIFO.V6.I_LINEBUFFER_FIFO/fg91_inst/U0/xst_fifo_gene

   rator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmgb.ngecc.bmg/gnat

   ivebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_

   PRIM18.ram, are using the same clock signal (synchronous clocking) with

   WRITE_FIRST mode specified. This configuration may encounter address

   collisions if the same address appears on both ports. It is suggested for

   this configuration to use READ_FIRST mode to avoid any conditions for address

   collision. See the FPGA Memory Resources User Guide for additional

   information.

DRC detected 0 errors and 54 warnings.  Please see the previously displayed

individual error or warning messages for more details.

Creating bit map...

Saving bit stream in "system.bit".

Bitstream generation is complete.

Done!

********************************************************************************
At Local date and time: Tue Sep 24 16:08:06 2013
 xsdk.exe -hwspec D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\SDK\SDK_Export\hw\system.xml started...
Xilinx Software Development Kit

Xilinx EDK 14.4 Build EDK_P.49d

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Done!

********************************************************************************
At Local date and time: Tue Sep 24 16:12:46 2013
 make -f system.make exporttosdk started...
make: Nothing to be done for `exporttosdk'.

Done!

********************************************************************************
At Local date and time: Tue Sep 24 16:12:46 2013
 xsdk.exe -hwspec D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\SDK\SDK_Export\hw\system.xml started...
Xilinx Software Development Kit

Xilinx EDK 14.4 Build EDK_P.49d

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Done!

********************************************************************************
At Local date and time: Tue Sep 24 16:14:32 2013
 make -f system.make exporttosdk started...
make: Nothing to be done for `exporttosdk'.

Done!

********************************************************************************
At Local date and time: Tue Sep 24 16:14:33 2013
 xsdk.exe -hwspec D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\SDK\SDK_Export\hw\system.xml started...
Xilinx Software Development Kit

Xilinx EDK 14.4 Build EDK_P.49d

Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Done!
Writing filter settings....
Done writing filter settings to:
	D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\etc\system.filters
Done writing Tab View settings to:
	D:\Temp\fpgahdl_xilinx\cf_ssm2518_zed\etc\system.gui

********************************************************************************
At Local date and time: Fri Sep 27 16:54:32 2013
 make -f system.make clean started...
rm -f implementation/system.ngc

rm -f implementation/system_processing_system7_0_wrapper.ngc implementation/system_axi_vdma_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_axi_interconnect_2_wrapper.ngc implementation/system_axi_hdmi_tx_16b_0_wrapper.ngc implementation/system_axi_spdif_tx_0_wrapper.ngc implementation/system_axi_iic_0_wrapper.ngc implementation/system_axi_clkgen_0_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_util_vector_logic_0_wrapper.ngc implementation/system_axi_i2s_adi_0_wrapper.ngc implementation/system_util_i2c_mixer_0_wrapper.ngc implementation/system_axi_iic_1_wrapper.ngc implementation/system_axi_interconnect_3_wrapper.ngc implementation/system_axi_vdma_1_wrapper.ngc implementation/system_axi_ssm2518_0_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

rm -f implementation/system.bit

rm -f implementation/system.ncd

rm -f implementation/system_bd.bmm 

rm -f implementation/system_map.ncd 

rm -f implementation/download.bit 

rm -f __xps/system_bits

rm -rf implementation synthesis xst hdl

rm -rf xst.srp system.srp

rm -f __xps/ise/_xmsgs/bitinit.xmsgs

rm -rf __xps/ps7_instance.mhs

rm -rf simulation/behavioral

rm -f simgen.log

rm -f __xps/ise/_xmsgs/simgen.xmsgs

rm -f _impact.cmd

Done!

********************************************************************************
At Local date and time: Fri Sep 27 16:54:37 2013
 make -f system.make netlistclean started...
rm -f implementation/system.ngc

rm -f implementation/system_processing_system7_0_wrapper.ngc implementation/system_axi_vdma_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_axi_interconnect_2_wrapper.ngc implementation/system_axi_hdmi_tx_16b_0_wrapper.ngc implementation/system_axi_spdif_tx_0_wrapper.ngc implementation/system_axi_iic_0_wrapper.ngc implementation/system_axi_clkgen_0_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_util_vector_logic_0_wrapper.ngc implementation/system_axi_i2s_adi_0_wrapper.ngc implementation/system_util_i2c_mixer_0_wrapper.ngc implementation/system_axi_iic_1_wrapper.ngc implementation/system_axi_interconnect_3_wrapper.ngc implementation/system_axi_vdma_1_wrapper.ngc implementation/system_axi_ssm2518_0_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

Done!

********************************************************************************
At Local date and time: Fri Sep 27 16:54:41 2013
 make -f system.make bitsclean started...
rm -f implementation/system.bit

rm -f implementation/system.ncd

rm -f implementation/system_bd.bmm 

rm -f implementation/system_map.ncd 

rm -f implementation/download.bit 

rm -f __xps/system_bits

Done!

********************************************************************************
At Local date and time: Fri Sep 27 16:54:45 2013
 make -f system.make hwclean started...
rm -f implementation/system.ngc

rm -f implementation/system_processing_system7_0_wrapper.ngc implementation/system_axi_vdma_0_wrapper.ngc implementation/system_axi_interconnect_1_wrapper.ngc implementation/system_axi_interconnect_2_wrapper.ngc implementation/system_axi_hdmi_tx_16b_0_wrapper.ngc implementation/system_axi_spdif_tx_0_wrapper.ngc implementation/system_axi_iic_0_wrapper.ngc implementation/system_axi_clkgen_0_wrapper.ngc implementation/system_clock_generator_0_wrapper.ngc implementation/system_util_vector_logic_0_wrapper.ngc implementation/system_axi_i2s_adi_0_wrapper.ngc implementation/system_util_i2c_mixer_0_wrapper.ngc implementation/system_axi_iic_1_wrapper.ngc implementation/system_axi_interconnect_3_wrapper.ngc implementation/system_axi_vdma_1_wrapper.ngc implementation/system_axi_ssm2518_0_wrapper.ngc

rm -f platgen.log

rm -f __xps/ise/_xmsgs/platgen.xmsgs

rm -f implementation/system.bmm

rm -rf implementation/cache

rm -f implementation/system.bit

rm -f implementation/system.ncd

rm -f implementation/system_bd.bmm 

rm -f implementation/system_map.ncd 

rm -f implementation/download.bit 

rm -f __xps/system_bits

rm -rf implementation synthesis xst hdl

rm -rf xst.srp system.srp

rm -f __xps/ise/_xmsgs/bitinit.xmsgs

rm -rf __xps/ps7_instance.mhs

Done!
Writing filter settings....
Done writing filter settings to:
	D:\AD\GitHub\no-OS\Pmods\PmodAMP3\cf_ssm2518_zed\etc\system.filters
Done writing Tab View settings to:
	D:\AD\GitHub\no-OS\Pmods\PmodAMP3\cf_ssm2518_zed\etc\system.gui
