PIC12F510
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC12F510
CONFIG (address:0x0FFF, mask:0x003F, default:0x003F)
OSC -- Oscillator Select (bitmask:0x0003)
OSC = LP | 0x0FFC | LP oscillator with 18 ms DRT.
OSC = XT | 0x0FFD | XT oscillator with 18 ms DRT.
OSC = IntRC | 0x0FFE | INTOSC with 1.125 ms DRT.
OSC = ExtRC | 0x0FFF | EXTRC with 1.125 ms DRT.
WDT -- Watchdog Timer Enable bit (bitmask:0x0004)
WDT = OFF | 0x0FFB | WDT disabled.
WDT = ON | 0x0FFF | WDT enabled.
CP -- Code Protect (bitmask:0x0008)
CP = ON | 0x0FF7 | Code protection on.
CP = OFF | 0x0FFF | Code protection off.
MCLRE -- Master Clear Enable bit (bitmask:0x0010)
MCLRE = OFF | 0x0FEF | GP3/MCLR pin functions as GP3, MCLR internally tied to VDD.
MCLRE = ON | 0x0FFF | GP3/MCLR Functions as MCLR.
IOSCFS -- Internal Oscillator Frequency Select bit (bitmask:0x0020)
IOSCFS = OFF | 0x0FDF | 4 MHz INTOSC Speed.
IOSCFS = ON | 0x0FFF | 8 MHz INTOSC Speed.

This page generated automatically by the device-help.pl program (2014-09-27 07:53:45 UTC) from the 8bit_device.info file (rev: 1.21) of mpasmx and from the gputils source package (rev: svn 1103). The mpasmx is included in the MPLAB X.