PIC16F636
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC16F636
CONFIG (address:0x2007, mask:0x1FFF, default:0x1FFF)
FOSC -- Oscillator Selection bits (bitmask:0x0007)
FOSC = LP | 0x3FF8 | LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
FOSC = XT | 0x3FF9 | XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
FOSC = HS | 0x3FFA | HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
FOSC = EC | 0x3FFB | EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN.
FOSC = INTOSCIO | 0x3FFC | INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN.
FOSC = INTOSCCLK | 0x3FFD | INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN.
FOSC = EXTRCIO | 0x3FFE | RCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN.
FOSC = EXTRCCLK | 0x3FFF | RC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0008)
WDTE = OFF | 0x3FF7 | WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
WDTE = ON | 0x3FFF | WDT enabled.
PWRTE -- Power-up Timer Enable bit (bitmask:0x0010)
PWRTE = ON | 0x3FEF | PWRT enabled.
PWRTE = OFF | 0x3FFF | PWRT disabled.
MCLRE -- MCLR pin function select bit (bitmask:0x0020)
MCLRE = OFF | 0x3FDF | MCLR pin function is alternate function, MCLR function is internally disabled.
MCLRE = ON | 0x3FFF | MCLR pin is MCLR function and weak internal pull-up is enabled.
CP -- Code Protection bit (bitmask:0x0040)
CP = ON | 0x3FBF | Program memory is external read and write-protected.
CP = OFF | 0x3FFF | Program memory is not code protected.
CPD -- Data Code Protection bit (bitmask:0x0080)
CPD = ON | 0x3F7F | Data memory is external read protected.
CPD = OFF | 0x3FFF | Data memory is not code protected.
BOREN -- Brown-out Reset Selection bits (bitmask:0x0300)
BOREN = OFF | 0x3CFF | BOD and SBODEN disabled.
BOREN = SBODEN | 0x3DFF | SBODEN controls BOD function.
BOREN = NSLEEP | 0x3EFF | BOD enabled while running and disabled in Sleep. SBODEN bit disabled.
BOREN = ON | 0x3FFF | BOD enabled and SBOdEN bit disabled.
IESO -- Internal-External Switchover bit (bitmask:0x0400)
IESO = OFF | 0x3BFF | Internal External Switchover mode disabled.
IESO = ON | 0x3FFF | Internal External Switchover mode enabled.
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x0800)
FCMEN = OFF | 0x37FF | Fail-Safe Clock Monitor disabled.
FCMEN = ON | 0x3FFF | Fail-Safe Clock Monitor enabled.
WURE -- Wake-Up Reset Enable bit (bitmask:0x1000)
WURE = ON | 0x2FFF | Wake-up and Reset enabled.
WURE = OFF | 0x3FFF | Standard wake-up and continue enabled.

This page generated automatically by the device-help.pl program (2014-09-27 07:53:45 UTC) from the 8bit_device.info file (rev: 1.21) of mpasmx and from the gputils source package (rev: svn 1103). The mpasmx is included in the MPLAB X.