PIC16F570
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC16F570
CONFIG (address:0x0FFF, mask:0x03DF, default:0x03DF)
FOSC -- Oscillator (bitmask:0x0007)
FOSC = LP | 0x0FF8 | LP oscillator and 18 ms DRT.
FOSC = XT | 0x0FF9 | XT oscillator and 18 ms DRT.
FOSC = HS | 0x0FFA | HS oscillator and 18 ms DRT.
FOSC = EC | 0x0FFB | EC oscillator with I/O function on OSC2/CLKOUT.
FOSC = INTRC_IO | 0x0FFC | INTRC with I/O function on OSC2/CLKOUT.
FOSC = INTRC_CLKOUT | 0x0FFD | INTRC with CLKOUT function on OSC2/CLKOUT.
FOSC = EXTRC_IO | 0x0FFE | EXTRC with I/O function on OSC2/CLKOUT.
FOSC = EXTRC_CLKOUT | 0x0FFF | EXTRC with CLKOUT function on OSC2/CLKOUT.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0008)
WDTE = OFF | 0x0FF7 | Disabled.
WDTE = ON | 0x0FFF | Enabled.
CP -- Code Protection bit (bitmask:0x0010)
CP = ON | 0x0FEF | Code protection on.
CP = OFF | 0x0FFF | Code protection off.
IOSCFS -- Internal Oscillator Frequency Select (bitmask:0x0040)
IOSCFS = 4MHz | 0x0FBF | 4 MHz INTOSC Speed.
IOSCFS = 8MHz | 0x0FFF | 8 MHz INTOSC Speed.
CPSW -- Code Protection bit - Flash Data Memory (bitmask:0x0080)
CPSW = ON | 0x0F7F | Code protection on.
CPSW = OFF | 0x0FFF | Code protection off.
BOREN (bitmask:0x0100)
BOREN = OFF | 0x0EFF | BOR Disabled.
BOREN = ON | 0x0FFF | BOR Enabled.
DRTEN (bitmask:0x0200)
DRTEN = OFF | 0x0DFF | DRT Disabled.
DRTEN = ON | 0x0FFF | DRT Enabled.

This page generated automatically by the device-help.pl program (2014-09-27 07:53:45 UTC) from the 8bit_device.info file (rev: 1.21) of mpasmx and from the gputils source package (rev: svn 1103). The mpasmx is included in the MPLAB X.