/* SPDX-License-Identifier: GPL-2.0-or-later */
/**
  ******************************************************************************
  * @file  syscon_iopad_ctrl_macro.h
  * @author  StarFive Technology
  * @version  V1.0
  * @date  07/24/2020
  * @brief
  ******************************************************************************
  * @copy
  *
  * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
  *  COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  */

#ifndef _SYSCON_IOPAD_CTRL_MACRO_H_
#define _SYSCON_IOPAD_CTRL_MACRO_H_

//#define SYSCON_IOPAD_CTRL_BASE_ADDR 0x0
#define syscon_iopad_ctrl_register0_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x0
#define syscon_iopad_ctrl_register1_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x4
#define syscon_iopad_ctrl_register2_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x8
#define syscon_iopad_ctrl_register3_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC
#define syscon_iopad_ctrl_register4_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x10
#define syscon_iopad_ctrl_register5_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x14
#define syscon_iopad_ctrl_register6_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x18
#define syscon_iopad_ctrl_register7_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1C
#define syscon_iopad_ctrl_register8_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x20
#define syscon_iopad_ctrl_register9_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x24
#define syscon_iopad_ctrl_register10_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x28
#define syscon_iopad_ctrl_register11_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x2C
#define syscon_iopad_ctrl_register12_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x30
#define syscon_iopad_ctrl_register13_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x34
#define syscon_iopad_ctrl_register14_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x38
#define syscon_iopad_ctrl_register15_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x3C
#define syscon_iopad_ctrl_register16_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x40
#define syscon_iopad_ctrl_register17_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x44
#define syscon_iopad_ctrl_register18_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x48
#define syscon_iopad_ctrl_register19_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x4C
#define syscon_iopad_ctrl_register20_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x50
#define syscon_iopad_ctrl_register21_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x54
#define syscon_iopad_ctrl_register22_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x58
#define syscon_iopad_ctrl_register23_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x5C
#define syscon_iopad_ctrl_register24_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x60
#define syscon_iopad_ctrl_register25_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x64
#define syscon_iopad_ctrl_register26_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x68
#define syscon_iopad_ctrl_register27_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x6C
#define syscon_iopad_ctrl_register28_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x70
#define syscon_iopad_ctrl_register29_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x74
#define syscon_iopad_ctrl_register30_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x78
#define syscon_iopad_ctrl_register31_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x7C
#define syscon_iopad_ctrl_register32_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x80
#define syscon_iopad_ctrl_register33_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x84
#define syscon_iopad_ctrl_register34_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x88
#define syscon_iopad_ctrl_register35_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x8C
#define syscon_iopad_ctrl_register36_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x90
#define syscon_iopad_ctrl_register37_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x94
#define syscon_iopad_ctrl_register38_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x98
#define syscon_iopad_ctrl_register39_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x9C
#define syscon_iopad_ctrl_register40_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA0
#define syscon_iopad_ctrl_register41_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA4
#define syscon_iopad_ctrl_register42_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xA8
#define syscon_iopad_ctrl_register43_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xAC
#define syscon_iopad_ctrl_register44_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB0
#define syscon_iopad_ctrl_register45_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB4
#define syscon_iopad_ctrl_register46_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xB8
#define syscon_iopad_ctrl_register47_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xBC
#define syscon_iopad_ctrl_register48_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC0
#define syscon_iopad_ctrl_register49_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC4
#define syscon_iopad_ctrl_register50_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xC8
#define syscon_iopad_ctrl_register51_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xCC
#define syscon_iopad_ctrl_register52_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD0
#define syscon_iopad_ctrl_register53_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD4
#define syscon_iopad_ctrl_register54_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xD8
#define syscon_iopad_ctrl_register55_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xDC
#define syscon_iopad_ctrl_register56_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE0
#define syscon_iopad_ctrl_register57_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE4
#define syscon_iopad_ctrl_register58_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xE8
#define syscon_iopad_ctrl_register59_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xEC
#define syscon_iopad_ctrl_register60_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF0
#define syscon_iopad_ctrl_register61_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF4
#define syscon_iopad_ctrl_register62_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xF8
#define syscon_iopad_ctrl_register63_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0xFC
#define syscon_iopad_ctrl_register64_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x100
#define syscon_iopad_ctrl_register65_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x104
#define syscon_iopad_ctrl_register66_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x108
#define syscon_iopad_ctrl_register67_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x10C
#define syscon_iopad_ctrl_register68_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x110
#define syscon_iopad_ctrl_register69_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x114
#define syscon_iopad_ctrl_register70_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x118
#define syscon_iopad_ctrl_register71_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x11C
#define syscon_iopad_ctrl_register72_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x120
#define syscon_iopad_ctrl_register73_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x124
#define syscon_iopad_ctrl_register74_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x128
#define syscon_iopad_ctrl_register75_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x12C
#define syscon_iopad_ctrl_register76_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x130
#define syscon_iopad_ctrl_register77_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x134
#define syscon_iopad_ctrl_register78_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x138
#define syscon_iopad_ctrl_register79_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x13C
#define syscon_iopad_ctrl_register80_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x140
#define syscon_iopad_ctrl_register81_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x144
#define syscon_iopad_ctrl_register82_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x148
#define syscon_iopad_ctrl_register83_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x14C
#define syscon_iopad_ctrl_register84_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x150
#define syscon_iopad_ctrl_register85_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x154
#define syscon_iopad_ctrl_register86_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x158
#define syscon_iopad_ctrl_register87_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x15C
#define syscon_iopad_ctrl_register88_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x160
#define syscon_iopad_ctrl_register89_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x164
#define syscon_iopad_ctrl_register90_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x168
#define syscon_iopad_ctrl_register91_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x16C
#define syscon_iopad_ctrl_register92_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x170
#define syscon_iopad_ctrl_register93_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x174
#define syscon_iopad_ctrl_register94_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x178
#define syscon_iopad_ctrl_register95_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x17C
#define syscon_iopad_ctrl_register96_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x180
#define syscon_iopad_ctrl_register97_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x184
#define syscon_iopad_ctrl_register98_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x188
#define syscon_iopad_ctrl_register99_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x18C
#define syscon_iopad_ctrl_register100_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x190
#define syscon_iopad_ctrl_register101_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x194
#define syscon_iopad_ctrl_register102_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x198
#define syscon_iopad_ctrl_register103_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x19C
#define syscon_iopad_ctrl_register104_REG_ADDR  SYSCON_IOPAD_CTRL_BASE_ADDR + 0x1A0

#define _SET_SYSCON_REG_register0_SCFG_gpio_pad_ctrl_0(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register0_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register0_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register0_SCFG_gpio_pad_ctrl_0(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register0_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register1_SCFG_gpio_pad_ctrl_1(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register1_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register1_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register1_SCFG_gpio_pad_ctrl_1(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register1_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register2_SCFG_gpio_pad_ctrl_2(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register2_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register2_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register2_SCFG_gpio_pad_ctrl_2(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register2_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register3_SCFG_gpio_pad_ctrl_3(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register3_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register3_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register3_SCFG_gpio_pad_ctrl_3(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register3_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register4_SCFG_gpio_pad_ctrl_4(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register4_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register4_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register4_SCFG_gpio_pad_ctrl_4(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register4_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register5_SCFG_gpio_pad_ctrl_5(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register5_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register5_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register5_SCFG_gpio_pad_ctrl_5(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register5_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register6_SCFG_gpio_pad_ctrl_6(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register6_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register6_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register6_SCFG_gpio_pad_ctrl_6(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register6_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register7_SCFG_gpio_pad_ctrl_7(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register7_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register7_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register7_SCFG_gpio_pad_ctrl_7(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register7_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register8_SCFG_gpio_pad_ctrl_8(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register8_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register8_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register8_SCFG_gpio_pad_ctrl_8(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register8_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register9_SCFG_gpio_pad_ctrl_9(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register9_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register9_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register9_SCFG_gpio_pad_ctrl_9(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register9_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register10_SCFG_gpio_pad_ctrl_10(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register10_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register10_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register10_SCFG_gpio_pad_ctrl_10(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register10_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register11_SCFG_gpio_pad_ctrl_11(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register11_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register11_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register11_SCFG_gpio_pad_ctrl_11(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register11_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register12_SCFG_gpio_pad_ctrl_12(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register12_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register12_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register12_SCFG_gpio_pad_ctrl_12(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register12_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register13_SCFG_gpio_pad_ctrl_13(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register13_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register13_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register13_SCFG_gpio_pad_ctrl_13(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register13_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register14_SCFG_gpio_pad_ctrl_14(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register14_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register14_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register14_SCFG_gpio_pad_ctrl_14(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register14_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register15_SCFG_gpio_pad_ctrl_15(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register15_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register15_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register15_SCFG_gpio_pad_ctrl_15(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register15_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register16_SCFG_gpio_pad_ctrl_16(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register16_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register16_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register16_SCFG_gpio_pad_ctrl_16(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register16_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register17_SCFG_gpio_pad_ctrl_17(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register17_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register17_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register17_SCFG_gpio_pad_ctrl_17(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register17_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register18_SCFG_gpio_pad_ctrl_18(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register18_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register18_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register18_SCFG_gpio_pad_ctrl_18(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register18_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register19_SCFG_gpio_pad_ctrl_19(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register19_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register19_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register19_SCFG_gpio_pad_ctrl_19(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register19_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register20_SCFG_gpio_pad_ctrl_20(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register20_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register20_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register20_SCFG_gpio_pad_ctrl_20(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register20_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register21_SCFG_gpio_pad_ctrl_21(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register21_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register21_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register21_SCFG_gpio_pad_ctrl_21(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register21_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register22_SCFG_gpio_pad_ctrl_22(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register22_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register22_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register22_SCFG_gpio_pad_ctrl_22(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register22_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register23_SCFG_gpio_pad_ctrl_23(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register23_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register23_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register23_SCFG_gpio_pad_ctrl_23(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register23_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register24_SCFG_gpio_pad_ctrl_24(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register24_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register24_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register24_SCFG_gpio_pad_ctrl_24(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register24_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register25_SCFG_gpio_pad_ctrl_25(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register25_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register25_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register25_SCFG_gpio_pad_ctrl_25(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register25_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register26_SCFG_gpio_pad_ctrl_26(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register26_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register26_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register26_SCFG_gpio_pad_ctrl_26(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register26_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register27_SCFG_gpio_pad_ctrl_27(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register27_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register27_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register27_SCFG_gpio_pad_ctrl_27(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register27_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register28_SCFG_gpio_pad_ctrl_28(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register28_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register28_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register28_SCFG_gpio_pad_ctrl_28(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register28_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register29_SCFG_gpio_pad_ctrl_29(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register29_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register29_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register29_SCFG_gpio_pad_ctrl_29(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register29_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register30_SCFG_gpio_pad_ctrl_30(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register30_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register30_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register30_SCFG_gpio_pad_ctrl_30(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register30_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register31_SCFG_gpio_pad_ctrl_31(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register31_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register31_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register31_SCFG_gpio_pad_ctrl_31(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register31_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register32_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register32_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register32_SCFG_funcshare_pad_ctrl_0(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register32_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register33_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register33_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register33_SCFG_funcshare_pad_ctrl_1(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register33_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register34_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register34_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register34_SCFG_funcshare_pad_ctrl_2(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register34_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register35_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register35_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register35_SCFG_funcshare_pad_ctrl_3(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register35_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register36_SCFG_funcshare_pad_ctrl_4(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register36_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register36_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register36_SCFG_funcshare_pad_ctrl_4(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register36_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register37_SCFG_funcshare_pad_ctrl_5(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register37_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register37_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register37_SCFG_funcshare_pad_ctrl_5(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register37_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register38_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register38_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register38_SCFG_funcshare_pad_ctrl_6(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register38_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register39_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register39_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register39_SCFG_funcshare_pad_ctrl_7(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register39_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register40_SCFG_funcshare_pad_ctrl_8(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register40_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register40_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register40_SCFG_funcshare_pad_ctrl_8(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register40_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register41_SCFG_funcshare_pad_ctrl_9(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register41_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register41_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register41_SCFG_funcshare_pad_ctrl_9(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register41_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register42_SCFG_funcshare_pad_ctrl_10(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register42_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register42_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register42_SCFG_funcshare_pad_ctrl_10(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register42_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register43_SCFG_funcshare_pad_ctrl_11(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register43_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register43_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register43_SCFG_funcshare_pad_ctrl_11(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register43_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register44_SCFG_funcshare_pad_ctrl_12(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register44_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register44_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register44_SCFG_funcshare_pad_ctrl_12(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register44_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register45_SCFG_funcshare_pad_ctrl_13(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register45_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register45_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register45_SCFG_funcshare_pad_ctrl_13(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register45_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register46_SCFG_funcshare_pad_ctrl_14(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register46_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register46_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register46_SCFG_funcshare_pad_ctrl_14(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register46_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register47_SCFG_funcshare_pad_ctrl_15(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register47_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register47_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register47_SCFG_funcshare_pad_ctrl_15(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register47_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register48_SCFG_funcshare_pad_ctrl_16(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register48_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register48_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register48_SCFG_funcshare_pad_ctrl_16(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register48_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register49_SCFG_funcshare_pad_ctrl_17(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register49_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register49_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register49_SCFG_funcshare_pad_ctrl_17(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register49_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register50_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register50_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register50_SCFG_funcshare_pad_ctrl_18(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register50_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register51_SCFG_funcshare_pad_ctrl_19(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register51_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register51_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register51_SCFG_funcshare_pad_ctrl_19(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register51_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register52_SCFG_funcshare_pad_ctrl_20(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register52_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register52_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register52_SCFG_funcshare_pad_ctrl_20(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register52_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register53_SCFG_funcshare_pad_ctrl_21(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register53_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register53_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register53_SCFG_funcshare_pad_ctrl_21(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register53_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register54_SCFG_funcshare_pad_ctrl_22(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register54_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register54_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register54_SCFG_funcshare_pad_ctrl_22(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register54_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register55_SCFG_funcshare_pad_ctrl_23(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register55_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register55_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register55_SCFG_funcshare_pad_ctrl_23(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register55_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register56_SCFG_funcshare_pad_ctrl_24(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register56_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register56_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register56_SCFG_funcshare_pad_ctrl_24(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register56_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register57_SCFG_funcshare_pad_ctrl_25(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register57_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register57_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register57_SCFG_funcshare_pad_ctrl_25(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register57_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register58_SCFG_funcshare_pad_ctrl_26(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register58_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register58_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register58_SCFG_funcshare_pad_ctrl_26(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register58_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register59_SCFG_funcshare_pad_ctrl_27(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register59_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register59_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register59_SCFG_funcshare_pad_ctrl_27(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register59_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register60_SCFG_funcshare_pad_ctrl_28(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register60_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register60_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register60_SCFG_funcshare_pad_ctrl_28(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register60_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register61_SCFG_funcshare_pad_ctrl_29(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register61_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register61_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register61_SCFG_funcshare_pad_ctrl_29(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register61_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register62_SCFG_funcshare_pad_ctrl_30(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register62_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register62_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register62_SCFG_funcshare_pad_ctrl_30(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register62_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register63_SCFG_funcshare_pad_ctrl_31(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register63_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register63_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register63_SCFG_funcshare_pad_ctrl_31(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register63_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register64_SCFG_funcshare_pad_ctrl_32(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register64_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register64_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register64_SCFG_funcshare_pad_ctrl_32(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register64_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register65_SCFG_funcshare_pad_ctrl_33(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register65_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register65_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register65_SCFG_funcshare_pad_ctrl_33(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register65_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register66_SCFG_funcshare_pad_ctrl_34(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register66_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register66_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register66_SCFG_funcshare_pad_ctrl_34(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register66_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register67_SCFG_funcshare_pad_ctrl_35(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register67_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register67_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register67_SCFG_funcshare_pad_ctrl_35(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register67_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register68_SCFG_funcshare_pad_ctrl_36(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register68_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register68_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register68_SCFG_funcshare_pad_ctrl_36(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register68_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register69_SCFG_funcshare_pad_ctrl_37(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register69_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register69_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register69_SCFG_funcshare_pad_ctrl_37(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register69_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register70_SCFG_funcshare_pad_ctrl_38(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register70_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register70_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register70_SCFG_funcshare_pad_ctrl_38(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register70_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register71_SCFG_funcshare_pad_ctrl_39(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register71_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register71_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register71_SCFG_funcshare_pad_ctrl_39(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register71_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register72_SCFG_funcshare_pad_ctrl_40(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register72_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register72_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register72_SCFG_funcshare_pad_ctrl_40(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register72_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register73_SCFG_funcshare_pad_ctrl_41(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register73_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register73_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register73_SCFG_funcshare_pad_ctrl_41(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register73_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register74_SCFG_funcshare_pad_ctrl_42(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register74_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register74_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register74_SCFG_funcshare_pad_ctrl_42(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register74_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register75_SCFG_funcshare_pad_ctrl_43(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register75_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register75_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register75_SCFG_funcshare_pad_ctrl_43(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register75_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register76_SCFG_funcshare_pad_ctrl_44(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register76_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register76_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register76_SCFG_funcshare_pad_ctrl_44(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register76_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register77_SCFG_funcshare_pad_ctrl_45(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register77_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register77_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register77_SCFG_funcshare_pad_ctrl_45(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register77_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register78_SCFG_funcshare_pad_ctrl_46(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register78_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register78_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register78_SCFG_funcshare_pad_ctrl_46(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register78_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register79_SCFG_funcshare_pad_ctrl_47(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register79_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register79_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register79_SCFG_funcshare_pad_ctrl_47(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register79_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register80_SCFG_funcshare_pad_ctrl_48(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register80_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register80_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register80_SCFG_funcshare_pad_ctrl_48(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register80_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register81_SCFG_funcshare_pad_ctrl_49(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register81_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register81_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register81_SCFG_funcshare_pad_ctrl_49(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register81_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register82_SCFG_funcshare_pad_ctrl_50(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register82_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register82_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register82_SCFG_funcshare_pad_ctrl_50(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register82_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register83_SCFG_funcshare_pad_ctrl_51(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register83_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register83_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register83_SCFG_funcshare_pad_ctrl_51(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register83_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register84_SCFG_funcshare_pad_ctrl_52(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register84_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register84_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register84_SCFG_funcshare_pad_ctrl_52(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register84_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register85_SCFG_funcshare_pad_ctrl_53(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register85_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register85_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register85_SCFG_funcshare_pad_ctrl_53(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register85_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register86_SCFG_funcshare_pad_ctrl_54(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register86_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register86_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register86_SCFG_funcshare_pad_ctrl_54(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register86_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register87_SCFG_funcshare_pad_ctrl_55(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register87_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register87_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register87_SCFG_funcshare_pad_ctrl_55(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register87_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register88_SCFG_funcshare_pad_ctrl_56(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register88_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register88_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register88_SCFG_funcshare_pad_ctrl_56(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register88_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register89_SCFG_funcshare_pad_ctrl_57(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register89_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register89_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register89_SCFG_funcshare_pad_ctrl_57(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register89_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register90_SCFG_funcshare_pad_ctrl_58(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register90_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register90_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register90_SCFG_funcshare_pad_ctrl_58(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register90_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register91_SCFG_funcshare_pad_ctrl_59(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register91_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register91_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register91_SCFG_funcshare_pad_ctrl_59(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register91_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register92_SCFG_funcshare_pad_ctrl_60(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register92_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register92_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register92_SCFG_funcshare_pad_ctrl_60(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register92_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register93_SCFG_funcshare_pad_ctrl_61(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register93_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register93_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register93_SCFG_funcshare_pad_ctrl_61(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register93_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register94_SCFG_funcshare_pad_ctrl_62(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register94_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register94_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register94_SCFG_funcshare_pad_ctrl_62(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register94_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register95_SCFG_funcshare_pad_ctrl_63(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register95_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register95_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register95_SCFG_funcshare_pad_ctrl_63(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register95_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register96_SCFG_funcshare_pad_ctrl_64(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register96_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register96_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register96_SCFG_funcshare_pad_ctrl_64(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register96_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register97_SCFG_funcshare_pad_ctrl_65(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register97_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register97_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register97_SCFG_funcshare_pad_ctrl_65(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register97_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register98_SCFG_funcshare_pad_ctrl_66(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register98_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register98_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register98_SCFG_funcshare_pad_ctrl_66(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register98_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register99_SCFG_funcshare_pad_ctrl_67(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register99_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register99_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register99_SCFG_funcshare_pad_ctrl_67(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register99_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register100_SCFG_funcshare_pad_ctrl_68(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register100_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register100_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register100_SCFG_funcshare_pad_ctrl_68(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register100_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register101_SCFG_funcshare_pad_ctrl_69(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register101_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register101_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register101_SCFG_funcshare_pad_ctrl_69(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register101_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register102_SCFG_funcshare_pad_ctrl_70(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register102_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0xFFFFFFFF); \
	_ezchip_macro_read_value_ |= (v&0xFFFFFFFF); \
	MA_OUTW(syscon_iopad_ctrl_register102_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register102_SCFG_funcshare_pad_ctrl_70(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register102_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0xFFFFFFFF;\
}

#define _SET_SYSCON_REG_register103_SCFG_qspi_ioctrl(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register103_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0x7F); \
	_ezchip_macro_read_value_ |= (v&0x7F); \
	MA_OUTW(syscon_iopad_ctrl_register103_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register103_SCFG_qspi_ioctrl(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register103_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0x7f;\
}

#define _SET_SYSCON_REG_register104_SCFG_io_padshare_sel(v) { \
	uint32_t _ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register104_REG_ADDR); \
	_ezchip_macro_read_value_ &= ~(0x7); \
	_ezchip_macro_read_value_ |= (v&0x7); \
	MA_OUTW(syscon_iopad_ctrl_register104_REG_ADDR,_ezchip_macro_read_value_); \
}

#define _GET_SYSCON_REG_register104_SCFG_io_padshare_sel(_ezchip_macro_read_value_) { \
	_ezchip_macro_read_value_=MA_INW(syscon_iopad_ctrl_register104_REG_ADDR); \
	_ezchip_macro_read_value_ &= 0x7;\
}

#endif //_SYSCON_IOPAD_CTRL_MACRO_H_
