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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
fifo_xlnx_64x36_2clk YourInstanceName (
	.din(din), // Bus [35 : 0] 
	.rd_clk(rd_clk),
	.rd_en(rd_en),
	.rst(rst),
	.wr_clk(wr_clk),
	.wr_en(wr_en),
	.dout(dout), // Bus [35 : 0] 
	.empty(empty),
	.full(full),
	.rd_data_count(rd_data_count), // Bus [6 : 0] 
	.wr_data_count(wr_data_count)); // Bus [6 : 0] 

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating
// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

