fir_compiler_v6_3_vinfo

    CHANGE LOG for Xilinx LogiCORE FIR Compiler 6.3

    Release Date:  December 18, 2012
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    Table of Contents

    1.   INTRODUCTION
    2.   DEVICE SUPPORT
    3.   NEW FEATURE HISTORY
    4.   RESOLVED ISSUES
    5.   KNOWN ISSUES & LIMITATIONS
    6.   TECHNICAL SUPPORT & FEEDBACK
    7.   CORE RELEASE HISTORY
    8.   LEGAL DISCLAIMER

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    1. INTRODUCTION

      This file contains the change log for all released versions of the Xilinx
      LogiCORE IP FIR Compiler.

      For the latest core updates, see the product page at:

        www.xilinx.com/products/ipcenter/FIR_Compiler.htm

      For installation instructions for this release, please go to:

        www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

      For system requirements:

        www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

    2. DEVICE SUPPORT

      2.1. ISE

        The following device families are supported by the core for this release:

        All Series 7 devices
        All Virtex-6 devices
        All Spartan-6 devices

      2.2. VIVADO

        The following device families are supported by the core for this release:

        All Series 7 devices

    3. NEW FEATURE HISTORY

      3.1 ISE

      v6.3
        - Ongoing new device support.
        - Advanced Interleaved Channels (Configurable Bandwidth support)
        - Multi-column support for symmetric filter implementations
        - Re-introduction of Hilbert Transform, Single Rate Half-Band and Interpolated filters
        - C Model added

      3.1 VIVADO

      v6.3
        - Introduction to Vivado.
        - Same features as for ISE.

    4. RESOLVED ISSUES

      4.1 ISE

        - FIR Compiler v6.x - GUI may crash when Maximize_Dynamic_Range is selected
          - CR 627620

        - FIR Compiler v6.x - Reload port allows boolean type in System Generator
          - CR 640607

        - FIR Compiler v6.x - Custom column lengths ignored in System Generator for some core configurations
          - CR 630639

        - FIR Compiler v6.x - Latency information in the GUI doesn't match the core
          - AR 40200
          - CR 591161

        - FIR Compiler v6.x : Multi-column filters will not map/place
          - AR 40769
          - CR 594220

        - FIR Compiler v6.2 - The output for a Fractional Rate is in bursts rather than at regular intervals
          - AR 41707
          - CR 605099

        - FIR Compiler v6.x : Event I/F mismatches between model and core
          - AR 42305
          - CR 592301

        - FIR Compiler v6.2 - Multi-Channel core data comes out on the wrong channel
          - The output shift channels when using a multi-channel, interpolate by 2, odd number of symetrical coefficients,
            with oversample rate of 3 with Block RAM selected for memory implementation
          - AR 42727
          - CR 614460
          - N/A

      4.2 Vivado

        - N/A

    5. KNOWN ISSUES & LIMITATIONS

      The following are known issues for this core at time of release:

      5.1 ISE
        1. Unsupported v5.0 features - The following features are not supported by v6.3:
          - Distributed Arithmetic
          - Polyphase filter bank

        2. Memory collision errors - Netlist or UniSim structural model simulation may
            report Block RAM memory collision errors. These errors are issued by the Block RAM
            primitive when a write occurs and the read and write addresses match. However, a
            read or write event is qualified by read enable or write enable respectively.
            In operation, read and write events never occur to the same address at the same
            time so functionality is not affected by these apparent collisions.

      5.2 Vivado
        1. As per 1. above for ISE.

        2. Core may fail to compile in XSIM.
         - CR667417
         - AR50922

      For a comprehensive listing of Known Issues for this core, please see the IP
      Release Notes Guide,

        www.xilinx.com/support/documentation/user_guides/xtp025.pdf

    6. TECHNICAL SUPPORT & FEEDBACK

      To obtain technical support, create a WebCase at www.xilinx.com/support.
      Questions are routed to a team with expertise using this product.
      Please feel free to leave feedback on this IP under the "Leave Feedback"
      menu item in Vivado/PlanAhead.

      Xilinx provides technical support for use of this product when used
      according to the guidelines described in the core documentation, and
      cannot guarantee timing, functionality, or support of this product for
      designs that do not follow specified guidelines.

    7. CORE RELEASE HISTORY

    Date        By            Version      Description
    ================================================================================
    12/18/2012  Xilinx, Inc.  6.3          ISE 14.4 and Vivado 2012.4 support
    10/16/2012  Xilinx, Inc.  6.3          ISE 14.3 and Vivado 2012.3 support
    07/25/2012  Xilinx, Inc.  6.3          ISE 14.2 and Vivado 2012.2 support
    04/24/2012  Xilinx, Inc.  6.3          ISE 14.1 and Vivado 2012.1 support
    01/11/2012  Xilinx, Inc.  6.3          ISE 13.4 support
    10/19/2011  Xilinx, Inc.  6.3          ISE 13.3 support.
    06/22/2011  Xilinx, Inc.  6.2          ISE 13.2 support, Artix-7 support
    03/01/2011  Xilinx, Inc.  6.2          IDS 13.1 support.
    12/14/2010  Xilinx, Inc.  6.1          IDS 12.4 support.
    09/21/2010  Xilinx, Inc.  6.0          IDS 12.3 support. AXI4-Stream Interfaces
    12/02/2009  Xilinx, Inc.  5.0          11.4 support, Spartan-6L support
                                           and Automotive Spartan6 support
    09/16/2009  Xilinx, Inc.  5.0          11.3 support, Virtex-6L support
    06/24/2009  Xilinx, Inc.  5.0          11.2 support, Virtex-6 and Spartan-6 support
    05/30/2008  Xilinx, Inc.  4.0          Scheduled Release
    10/10/2007  Xilinx, Inc.  3.2          Patch Release
    ================================================================================

    8. LEGAL DISCLAIMER

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