CHANGE LOG for Xilinx LogiCORE Divider Generator 4.0

Release Date:  June 19, 2013 
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Table of Contents

1.   INTRODUCTION 
2.   DEVICE SUPPORT    
3.   NEW FEATURE HISTORY   
4.   RESOLVED ISSUES 
5.   KNOWN ISSUES & LIMITATIONS 
6.   TECHNICAL SUPPORT & FEEDBACK 
7.   CORE RELEASE HISTORY 
8.   LEGAL DISCLAIMER 

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1. INTRODUCTION

  This file contains the change log for all released versions of the Xilinx 
  LogiCORE IP Divider Generator. 

  For the latest core updates, see the product page at:

    http://www.xilinx.com/products/ipcenter/Divider.htm

  For installation instructions for this release, please go to:

    http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

  For system requirements:

    http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm


2. DEVICE SUPPORT 

  2.1. ISE

    The following device families are supported by the core for this release:

    All Series 7 devices
    All Virtex-6 devices
    All Spartan-6 devices


3. NEW FEATURE HISTORY

  3.1 ISE
 
  v4.0
    - Ongoing new device support.
    - AXI-4 Stream Interfaces replace old pinout
    - Maximum operand and output widths increased to 64 bits. 


4. RESOLVED ISSUES 

  4.1 ISE

    - N/A


5. KNOWN ISSUES & LIMITATIONS 

  The following are known issues for this core at time of release:

  5.1 ISE
    - None

  - For a comprehensive listing of Known Issues for this core, please see the IP 
    Release Notes Guide,  
    
    www.xilinx.com/support/documentation/user_guides/xtp025.pdf


6. TECHNICAL SUPPORT & FEEDBACK

  To obtain technical support, create a WebCase at www.xilinx.com/support.
  Questions are routed to a team with expertise using this product.
  Please feel free to leave feedback on this IP under the "Leave Feedback"
  menu item in Vivado/PlanAhead.

  Xilinx provides technical support for use of this product when used
  according to the guidelines described in the core documentation, and
  cannot guarantee timing, functionality, or support of this product for
  designs that do not follow specified guidelines.


7. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
06/19/2012  Xilinx, Inc.  4.0          ISE 14.6 support
03/20/2012  Xilinx, Inc.  4.0          ISE 14.5 support. 
12/18/2012  Xilinx, Inc.  4.0          ISE 14.4 and Vivado 2012.4 support
10/16/2012  Xilinx, Inc.  4.0          ISE 14.3 and Vivado 2012.3 support
07/25/2012  Xilinx, Inc.  4.0          ISE 14.2 and Vivado 2012.2 support
04/24/2012  Xilinx, Inc.  4.0          ISE 14.1 and Vivado 2012.1 support
01/11/2012  Xilinx, Inc.  4.0          ISE 13.4 support
10/19/2011  Xilinx, Inc.  4.0          ISE 13.3 support, Artix-7 support
06/22/2011  Xilinx, Inc   4.0          13.2 support, Virtex7, Kintex7, Virtex7 
                                       Low Power and Kintex7 Low Power Support
                                       AXI4-Stream interfaces, 64 bit width support.
12/02/2009  Xilinx, Inc.  3.0          11.4 support, Spartan-6L support
                                       and Automotive Spartan6 support
09/16/2009  Xilinx, Inc.  3.0          11.3 support, Virtex-6L support
06/24/2009  Xilinx, Inc.  3.0          11.2 support
04/25/2008  Xilinx, Inc.  2.0          10.1i support
01/18/2006  Xilinx, Inc.  1.0          Introduction
================================================================================


8. LEGAL DISCLAIMER

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