// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 2016 Xilinx Inc. All rights reserved.
// 
// ==============================================================

// control
// 0x00 : Control signals
//        bit 0  - ap_start (Read/Write/COH)
//        bit 1  - ap_done (Read/COR)
//        bit 2  - ap_idle (Read)
//        bit 3  - ap_ready (Read)
//        bit 7  - auto_restart (Read/Write)
//        others - reserved
// 0x04 : Global Interrupt Enable Register
//        bit 0  - Global Interrupt Enable (Read/Write)
//        others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
//        bit 0  - Channel 0 (ap_done)
//        bit 1  - Channel 1 (ap_ready)
//        others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
//        bit 0  - Channel 0 (ap_done)
//        bit 1  - Channel 1 (ap_ready)
//        others - reserved
// 0x10 : Data signal of a
//        bit 31~0 - a[31:0] (Read/Write)
// 0x14 : Data signal of a
//        bit 31~0 - a[63:32] (Read/Write)
// 0x18 : reserved
// 0x1c : Data signal of b
//        bit 31~0 - b[31:0] (Read/Write)
// 0x20 : Data signal of b
//        bit 31~0 - b[63:32] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of elements
//        bit 31~0 - elements[31:0] (Read/Write)
// 0x2c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

#define XADDONE_CONTROL_ADDR_AP_CTRL       0x00
#define XADDONE_CONTROL_ADDR_GIE           0x04
#define XADDONE_CONTROL_ADDR_IER           0x08
#define XADDONE_CONTROL_ADDR_ISR           0x0c
#define XADDONE_CONTROL_ADDR_A_DATA        0x10
#define XADDONE_CONTROL_BITS_A_DATA        64
#define XADDONE_CONTROL_ADDR_B_DATA        0x1c
#define XADDONE_CONTROL_BITS_B_DATA        64
#define XADDONE_CONTROL_ADDR_ELEMENTS_DATA 0x28
#define XADDONE_CONTROL_BITS_ELEMENTS_DATA 32

