[^:]*: Assembler messages:
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block
[^:]*:12: Error: bad type in SIMD instruction -- `vmlalv.s64 r0,r1,q1,q2'
[^:]*:13: Error: bad type in SIMD instruction -- `vmlalv.f32 r0,r1,q1,q2'
[^:]*:14: Error: bad type in SIMD instruction -- `vmlalv.s8 r0,r1,q1,q2'
[^:]*:15: Error: ARM register expected -- `vmlalv.s16 r0,q1,q2'
[^:]*:16: Error: bad type in SIMD instruction -- `vmlalva.s64 r0,r1,q1,q2'
[^:]*:17: Error: bad type in SIMD instruction -- `vmlalva.f32 r0,r1,q1,q2'
[^:]*:18: Error: bad type in SIMD instruction -- `vmlalva.s8 r0,r1,q1,q2'
[^:]*:19: Error: ARM register expected -- `vmlalva.s16 r0,q1,q2'
[^:]*:20: Error: bad instruction `vmlalvx.s16 r0,r1,q1,q2'
[^:]*:21: Error: bad instruction `vmlalvax.s16 r0,r1,q1,q2'
[^:]*:23: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
[^:]*:24: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
[^:]*:25: Error: syntax error -- `vmlalveq.s16 r0,r1,q1,q2'
[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vmlalvt.s16 r0,r1,q1,q2'
[^:]*:28: Error: instruction missing MVE vector predication code -- `vmlalv.s16 r0,r1,q1,q2'
[^:]*:30: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
[^:]*:31: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
[^:]*:32: Error: syntax error -- `vmlalvaeq.s16 r0,r1,q1,q2'
[^:]*:33: Error: vector predicated instruction should be in VPT/VPST block -- `vmlalvat.s16 r0,r1,q1,q2'
[^:]*:35: Error: instruction missing MVE vector predication code -- `vmlalva.s16 r0,r1,q1,q2'
