The Bus arc of the Schematics technology is a special arc that can carry multiple signals (see Section 7-5-1). When giving a network name to Bus arcs, it is possible to specify complex bus names.

- Simple arrays Bus names can be arrays (for example, "A[0:7]" which defines an 8-wide bus). The indices can ascend or descend.
- Lists Bus names can be lists (for example, "clock,in1,out" which aggregates 3 signals into a 3-wide bus).
- Array index lists and ranges Arrayed bus names can have lists of values (separated by commas) or ranges of values (using the colon). For example, the bus "b[0],c[3,5],d[1:2],e[8:6]" is an 8-wide bus with signals in this order: b[0], c[3], c[5], d[1], d[2], e[8], e[7], e[6].
- Multidimensional array indices Arrays can be multiply indexed (for example "b[1:2][100,102]" defines a bus with 4 entries: b[1][100], b[1][102], b[2][100], and b[2][102]). You can have any number of dimensions in an array. Note that the order of signals in a multidimensional array is such that the rightmost index varies the fastest. For example, the bus "D[1:2][1:2]" has signals in this order: D[1][1], D[1][2], D[2][1], D[2][2].
- Symbolic array indices It is possible to use symbolic indices in bus naming (for example, the bus "r[x,y]" defines a 2-wide bus with the signals r[x] and r[y]).

When a bus is unnamed, the system determines its width from the ports that it connects. Some tools (such as simulation netlisters) need to name everything, and so use automatically-generated names. When this happens, the system must choose whether to number the bus ascending or descending. To resolve this issue, use the Network Preferences (in menu File / Preferences..., "Tools" section, "Network" tab), and choose "Ascending" or "Descending". (For information about the "Node Extraction" portion of the Network Preferences, see Section 9-10-2.)

Individual wires that connect to a bus must be named with names from that bus. As an aid in obtaining individual signals from a bus, the Rip Bus command (in menu Edit / Arc) will automatically create such wires for the selected bus arc.

To find out what signals are on a bus, select that bus and use the Object Properties... command (in the Edit / Properties menu). In the full dialog (obtained by clicking the "More" button), select "List Shows Bus Members" to see a list of networks on the selected bus arc. When a node's port is a bus, you can see the signals on that bus by selecting that port of the node and using the Object Properties... command. In the full dialog, select "Bus Members on Port" to see the signals.

#### Arrayed Nodes

Besides using array names on busses, you can also give array names to cell instances in a schematic. Netlisters will create multiple copies of that node, named with the individual elements of the array.

| When a cell instance is arrayed, the connections to its ports can be similarly arrayed. For example, suppose that schematic cell X has wire port Y and bus port Z[1:2]. An instance of cell X is arrayed by giving it the name M[2:4]. Ports Y and Z can be connected in two ways:

- Implicit connection to all instances (top illustration). If the wire port Y is connected to a single wire (A), then wire A connects to port Y on all three instances of cell X. If the bus port Z is connected to a 2-wide bus (B), then each element of that bus connects to the same element of bus port Z on all three instances of cell X. So B[1] connects to port Z[1] and B[2] connects to Z[2] on all three instances, M[2], M[3], and M[4].
- Explicit connection to individual instances (bottom illustration). If the wire port Y is connected to a 3-wide bus (C), then each element of the bus connects to port Y on a different instance of cell X. C[1] connects to Y on M[2]; C[2] connects to Y on M[3]; and C[3] connects to Y on M[4]. If the bus port Z is connected to a 6-wide bus (D), then it is viewed as 3 pairs of signals, and each pair connecting to the two-wide bus Z on a different instance of cell X. D[1] and D[2] connect to Z[1] and Z[2] on M[2]; D[3] and D[4] connect to Z[1] and Z[2] on M[3]; and D[5] and D[6] connect to Z[1] and Z[2] on M[4].

Note that it is not possible to array a primitive node from the Schematic technology. Instead, you must place that node inside of a cell, and array instances of the cell.

#### Parameterized Bus Names

It is possible to have variable-width busses by parameterizing their names. Electric maintains a list of global parameters, and these can be manipulated with the Edit Bus Parameters... command (in menu Edit / Properties). You can create and delete parameters, and can set values for each. |

To use these parameters, you must add a template to an arc, node, or export name.

| This figure shows an export called "in", and an arc called "internal". Both the export name and the arc name were selected, and the command Parameterize Bus Name issued (in menu Edit / Properties).

The templates are then shown near the original names. Arrayed nodes can also have their names parameterized.

You may type any text into the template. Wherever the string `$(par)` appears, it will be replaced with the parameter `par`. In this example, the parameter `x` has the value 7. You can also use simple arithmetic operators (just "+", "-", "*", and "/"), for example `in[0:$(x)-1]` defines a bus that runs from 0 to one minus the value of "x". When parameter values change, click the "Update All Templates" button to reevaluate all node, arc, and export names.