When editing one view of a cell, there are commands in the View menu that will switch to an alternate view of the same cell.

- Use Edit Layout View to switch to the layout view.
- Use Edit Schematic View to switch to the schematic view.
- Use Edit Icon View to switch to the Icon view.
- Use Edit VHDL View to switch to the VHDL view.
- Use Edit Documentation View to switch to the text-only documentation view.
- Use Edit Skeleton View to switch to the Skeleton view.

For all other view types, use Edit Other View... and select the desired view. Note that these commands are equivalent to the Edit Cell... command (in menu Cell) with an appropriate selection.

When editing cells with text-only views (VHDL, Documentation, etc.), the window becomes a text editor. You may then use the Text Cell Contents... commands (in menu File / Export and File / Import) to save and restore this text to disk. See Section 4-9 for more on text editing.

The commands to edit another view work only when that cell exists. To create a new cell of a particular type, use the Make... commands of the View menu. These view conversion commands are available:

- Make Icon View creates an icon from a schematic (see Section 3-11-4 for more on this).
- Make Schematic View creates a schematic from a layout.
- Make Alternate Layout View... converts from layout or schematic to an alternate layout. You must choose a specific layout technology, and the new layout will use components from that technology. You can also request that the converted layout be placed into a new library. This is useful if the conversion creates a hierarchy of cells in the new technology.
- Make Skeleton View makes a skeletonized layout from a layout (the only thing in the skeleton is the exports and the frame; it is a "layout icon").
- Make VHDL View converts the current layout or schematic into structural VHDL. This VHDL is used by the Silicon Compiler (see Section 9-12) and the ALS simulator (see Section 9-5-2). Note that there are 5 schematic primitives which can exist in a normal and negated form ("buffer", "and", "or", "xor", and "mux"). You can choose the names to use for these two forms in the "Schematics" section of the Technology Preferences (in menu File / Preferences..., "Technology" section, "Technology" tab).

There is also a way to convert from a hardware description language (VHDL or Verilog) to a circuit. To do this, use the Convert Current Cell to Rats-Nest Structure command (in menu Tools / Silicon Compiler). The resulting cell will be either a layout cell or a schematics cell (depending on the "Make Layout Cells (not Schematics)" setting in the "Verilog" preferences, see Section 9-4-2). See Section 9-12 for more on Silicon Compilation.