Writing libraries to disk is done with the Save Library command (in menu File). The Save All Libraries command writes all libraries that have changed.

| You can also use the save-libraries icon from the tool bar.

To force all libraries to be saved, use the Mark All Libraries for Saving command, or use Save All Libraries in Format... to specify how they are to be saved. If a library was read from disk, it is written back to the same file. If, however, you wish to write the library to a new file (thus preserving the original) then use the Save Library As... command. The Library Preferences (in menu File / Preferences..., "I/O" section, "Library" tab) offers options for writing libraries to disk. By default, saved libraries overwrite the previous files and no backup is created. If you choose "Backup of last library file", then the former library is renamed so that it has a "~" at the end. |

If you choose "Backup history of library files", then the former library is renamed so that it has its creation date as part of its name.

Electric can also write external format files with these commands in the File / Export menu:

- Bookshelf is an open format for specifying placement tasks.
- CIF (Caltech Intermediate Format) is used to describe integrated circuit layout. The output file contains only the current cell and any circuitry below that in the hierarchy. Use the CIF Preferences (in menu File / Preferences..., "I/O" section, "CIF" tab) to affect how CIF is written. See Section 7-3-2 for more on CIF.
- DFTM is a network interchange format for digital filters/transactional memory routers.
- DXF (AutoCAD) is a solid-modeling interchange format. Use the DXF Preferences (in menu File / Preferences..., "I/O" section, "DXF" tab) to affect how DXF is written. See Section 7-3-7 for more on DXF.
- Eagle is an interface to the Eagle schematics design system (its netlist format). Before writing Eagle files, you must give every node the "ref_des" attribute, and every port on these nodes the "pin" attribute. If you also place the "pkg_type" attribute on the node, it overrides the cell name.
- ECAD is an interface to the ECAD schematics design system (its netlist format). Before writing ECAD files, you must give every node the "ref_des" attribute, and every port on these nodes the "pin" attribute. If you also place the "pkg_type" attribute on the node, it overrides the cell name.
- EDIF (Electronic Design Interchange Format) can write either the Netlist or the Schematic view of the circuit. Electric writes EDIF version 2 0 0. Use the EDIF Preferences (in menu File / Preferences..., "I/O" section, "EDIF" tab) to affect how EDIF is written. See Section 7-3-4 for more on EDIF.
- ELIB (Version 6) writes old-format binary files. These files can be read by version 6 of Electric.
- GDS II (Stream) is also used to describe integrated circuit layout. The output file contains only the current cell and any circuitry below that in the hierarchy. Use the GDS Preferences (in menu File / Preferences..., "I/O" section, "GDS" tab) to affect how GDS is written. See Section 7-3-3 for more on GDS.
- Gerber is a printed-circuit board artwork format.
- HPGL is the Hewlett-Packard printing language. The output file contains only a visual representation of the current cell (or part of that cell).
- JELIB (Version 8.03) writes old-format JELIB files. These files are useful for versions 8.03 and earlier.
- L is the GDT language, still appearing in some commercial systems. The output file contains only the current cell and any circuitry below that in the hierarchy.
- LEF (Library Exchange Format) and DEF (Design Exchange Format) are interchange formats that describe a two-level layout. The lower level (the standard cells) are written to the LEF file. The top-level is written to the DEF file. If the hierarchy has more than two levels, then it is flattened and written all in the LEF file. See Section 7-3-5 for more on LEF and DEF.
- Pads is an interface to the Pads schematics design system (its netlist format). Before writing Pads files, you must give every node the "ref_des" attribute, and every port on these nodes the "pin" attribute. If you also place the "pkg_type" attribute on the node, it overrides the cell name.
- PNG (Portable Network Graphics) is an image format that captures the current window.
- PostScript is the Adobe printing language. The output file contains only a visual representation of the current cell (or part of that cell). PostScript options can be controlled with the Printing Preferences (in menu File / Preferences..., "General" section, "Printing" tab).
- Flattened Rectangles is a general format for writing flattened geometry as rectangles. Users are prompted for the format to use, with %l replaced by the rectangle layer, %x replaced by the X coordinate of the center of the rectangle, %y replaced by the Y coordinate of the center of the rectangle, %w replaced by the width of the rectangle, and %h replaced by the height of the rectangle.
- STL (Stereolithography) is a format for interfacing with "3D printing" machines.
- SVG is a web format (Scalable Vector Graphics) that captures the current window. See Section 7-3-10 for more on SVG.
- Telesis is an old netlist interface. Each cell in the circuit is saved to a separate Telesis file with the ".txt" extension.
- Text Cell Contents is used to write a text file from a text cell. The current window must be a textual view (such as VHDL, Verilog, documentation, etc.) See Section 4-9 for more on text windows.

The exported files from Electric are often considered to be proprietary information, and must be marked appropriately. Copyright information can be inserted into exported files with the Copyright Preferences (in menu File / Preferences..., "I/O" section, "Copyright" tab).

Since each export file has a different format for comments, the copyright text should not contain any such characters. Instead, the system will insert the proper comment characters for the particular export format.

The copyright information will be inserted into decks exported for CIF, LEF, and PostScript, as well as in simulation netlists for Verilog, Spice, Silos, ESIM/RSIM/RNL/COSMOS, FastHenry, Maxwell, and IRSIM.