/* * Copyright (C) 2011 - 2014 Xilinx * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>
    ;
    		};

    	};
    };