// Instruction handlers for the m68000 (direct, partial, cpu)
//
// Generated by m68000gen.py sdp m68000.lst m68000-sdp.cpp

#include "emu.h"
#include "m68000.h"

void m68000_device::state_reset_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 002 rstp3
	m_icount -= 2;
	// 296 rstp4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 27e rstp5
	debugger_exception_hook(0x00);
	m_ftu = 0x0000;
	m_icount -= 2;
	// 27f rstp6
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_sr |= 0x0700;
	update_interrupt();
	m_au = ext32(m_ftu);
	m_icount -= 2;
	// 2fb rstp7
	m_aob = m_au;
	set_16h(m_da[16], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2ff rstp8
	m_aob = m_au;
	set_16h(m_da[16], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 300 rstp9
	m_aob = m_au;
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	set_16l(m_da[16], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	if(m_next_state == S_TRACE)
		m_next_state = 0;
	// 11e rstpa
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::state_bus_error_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 003 bser1
	m_ssw = m_base_ssw | (m_sr & SR_S ? SSW_S : 0);
	m_at = m_aob;
	m_ftu = m_sr;
	m_au = m_pc;
	m_icount -= 2;
	// 3a7 bser2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	if(m_next_state == S_TRACE)
		m_next_state = 0;
	// 3ca bser3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0a2 bser4
	m_aob = m_au;
	m_dbout = m_aluo;
	m_ftu = m_ird;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3c6 bser5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 088 bser6
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_pc = m_at;
	m_ftu = (m_ftu & ~0x1f) | m_ssw;
	m_au = m_au - 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x02);
	m_da[16] = m_au;
	m_ftu = 0x0008;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::state_address_error_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 003 bser1
	m_ssw = m_base_ssw | (m_sr & SR_S ? SSW_S : 0);
	m_at = m_aob;
	m_ftu = m_sr;
	m_au = m_pc;
	m_icount -= 2;
	// 3a7 bser2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	if(m_next_state == S_TRACE)
		m_next_state = 0;
	// 3ca bser3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0a2 bser4
	m_aob = m_au;
	m_dbout = m_aluo;
	m_ftu = m_ird;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3c6 bser5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 088 bser6
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_pc = m_at;
	m_ftu = (m_ftu & ~0x1f) | m_ssw;
	m_au = m_au - 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x03);
	m_da[16] = m_au;
	m_ftu = 0x000c;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N | SSW_CRITICAL;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::state_double_fault_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 001 halt1
	m_icount = 0;
	}
}

void m68000_device::state_interrupt_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 1c4 itlx1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 234 itlx2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_alub = m_ftu;
	m_pc = m_au;
	m_sr = (m_sr & ~SR_I) | ((m_next_state >> 16) & SR_I);
	update_interrupt();
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_icount -= 2;
	// 235 itlx3
	m_ftu = 0xfff0 | ((m_next_state >> 23) & 0xe);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 0eb itlx4
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 236 itlx5
	m_aob = m_at;
	m_base_ssw = SSW_CPU | SSW_R | SSW_N;
	start_interrupt_vector_lookup();
	[[fallthrough]]; case 3:
	m_edb = m_cpu_space.read_interruptible(m_aob);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	end_interrupt_vector_lookup();
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 118 itlx6
	m_ir = m_irc;
	m_icount -= 2;
	// 292 itlx7
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook((m_int_vector) >> 2);
	m_da[16] = m_au;
	m_ftu = m_int_vector;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::state_trace_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 1c0 trac1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 3a3 trac2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	if(m_next_state == S_TRACE)
		m_next_state = 0;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x09);
	m_da[16] = m_au;
	m_ftu = 0x0024;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::state_illegal_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 1c0 trac1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 3a3 trac2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	if(m_next_state == S_TRACE)
		m_next_state = 0;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x04);
	m_da[16] = m_au;
	m_ftu = 0x0010;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::state_priviledge_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 1c0 trac1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 3a3 trac2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	if(m_next_state == S_TRACE)
		m_next_state = 0;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x08);
	m_da[16] = m_au;
	m_ftu = 0x0020;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::state_linea_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 1c0 trac1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 3a3 trac2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	if(m_next_state == S_TRACE)
		m_next_state = 0;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x0a);
	m_da[16] = m_au;
	m_ftu = 0x0028;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::state_linef_dp()
{
	switch(m_inst_substate) {
	case 0:
	// 1c0 trac1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 3a3 trac2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	if(m_next_state == S_TRACE)
		m_next_state = 0;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x0b);
	m_da[16] = m_au;
	m_ftu = 0x002c;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_N;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R | SSW_N;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R | SSW_N;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_b_imm8_ds_dp() // 0000 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_or8(m_dt, m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_b_imm8_ais_dp() // 0010 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_b_imm8_aips_dp() // 0018 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_b_imm8_pais_dp() // 0020 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_b_imm8_das_dp() // 0028 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_b_imm8_dais_dp() // 0030 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_b_imm8_adr16_dp() // 0038 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_b_imm8_adr32_dp() // 0039 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_imm8_ccr_dp() // 003c ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1cc stiw1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_icount -= 2;
	// 307 stiw2
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dtl:m_dt
	alu_or8(m_ftu, m_dt);
	m_icount -= 2;
	// 320 stiw3
	m_movemr = m_dbin;
	m_ftu = m_aluo;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_w_imm16_ds_dp() // 0040 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_or(m_dt, m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_w_imm16_ais_dp() // 0050 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_w_imm16_aips_dp() // 0058 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_w_imm16_pais_dp() // 0060 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_w_imm16_das_dp() // 0068 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_w_imm16_dais_dp() // 0070 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_w_imm16_adr16_dp() // 0078 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_w_imm16_adr32_dp() // 0079 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_i16u_sr_dp() // 007c ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1cc stiw1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_icount -= 2;
	// 307 stiw2
	// alu r=14 c=2 m=.....  i=....... ALU.or_ a=R.ftu:m_ftu d=R.dtl:m_dt
	alu_or(m_ftu, m_dt);
	m_icount -= 2;
	// 320 stiw3
	m_movemr = m_dbin;
	m_ftu = m_aluo;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_l_imm32_ds_dp() // 0080 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 10c roal1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_or(m_dt, m_da[ry]);
	sr_nzvc();
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=18:m_da[ry]
	alu_or(high16(m_dt), high16(m_da[ry]));
	sr_nzvc_u();
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_l_imm32_ais_dp() // 0090 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=R.alue:m_alue
	alu_or(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_l_imm32_aips_dp() // 0098 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=R.alue:m_alue
	alu_or(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_l_imm32_pais_dp() // 00a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=R.alue:m_alue
	alu_or(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_l_imm32_das_dp() // 00a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=R.alue:m_alue
	alu_or(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_l_imm32_dais_dp() // 00b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e7 aixw0
	// alu r=14 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=R.alue:m_alue
	alu_or(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_l_imm32_adr16_dp() // 00b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=R.alue:m_alue
	alu_or(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ori_l_imm32_adr32_dp() // 00b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=R.alue:m_alue
	alu_or(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 17:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_ds_dp() // 0100 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3e7 btsr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = m_da[rx];
	m_au = m_da[ry];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=R.dyl:m_da[ry]
	alu_eor(m_da[rx], m_da[ry]);
	// 0e7 btsr2
	m_t = m_dcr & 0x10;
	m_alub = m_da[ry];
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto btsr3;
	else
		goto bcsr4;
bcsr4:
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	// alu r=13 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
btsr3:
	// 044 btsr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=1 m=..z..  i=.....i. ALU.and_ a=18:m_da[ry] d=R.dcro:m_dcro
	alu_and(high16(m_da[ry]), 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movep_w_das_dd_dp() // 0108 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1d2 mpiw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 29a mpiw2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	set_8h(m_dbin, m_edb);
	// 368 mpiw3
	m_aob = m_au;
	m_ir = m_irc;
	m_au = m_pc + 4;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_8(m_dbin, m_edb);
	// 36a mpiw4
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_ais_dp() // 0110 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_aips_dp() // 0118 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_pais_dp() // 0120 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_das_dp() // 0128 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_dais_dp() // 0130 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_adr16_dp() // 0138 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_adr32_dp() // 0139 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_dpc_dp() // 013a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_dpci_dp() // 013b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_dd_imm_dp() // 013c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 0ab btsi1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16h(m_dt, high16(m_at));
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	// 0e7 btsr2
	m_t = m_dcr & 0x10;
	m_alub = m_dt;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto btsr3;
	else
		goto bcsr4;
bcsr4:
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_dt, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
btsr3:
	// 044 btsr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=23:m_dt d=R.dcro8:m_dcro8
	alu_and8(high16(m_dt), 1 << (m_dcr & 7));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_dd_ds_dp() // 0140 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3ef bcsr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = m_da[rx];
	m_au = m_da[ry];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=R.dyl:m_da[ry]
	alu_eor(m_da[rx], m_da[ry]);
	// 06a bcsr2
	m_t = m_dcr & 0x10;
	m_alub = m_da[ry];
	m_au = m_pc + 2;
	// alu r=13 c=2 m=.....  i=....... ALU.eor a=R.dyl:m_da[ry] d=R.dcro:m_dcro
	alu_eor(m_da[ry], 1 << (m_dcr & 15));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto bcsr3;
	else
		goto bcsr4;
bcsr4:
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	// alu r=13 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
bcsr3:
	// 084 bcsr3
	m_alub = high16(m_da[ry]);
	// alu r=13 c=2 m=.....  i=....... ALU.eor a=18:m_da[ry] d=R.dcro:m_dcro
	alu_eor(high16(m_da[ry]), 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0a1 bcsr5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	// alu r=13 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movep_l_das_dd_dp() // 0148 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1d6 mpil1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 29e mpil2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	set_8h(m_dbin, m_edb);
	// 34e mpil3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_8(m_dbin, m_edb);
	// 34f mpil4
	m_aob = m_au;
	set_16h(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_8h(m_dbin, m_edb);
	// 368 mpiw3
	m_aob = m_au;
	m_ir = m_irc;
	m_au = m_pc + 4;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_8(m_dbin, m_edb);
	// 36a mpiw4
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_dd_ais_dp() // 0150 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_dd_aips_dp() // 0158 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_dd_pais_dp() // 0160 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_dd_das_dp() // 0168 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_dd_dais_dp() // 0170 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_dd_adr16_dp() // 0178 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_dd_adr32_dp() // 0179 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_dd_ds_dp() // 0180 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3eb bclr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = m_da[rx];
	m_au = m_da[ry];
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dxl:m_da[rx] d=R.dyl:m_da[ry]
	alu_or(m_da[rx], m_da[ry]);
	// 06e bclr2
	m_t = m_dcr & 0x10;
	m_alub = m_da[ry];
	m_au = m_pc + 2;
	// alu r=14 c=2 m=.....  i=.l..... ALU.or_ a=R.dyl:m_da[ry] d=R.dcro:m_dcro
	alu_or(m_da[ry], 1 << (m_dcr & 15));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto bclr3;
	else
		goto bclr4;
bclr4:
	// 0cc bclr4
	// alu r=14 c=4 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=R.dcro:m_dcro
	alu_eor(m_aluo, 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	// alu r=14 c=1 m=..z..  i=.l...i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
bclr3:
	// 08c bclr3
	m_alub = high16(m_da[ry]);
	// alu r=14 c=2 m=.....  i=.l..... ALU.or_ a=18:m_da[ry] d=R.dcro:m_dcro
	alu_or(high16(m_da[ry]), 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0c8 bclr5
	// alu r=14 c=4 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=R.dcro:m_dcro
	alu_eor(m_aluo, 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0a1 bcsr5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	// alu r=14 c=1 m=..z..  i=.l...i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movep_w_dd_das_dp() // 0188 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1ca mpow1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 36d mpow2
	m_aob = m_au;
	m_ir = m_irc;
	set_8xh(m_dbout, m_da[rx]);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dxl:m_da[rx]
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 36e mpow3
	m_aob = m_au;
	set_8xl(m_dbout, m_da[rx]);
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_dd_ais_dp() // 0190 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_dd_aips_dp() // 0198 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_dd_pais_dp() // 01a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_dd_das_dp() // 01a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_dd_dais_dp() // 01b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=bl..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_dd_adr16_dp() // 01b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_dd_adr32_dp() // 01b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_dd_ds_dp() // 01c0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3ef bcsr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = m_da[rx];
	m_au = m_da[ry];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dyl:m_da[ry]
	alu_or(m_da[rx], m_da[ry]);
	// 06a bcsr2
	m_t = m_dcr & 0x10;
	m_alub = m_da[ry];
	m_au = m_pc + 2;
	// alu r=14 c=2 m=.....  i=....... ALU.or_ a=R.dyl:m_da[ry] d=R.dcro:m_dcro
	alu_or(m_da[ry], 1 << (m_dcr & 15));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto bcsr3;
	else
		goto bcsr4;
bcsr4:
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	// alu r=14 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
bcsr3:
	// 084 bcsr3
	m_alub = high16(m_da[ry]);
	// alu r=14 c=2 m=.....  i=....... ALU.or_ a=18:m_da[ry] d=R.dcro:m_dcro
	alu_or(high16(m_da[ry]), 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0a1 bcsr5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	// alu r=14 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movep_l_dd_das_dp() // 01c8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1ce mpol1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 36b mpol2
	m_aob = m_au;
	set_8xh(m_dbout, high16(m_da[rx]));
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=16:m_da[rx] d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 36c mpol3
	m_aob = m_au;
	set_8xl(m_dbout, high16(m_da[rx]));
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=16:m_da[rx] d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 36d mpow2
	m_aob = m_au;
	m_ir = m_irc;
	set_8xh(m_dbout, m_da[rx]);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.dxl:m_da[rx]
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 36e mpow3
	m_aob = m_au;
	set_8xl(m_dbout, m_da[rx]);
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_dd_ais_dp() // 01d0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_dd_aips_dp() // 01d8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_dd_pais_dp() // 01e0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_dd_das_dp() // 01e8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_dd_dais_dp() // 01f0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_dd_adr16_dp() // 01f8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_dd_adr32_dp() // 01f9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_b_imm8_ds_dp() // 0200 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_and8(m_dt, m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_b_imm8_ais_dp() // 0210 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_b_imm8_aips_dp() // 0218 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_b_imm8_pais_dp() // 0220 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_b_imm8_das_dp() // 0228 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_b_imm8_dais_dp() // 0230 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_b_imm8_adr16_dp() // 0238 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_b_imm8_adr32_dp() // 0239 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_imm8_ccr_dp() // 023c ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1cc stiw1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_icount -= 2;
	// 307 stiw2
	// alu r=4 c=2 m=.....  i=b...... ALU.and_ a=R.ftu:m_ftu d=R.dtl:m_dt
	alu_and8(m_ftu, m_dt);
	m_icount -= 2;
	// 320 stiw3
	m_movemr = m_dbin;
	m_ftu = m_aluo;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_w_imm16_ds_dp() // 0240 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_and(m_dt, m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_w_imm16_ais_dp() // 0250 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_w_imm16_aips_dp() // 0258 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_w_imm16_pais_dp() // 0260 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_w_imm16_das_dp() // 0268 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_w_imm16_dais_dp() // 0270 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_w_imm16_adr16_dp() // 0278 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_w_imm16_adr32_dp() // 0279 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_i16u_sr_dp() // 027c ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1cc stiw1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_icount -= 2;
	// 307 stiw2
	// alu r=4 c=2 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=R.dtl:m_dt
	alu_and(m_ftu, m_dt);
	m_icount -= 2;
	// 320 stiw3
	m_movemr = m_dbin;
	m_ftu = m_aluo;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_l_imm32_ds_dp() // 0280 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 10c roal1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_and(m_dt, m_da[ry]);
	sr_nzvc();
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=18:m_da[ry]
	alu_and(high16(m_dt), high16(m_da[ry]));
	sr_nzvc_u();
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_l_imm32_ais_dp() // 0290 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=R.alue:m_alue
	alu_and(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_l_imm32_aips_dp() // 0298 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=R.alue:m_alue
	alu_and(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_l_imm32_pais_dp() // 02a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=R.alue:m_alue
	alu_and(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_l_imm32_das_dp() // 02a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=R.alue:m_alue
	alu_and(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_l_imm32_dais_dp() // 02b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e7 aixw0
	// alu r=4 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=R.alue:m_alue
	alu_and(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_l_imm32_adr16_dp() // 02b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=R.alue:m_alue
	alu_and(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::andi_l_imm32_adr32_dp() // 02b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_and(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=R.alue:m_alue
	alu_and(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 17:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_b_imm8_ds_dp() // 0400 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_sub8(m_dt, m_da[ry]);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_b_imm8_ais_dp() // 0410 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_b_imm8_aips_dp() // 0418 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_b_imm8_pais_dp() // 0420 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_b_imm8_das_dp() // 0428 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_b_imm8_dais_dp() // 0430 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_b_imm8_adr16_dp() // 0438 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_b_imm8_adr32_dp() // 0439 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_w_imm16_ds_dp() // 0440 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_sub(m_dt, m_da[ry]);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_w_imm16_ais_dp() // 0450 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_w_imm16_aips_dp() // 0458 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_w_imm16_pais_dp() // 0460 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_w_imm16_das_dp() // 0468 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_w_imm16_dais_dp() // 0470 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_w_imm16_adr16_dp() // 0478 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_w_imm16_adr32_dp() // 0479 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_l_imm32_ds_dp() // 0480 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 10c roal1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_sub(m_dt, m_da[ry]);
	sr_xnzvc();
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=18:m_da[ry]
	alu_subc(high16(m_dt), high16(m_da[ry]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_l_imm32_ais_dp() // 0490 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_l_imm32_aips_dp() // 0498 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_l_imm32_pais_dp() // 04a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_l_imm32_das_dp() // 04a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_l_imm32_dais_dp() // 04b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e7 aixw0
	// alu r=5 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_l_imm32_adr16_dp() // 04b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subi_l_imm32_adr32_dp() // 04b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 17:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_b_imm8_ds_dp() // 0600 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_add8(m_dt, m_da[ry]);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_b_imm8_ais_dp() // 0610 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_b_imm8_aips_dp() // 0618 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_b_imm8_pais_dp() // 0620 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_b_imm8_das_dp() // 0628 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_b_imm8_dais_dp() // 0630 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_b_imm8_adr16_dp() // 0638 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_b_imm8_adr32_dp() // 0639 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add8(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_w_imm16_ds_dp() // 0640 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_add(m_dt, m_da[ry]);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_w_imm16_ais_dp() // 0650 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_w_imm16_aips_dp() // 0658 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_w_imm16_pais_dp() // 0660 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_w_imm16_das_dp() // 0668 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_w_imm16_dais_dp() // 0670 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_w_imm16_adr16_dp() // 0678 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_w_imm16_adr32_dp() // 0679 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_l_imm32_ds_dp() // 0680 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 10c roal1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_add(m_dt, m_da[ry]);
	sr_xnzvc();
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=18:m_da[ry]
	alu_addc(high16(m_dt), high16(m_da[ry]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_l_imm32_ais_dp() // 0690 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_l_imm32_aips_dp() // 0698 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_l_imm32_pais_dp() // 06a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_l_imm32_das_dp() // 06a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_l_imm32_dais_dp() // 06b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_l_imm32_adr16_dp() // 06b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addi_l_imm32_adr32_dp() // 06b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_add(m_dt, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 17:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_ds_dp() // 0800 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3e7 btsr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = m_dt;
	m_au = m_da[ry];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_eor(m_dt, m_da[ry]);
	// 0e7 btsr2
	m_t = m_dcr & 0x10;
	m_alub = m_da[ry];
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto btsr3;
	else
		goto bcsr4;
bcsr4:
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	// alu r=13 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
btsr3:
	// 044 btsr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=1 m=..z..  i=.....i. ALU.and_ a=18:m_da[ry] d=R.dcro:m_dcro
	alu_and(high16(m_da[ry]), 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_ais_dp() // 0810 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_aips_dp() // 0818 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_pais_dp() // 0820 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_das_dp() // 0828 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_dais_dp() // 0830 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_adr16_dp() // 0838 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_adr32_dp() // 0839 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_dpc_dp() // 083a ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::btst_imm8_dpci_dp() // 083b ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 215 btsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_and8(m_dbin, 1 << (m_dcr & 7));
	sr_z();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_imm8_ds_dp() // 0840 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3ef bcsr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = m_dt;
	m_au = m_da[ry];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_eor(m_dt, m_da[ry]);
	// 06a bcsr2
	m_t = m_dcr & 0x10;
	m_alub = m_da[ry];
	m_au = m_pc + 2;
	// alu r=13 c=2 m=.....  i=....... ALU.eor a=R.dyl:m_da[ry] d=R.dcro:m_dcro
	alu_eor(m_da[ry], 1 << (m_dcr & 15));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto bcsr3;
	else
		goto bcsr4;
bcsr4:
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	// alu r=13 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
bcsr3:
	// 084 bcsr3
	m_alub = high16(m_da[ry]);
	// alu r=13 c=2 m=.....  i=....... ALU.eor a=18:m_da[ry] d=R.dcro:m_dcro
	alu_eor(high16(m_da[ry]), 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0a1 bcsr5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	// alu r=13 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_imm8_ais_dp() // 0850 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_imm8_aips_dp() // 0858 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_imm8_pais_dp() // 0860 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_imm8_das_dp() // 0868 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_imm8_dais_dp() // 0870 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_imm8_adr16_dp() // 0878 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bchg_imm8_adr32_dp() // 0879 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_eor8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=13 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_imm8_ds_dp() // 0880 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3eb bclr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = m_dt;
	m_au = m_da[ry];
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_or(m_dt, m_da[ry]);
	// 06e bclr2
	m_t = m_dcr & 0x10;
	m_alub = m_da[ry];
	m_au = m_pc + 2;
	// alu r=14 c=2 m=.....  i=.l..... ALU.or_ a=R.dyl:m_da[ry] d=R.dcro:m_dcro
	alu_or(m_da[ry], 1 << (m_dcr & 15));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto bclr3;
	else
		goto bclr4;
bclr4:
	// 0cc bclr4
	// alu r=14 c=4 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=R.dcro:m_dcro
	alu_eor(m_aluo, 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	// alu r=14 c=1 m=..z..  i=.l...i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
bclr3:
	// 08c bclr3
	m_alub = high16(m_da[ry]);
	// alu r=14 c=2 m=.....  i=.l..... ALU.or_ a=18:m_da[ry] d=R.dcro:m_dcro
	alu_or(high16(m_da[ry]), 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0c8 bclr5
	// alu r=14 c=4 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=R.dcro:m_dcro
	alu_eor(m_aluo, 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0a1 bcsr5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	// alu r=14 c=1 m=..z..  i=.l...i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_imm8_ais_dp() // 0890 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_imm8_aips_dp() // 0898 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_imm8_pais_dp() // 08a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_imm8_das_dp() // 08a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_imm8_dais_dp() // 08b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=bl..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_imm8_adr16_dp() // 08b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bclr_imm8_adr32_dp() // 08b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=bl..... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 069 bclm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_ftu = m_sr;
	// alu r=14 c=2 m=.....  i=bl..... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	// 067 bclm2
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=4 m=.....  i=bl..... ALU.eor a=R.aluo:m_aluo d=R.dcro8:m_dcro8
	alu_eor8(m_aluo, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=bl...i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_imm8_ds_dp() // 08c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3ef bcsr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = m_dt;
	m_au = m_da[ry];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_or(m_dt, m_da[ry]);
	// 06a bcsr2
	m_t = m_dcr & 0x10;
	m_alub = m_da[ry];
	m_au = m_pc + 2;
	// alu r=14 c=2 m=.....  i=....... ALU.or_ a=R.dyl:m_da[ry] d=R.dcro:m_dcro
	alu_or(m_da[ry], 1 << (m_dcr & 15));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto bcsr3;
	else
		goto bcsr4;
bcsr4:
	// 0c4 bcsr4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	// alu r=14 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
bcsr3:
	// 084 bcsr3
	m_alub = high16(m_da[ry]);
	// alu r=14 c=2 m=.....  i=....... ALU.or_ a=18:m_da[ry] d=R.dcro:m_dcro
	alu_or(high16(m_da[ry]), 1 << (m_dcr & 15));
	m_icount -= 2;
	// 0a1 bcsr5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	// alu r=14 c=1 m=..z..  i=.....i. ALU.and_ a=alub d=R.dcro:m_dcro
	alu_and(m_alub, 1 << (m_dcr & 15));
	sr_z();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_imm8_ais_dp() // 08d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_imm8_aips_dp() // 08d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_imm8_pais_dp() // 08e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_imm8_das_dp() // 08e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_imm8_dais_dp() // 08f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_imm8_adr16_dp() // 08f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bset_imm8_adr32_dp() // 08f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 081 bcsm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=14 c=2 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=R.dcro8:m_dcro8
	alu_or8(m_dbin, 1 << (m_dcr & 7));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 082 bcsm2
	m_aob = m_at;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	// alu r=14 c=1 m=..z..  i=b....i. ALU.and_ a=alub d=R.dcro8:m_dcro8
	alu_and8(m_alub, 1 << (m_dcr & 7));
	sr_z();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_b_imm8_ds_dp() // 0a00 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_eor8(m_dt, m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_b_imm8_ais_dp() // 0a10 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_b_imm8_aips_dp() // 0a18 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_b_imm8_pais_dp() // 0a20 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_b_imm8_das_dp() // 0a28 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_b_imm8_dais_dp() // 0a30 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_b_imm8_adr16_dp() // 0a38 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_b_imm8_adr32_dp() // 0a39 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor8(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_imm8_ccr_dp() // 0a3c ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1cc stiw1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_icount -= 2;
	// 307 stiw2
	// alu r=13 c=2 m=.....  i=b...... ALU.eor a=R.ftu:m_ftu d=R.dtl:m_dt
	alu_eor8(m_ftu, m_dt);
	m_icount -= 2;
	// 320 stiw3
	m_movemr = m_dbin;
	m_ftu = m_aluo;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_w_imm16_ds_dp() // 0a40 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_eor(m_dt, m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_w_imm16_ais_dp() // 0a50 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_w_imm16_aips_dp() // 0a58 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_w_imm16_pais_dp() // 0a60 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_w_imm16_das_dp() // 0a68 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_w_imm16_dais_dp() // 0a70 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_w_imm16_adr16_dp() // 0a78 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_w_imm16_adr32_dp() // 0a79 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_i16u_sr_dp() // 0a7c ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1cc stiw1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_icount -= 2;
	// 307 stiw2
	// alu r=13 c=2 m=.....  i=....... ALU.eor a=R.ftu:m_ftu d=R.dtl:m_dt
	alu_eor(m_ftu, m_dt);
	m_icount -= 2;
	// 320 stiw3
	m_movemr = m_dbin;
	m_ftu = m_aluo;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.aluo:m_aluo d=none
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_l_imm32_ds_dp() // 0a80 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 10c roal1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_eor(m_dt, m_da[ry]);
	sr_nzvc();
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=23:m_dt d=18:m_da[ry]
	alu_eor(high16(m_dt), high16(m_da[ry]));
	sr_nzvc_u();
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_l_imm32_ais_dp() // 0a90 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=23:m_dt d=R.alue:m_alue
	alu_eor(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_l_imm32_aips_dp() // 0a98 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=23:m_dt d=R.alue:m_alue
	alu_eor(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_l_imm32_pais_dp() // 0aa0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=23:m_dt d=R.alue:m_alue
	alu_eor(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_l_imm32_das_dp() // 0aa8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=23:m_dt d=R.alue:m_alue
	alu_eor(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_l_imm32_dais_dp() // 0ab0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e7 aixw0
	// alu r=13 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=23:m_dt d=R.alue:m_alue
	alu_eor(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_l_imm32_adr16_dp() // 0ab8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=23:m_dt d=R.alue:m_alue
	alu_eor(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eori_l_imm32_adr32_dp() // 0ab9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_eor(m_dt, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=23:m_dt d=R.alue:m_alue
	alu_eor(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 17:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_b_imm8_ds_dp() // 0c00 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 108 rcaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_sub8(m_dt, m_da[ry]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_b_imm8_ais_dp() // 0c10 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_b_imm8_aips_dp() // 0c18 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_b_imm8_pais_dp() // 0c20 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_b_imm8_das_dp() // 0c28 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_b_imm8_dais_dp() // 0c30 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_b_imm8_adr16_dp() // 0c38 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_b_imm8_adr32_dp() // 0c39 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub8(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_w_imm16_ds_dp() // 0c40 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 108 rcaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_sub(m_dt, m_da[ry]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_w_imm16_ais_dp() // 0c50 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_w_imm16_aips_dp() // 0c58 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_w_imm16_pais_dp() // 0c60 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_w_imm16_das_dp() // 0c68 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_w_imm16_dais_dp() // 0c70 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_w_imm16_adr16_dp() // 0c78 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_w_imm16_adr32_dp() // 0c79 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 087 cpdw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_l_imm32_ds_dp() // 0c80 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	if(!m_cmpild_instr_callback.isnull()) (m_cmpild_instr_callback)(ry, (m_dt & 0xffff0000) | m_dbin);
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 104 rcal1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dyl:m_da[ry]
	alu_sub(m_dt, m_da[ry]);
	sr_nzvc();
	// 239 rcal2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=18:m_da[ry]
	alu_subc(high16(m_dt), high16(m_da[ry]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_l_imm32_ais_dp() // 0c90 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 08f cpdl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 171 cpdl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_l_imm32_aips_dp() // 0c98 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 08f cpdl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 171 cpdl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_l_imm32_pais_dp() // 0ca0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 08f cpdl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 171 cpdl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_l_imm32_das_dp() // 0ca8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 08f cpdl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 171 cpdl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_l_imm32_dais_dp() // 0cb0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e7 aixw0
	// alu r=6 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 08f cpdl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 171 cpdl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_l_imm32_adr16_dp() // 0cb8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 08f cpdl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 171 cpdl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpi_l_imm32_adr32_dp() // 0cb9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 3e0 o#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b9 o#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 08f cpdl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_sub(m_dt, m_dbin);
	sr_nzvc();
	// 171 cpdl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ds_dd_dp() // 1000 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 121 rrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ais_dd_dp() // 1010 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_aips_dd_dp() // 1018 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_pais_dd_dp() // 1020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_das_dd_dp() // 1028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dais_dd_dp() // 1030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr16_dd_dp() // 1038 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr32_dd_dp() // 1039 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpc_dd_dp() // 103a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpci_dd_dp() // 103b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_8(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_imm8_dd_dp() // 103c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 121 rrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_dt;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ds_aid_dp() // 1080 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2fa rmrw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_da[ry]);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ais_aid_dp() // 1090 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_aips_aid_dp() // 1098 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_pais_aid_dp() // 10a0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_das_aid_dp() // 10a8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dais_aid_dp() // 10b0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr16_aid_dp() // 10b8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr32_aid_dp() // 10b9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpc_aid_dp() // 10ba f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpci_aid_dp() // 10bb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_imm8_aid_dp() // 10bc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2fa rmrw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dt);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ds_aipd_dp() // 10c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2fe rmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_da[ry]);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ais_aipd_dp() // 10d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_aips_aipd_dp() // 10d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_pais_aipd_dp() // 10e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_das_aipd_dp() // 10e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dais_aipd_dp() // 10f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr16_aipd_dp() // 10f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr32_aipd_dp() // 10f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpc_aipd_dp() // 10fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpci_aipd_dp() // 10fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dbin);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_imm8_aipd_dp() // 10fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2fe rmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	set_8xl(m_dbout, m_dt);
	m_pc = m_au;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ds_paid_dp() // 1100 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2f8 rmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ais_paid_dp() // 1110 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_aips_paid_dp() // 1118 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_pais_paid_dp() // 1120 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_das_paid_dp() // 1128 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dais_paid_dp() // 1130 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr16_paid_dp() // 1138 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr32_paid_dp() // 1139 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpc_paid_dp() // 113a f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpci_paid_dp() // 113b f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_imm8_paid_dp() // 113c f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2f8 rmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ds_dad_dp() // 1140 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2da rmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_dbin) + m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	set_8xl(m_dbout, m_da[ry]);
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ais_dad_dp() // 1150 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_aips_dad_dp() // 1158 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_pais_dad_dp() // 1160 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_das_dad_dp() // 1168 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dais_dad_dp() // 1170 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr16_dad_dp() // 1178 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr32_dad_dp() // 1179 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpc_dad_dp() // 117a f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpci_dad_dp() // 117b f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_imm8_dad_dp() // 117c f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2da rmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_dbin) + m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	set_8xl(m_dbout, m_dt);
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ds_daid_dp() // 1180 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1eb rmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 109 rmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto rmxw3;
	else
		goto rmxw2;
rmxw2:
	// 128 rmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmxw3:
	// 1e8 rmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmdw2:
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	set_8xl(m_dbout, m_da[ry]);
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ais_daid_dp() // 1190 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_aips_daid_dp() // 1198 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_pais_daid_dp() // 11a0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_das_daid_dp() // 11a8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dais_daid_dp() // 11b0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr16_daid_dp() // 11b8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr32_daid_dp() // 11b9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpc_daid_dp() // 11ba f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpci_daid_dp() // 11bb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=bl..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_imm8_daid_dp() // 11bc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1eb rmxw0
	// alu r=2 c=5 m=.....  i=bl..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 109 rmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto rmxw3;
	else
		goto rmxw2;
rmxw2:
	// 128 rmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmxw3:
	// 1e8 rmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmdw2:
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	set_8xl(m_dbout, m_dt);
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=bl...i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ds_adr16_dp() // 11c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2d9 raww1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = ext32(m_dbin);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ais_adr16_dp() // 11d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_aips_adr16_dp() // 11d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_pais_adr16_dp() // 11e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_das_adr16_dp() // 11e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dais_adr16_dp() // 11f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr16_adr16_dp() // 11f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr32_adr16_dp() // 11f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpc_adr16_dp() // 11fa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpci_adr16_dp() // 11fb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_imm8_adr16_dp() // 11fc ffff
{
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2d9 raww1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dt);
	m_au = ext32(m_dbin);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ds_adr32_dp() // 13c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1ea ralw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bb ralw2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_ais_adr32_dp() // 13d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_aips_adr32_dp() // 13d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_pais_adr32_dp() // 13e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_das_adr32_dp() // 13e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dais_adr32_dp() // 13f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr16_adr32_dp() // 13f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_adr32_adr32_dp() // 13f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpc_adr32_dp() // 13fa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_dpci_adr32_dp() // 13fb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_b_imm8_adr32_dp() // 13fc ffff
{
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1ea ralw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bb ralw2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dt);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and8(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ds_dd_dp() // 2000 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 129 rrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_da[rx] = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_as_dd_dp() // 2008 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 129 rrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=17:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ais_dd_dp() // 2010 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_aips_dd_dp() // 2018 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_pais_dd_dp() // 2020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_das_dd_dp() // 2028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dais_dd_dp() // 2030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr16_dd_dp() // 2038 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr32_dd_dp() // 2039 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpc_dd_dp() // 203a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpci_dd_dp() // 203b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_imm32_dd_dp() // 203c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 129 rrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_dt;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=23:m_dt d=-1
	alu_and(high16(m_dt), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_ds_ad_dp() // 2040 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 129 rrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_as_ad_dp() // 2048 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 129 rrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=17:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	m_da[rx] = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_ais_ad_dp() // 2050 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_aips_ad_dp() // 2058 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_pais_ad_dp() // 2060 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_das_ad_dp() // 2068 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_dais_ad_dp() // 2070 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_adr16_ad_dp() // 2078 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_adr32_ad_dp() // 2079 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_dpc_ad_dp() // 207a f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_dpci_ad_dp() // 207b f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29f mrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 36f mrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_alue);
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_l_imm32_ad_dp() // 207c f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 129 rrgl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_dt;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=23:m_dt d=-1
	alu_and(high16(m_dt), 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ds_aid_dp() // 2080 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2f9 rmrl1
	m_aob = m_da[rx];
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23f rmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_as_aid_dp() // 2088 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2f9 rmrl1
	m_aob = m_da[rx];
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23f rmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ais_aid_dp() // 2090 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_aips_aid_dp() // 2098 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_pais_aid_dp() // 20a0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_das_aid_dp() // 20a8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dais_aid_dp() // 20b0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr16_aid_dp() // 20b8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr32_aid_dp() // 20b9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpc_aid_dp() // 20ba f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpci_aid_dp() // 20bb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a9 mmrl1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3aa mmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_imm32_aid_dp() // 20bc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2f9 rmrl1
	m_aob = m_da[rx];
	m_dbout = high16(m_dt);
	m_alub = high16(m_dt);
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23f rmrl2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_dt;
	m_au = m_pc;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ds_aipd_dp() // 20c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2fd rmil1
	m_aob = m_da[rx];
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23c rmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23d rmil3
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_as_aipd_dp() // 20c8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2fd rmil1
	m_aob = m_da[rx];
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23c rmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23d rmil3
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ais_aipd_dp() // 20d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_aips_aipd_dp() // 20d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_pais_aipd_dp() // 20e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_das_aipd_dp() // 20e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dais_aipd_dp() // 20f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr16_aipd_dp() // 20f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr32_aipd_dp() // 20f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpc_aipd_dp() // 20fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpci_aipd_dp() // 20fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ad mmil1
	m_aob = m_da[rx];
	m_dbout = m_alue;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 3ae mmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_imm32_aipd_dp() // 20fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2fd rmil1
	m_aob = m_da[rx];
	m_dbout = high16(m_dt);
	m_alub = high16(m_dt);
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23c rmil2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_dt;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 23d rmil3
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ds_paid_dp() // 2100 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2fc rmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 23e rmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_as_paid_dp() // 2108 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2fc rmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 23e rmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=17:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ais_paid_dp() // 2110 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_aips_paid_dp() // 2118 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_pais_paid_dp() // 2120 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_das_paid_dp() // 2128 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dais_paid_dp() // 2130 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr16_paid_dp() // 2138 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr32_paid_dp() // 2139 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpc_paid_dp() // 213a f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpci_paid_dp() // 213b f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38f mmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34a mmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_imm32_paid_dp() // 213c f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2fc rmml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 23e rmml2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=23:m_dt d=-1
	alu_and(high16(m_dt), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ds_dad_dp() // 2140 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2de rmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_dbin) + m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2be rmdl2
	m_aob = m_au;
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 2df rmdl3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_as_dad_dp() // 2148 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2de rmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_dbin) + m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2be rmdl2
	m_aob = m_au;
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=17:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 2df rmdl3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ais_dad_dp() // 2150 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_aips_dad_dp() // 2158 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_pais_dad_dp() // 2160 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_das_dad_dp() // 2168 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dais_dad_dp() // 2170 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr16_dad_dp() // 2178 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr32_dad_dp() // 2179 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpc_dad_dp() // 217a f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpci_dad_dp() // 217b f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38e mmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_imm32_dad_dp() // 217c f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2de rmdl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_dbin) + m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2be rmdl2
	m_aob = m_au;
	m_dbout = high16(m_dt);
	m_alub = high16(m_dt);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=23:m_dt d=-1
	alu_and(high16(m_dt), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 2df rmdl3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_dt;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ds_daid_dp() // 2180 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1ef rmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 105 rmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto rmxl3;
	else
		goto rmxl2;
rmxl2:
	// 12c rmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdl2;
rmxl3:
	// 1ec rmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdl2;
rmdl2:
	// 2be rmdl2
	m_aob = m_au;
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 2df rmdl3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_as_daid_dp() // 2188 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1ef rmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 105 rmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto rmxl3;
	else
		goto rmxl2;
rmxl2:
	// 12c rmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdl2;
rmxl3:
	// 1ec rmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdl2;
rmdl2:
	// 2be rmdl2
	m_aob = m_au;
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=17:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 2df rmdl3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ais_daid_dp() // 2190 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_aips_daid_dp() // 2198 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_pais_daid_dp() // 21a0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_das_daid_dp() // 21a8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dais_daid_dp() // 21b0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr16_daid_dp() // 21b8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr32_daid_dp() // 21b9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpc_daid_dp() // 21ba f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpci_daid_dp() // 21bb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29c mmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 10d mmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxl3;
	else
		goto mmxl2;
mmxl2:
	// 02c mmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mmxl3:
	// 0ec mmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto mawl2;
mawl2:
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_imm32_daid_dp() // 21bc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1ef rmxl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 105 rmxl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto rmxl3;
	else
		goto rmxl2;
rmxl2:
	// 12c rmxl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdl2;
rmxl3:
	// 1ec rmxl3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdl2;
rmdl2:
	// 2be rmdl2
	m_aob = m_au;
	m_dbout = high16(m_dt);
	m_alub = high16(m_dt);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=23:m_dt d=-1
	alu_and(high16(m_dt), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 2df rmdl3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_dt;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 258 rmrl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ds_adr16_dp() // 21c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2dd rawl1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = ext32(m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2ba rall3
	m_aob = m_au;
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_as_adr16_dp() // 21c8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2dd rawl1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = ext32(m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2ba rall3
	m_aob = m_au;
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=17:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ais_adr16_dp() // 21d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_aips_adr16_dp() // 21d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_pais_adr16_dp() // 21e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_das_adr16_dp() // 21e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dais_adr16_dp() // 21f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr16_adr16_dp() // 21f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr32_adr16_dp() // 21f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpc_adr16_dp() // 21fa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpci_adr16_dp() // 21fb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38c mawl1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 32f mawl2
	m_aob = m_au;
	m_dbout = m_alue;
	set_16l(m_at, m_aluo);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_imm32_adr16_dp() // 21fc ffff
{
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2dd rawl1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dt);
	m_au = ext32(m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2ba rall3
	m_aob = m_au;
	m_dbout = high16(m_dt);
	m_alub = high16(m_dt);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=23:m_dt d=-1
	alu_and(high16(m_dt), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ds_adr32_dp() // 23c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1ee rall1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bf rall2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2ba rall3
	m_aob = m_au;
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_as_adr32_dp() // 23c8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1ee rall1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bf rall2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2ba rall3
	m_aob = m_au;
	m_dbout = high16(m_da[ry]);
	m_alub = high16(m_da[ry]);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=17:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_ais_adr32_dp() // 23d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_aips_adr32_dp() // 23d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_pais_adr32_dp() // 23e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_das_adr32_dp() // 23e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dais_adr32_dp() // 23f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr16_adr32_dp() // 23f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_adr32_adr32_dp() // 23f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpc_adr32_dp() // 23fa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_dpci_adr32_dp() // 23fb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 30f mall1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 329 mall2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_dbout = m_aluo;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 32a mall3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_l_imm32_adr32_dp() // 23fc ffff
{
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1ee rall1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bf rall2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dt);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2ba rall3
	m_aob = m_au;
	m_dbout = high16(m_dt);
	m_alub = high16(m_dt);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nz..  i=......f ALU.and_ a=23:m_dt d=-1
	alu_and(high16(m_dt), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ds_dd_dp() // 3000 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 121 rrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_as_dd_dp() // 3008 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 121 rrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ais_dd_dp() // 3010 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_aips_dd_dp() // 3018 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_pais_dd_dp() // 3020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_das_dd_dp() // 3028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dais_dd_dp() // 3030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr16_dd_dp() // 3038 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr32_dd_dp() // 3039 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpc_dd_dp() // 303a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpci_dd_dp() // 303b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29b mrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_imm16_dd_dp() // 303c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 121 rrgw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_dt;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_ds_ad_dp() // 3040 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 279 rrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	m_au = m_au + 2;
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_as_ad_dp() // 3048 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 279 rrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	m_au = m_au + 2;
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=17:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	m_da[rx] = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_ais_ad_dp() // 3050 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_aips_ad_dp() // 3058 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_pais_ad_dp() // 3060 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_das_ad_dp() // 3068 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_dais_ad_dp() // 3070 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_adr16_ad_dp() // 3078 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_adr32_ad_dp() // 3079 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_dpc_ad_dp() // 307a f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_dpci_ad_dp() // 307b f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 158 mrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movea_w_imm16_ad_dp() // 307c f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 279 rrgm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	m_au = m_au + 2;
	// 278 rrgl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	// alu r=2 c=1 m=.....  i=......f ALU.and_ a=23:m_dt d=-1
	alu_and(high16(m_dt), 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ds_aid_dp() // 3080 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2fa rmrw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_as_aid_dp() // 3088 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2fa rmrw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ais_aid_dp() // 3090 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_aips_aid_dp() // 3098 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_pais_aid_dp() // 30a0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_das_aid_dp() // 30a8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dais_aid_dp() // 30b0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr16_aid_dp() // 30b8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr32_aid_dp() // 30b9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpc_aid_dp() // 30ba f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpci_aid_dp() // 30bb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3ab mmrw1
	m_aob = m_da[rx];
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_imm16_aid_dp() // 30bc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2fa rmrw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dt;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ds_aipd_dp() // 30c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2fe rmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_as_aipd_dp() // 30c8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2fe rmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ais_aipd_dp() // 30d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_aips_aipd_dp() // 30d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_pais_aipd_dp() // 30e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_das_aipd_dp() // 30e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dais_aipd_dp() // 30f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr16_aipd_dp() // 30f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr32_aipd_dp() // 30f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpc_aipd_dp() // 30fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpci_aipd_dp() // 30fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3af mmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dbin;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_imm16_aipd_dp() // 30fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2fe rmiw1
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_dbout = m_dt;
	m_pc = m_au;
	m_au = m_da[rx] + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ds_paid_dp() // 3100 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2f8 rmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_as_paid_dp() // 3108 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2f8 rmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ais_paid_dp() // 3110 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_aips_paid_dp() // 3118 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_pais_paid_dp() // 3120 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_das_paid_dp() // 3128 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dais_paid_dp() // 3130 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr16_paid_dp() // 3138 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr32_paid_dp() // 3139 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpc_paid_dp() // 313a f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpci_paid_dp() // 313b f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38b mmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_imm16_paid_dp() // 313c f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2f8 rmmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_da[rx] - 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34b mmmw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ds_dad_dp() // 3140 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2da rmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_dbin) + m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_as_dad_dp() // 3148 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2da rmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_dbin) + m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ais_dad_dp() // 3150 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_aips_dad_dp() // 3158 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_pais_dad_dp() // 3160 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_das_dad_dp() // 3168 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dais_dad_dp() // 3170 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr16_dad_dp() // 3178 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr32_dad_dp() // 3179 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpc_dad_dp() // 317a f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpci_dad_dp() // 317b f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 38a mmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_da[rx];
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_imm16_dad_dp() // 317c f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2da rmdw1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_dbin) + m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_dt;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ds_daid_dp() // 3180 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1eb rmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 109 rmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto rmxw3;
	else
		goto rmxw2;
rmxw2:
	// 128 rmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmxw3:
	// 1e8 rmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmdw2:
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_as_daid_dp() // 3188 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1eb rmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 109 rmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto rmxw3;
	else
		goto rmxw2;
rmxw2:
	// 128 rmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmxw3:
	// 1e8 rmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmdw2:
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_da[ry];
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ais_daid_dp() // 3190 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_aips_daid_dp() // 3198 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_pais_daid_dp() // 31a0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_das_daid_dp() // 31a8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dais_daid_dp() // 31b0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr16_daid_dp() // 31b8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr32_daid_dp() // 31b9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpc_daid_dp() // 31ba f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpci_daid_dp() // 31bb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 298 mmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.aluo:m_aluo d=0
	alu_ext(m_aluo);
	m_icount -= 2;
	// 101 mmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto mmxw3;
	else
		goto mmxw2;
mmxw2:
	// 028 mmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
mmxw3:
	// 0e8 mmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto maww2;
maww2:
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_imm16_daid_dp() // 31bc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1eb rmxw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 109 rmxw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_pc = m_au;
	m_au = m_da[rx] + ext32(m_aluo);
	if(m_t)
		goto rmxw3;
	else
		goto rmxw2;
rmxw2:
	// 128 rmxw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmxw3:
	// 1e8 rmxw3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto rmdw2;
rmdw2:
	// 2db rmdw2
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_dt;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ds_adr16_dp() // 31c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2d9 raww1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = ext32(m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_as_adr16_dp() // 31c8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2d9 raww1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = ext32(m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ais_adr16_dp() // 31d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_aips_adr16_dp() // 31d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_pais_adr16_dp() // 31e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_das_adr16_dp() // 31e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dais_adr16_dp() // 31f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr16_adr16_dp() // 31f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr32_adr16_dp() // 31f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpc_adr16_dp() // 31fa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpci_adr16_dp() // 31fb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 388 maww1
	m_aob = m_au;
	m_pc = m_au;
	m_au = ext32(m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_imm16_adr16_dp() // 31fc ffff
{
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2d9 raww1
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dt);
	m_au = ext32(m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ds_adr32_dp() // 33c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1ea ralw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bb ralw2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_as_adr32_dp() // 33c8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1ea ralw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bb ralw2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_da[ry]);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_ais_adr32_dp() // 33d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_aips_adr32_dp() // 33d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_pais_adr32_dp() // 33e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_das_adr32_dp() // 33e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dais_adr32_dp() // 33f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr16_adr32_dp() // 33f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_adr32_adr32_dp() // 33f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpc_adr32_dp() // 33fa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_dpci_adr32_dp() // 33fb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32b malw1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_aluo);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 32e malw2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_w_imm16_adr32_dp() // 33fc ffff
{
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1ea ralw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bb ralw2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dt);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 389 maww2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_b_ds_dp() // 4000 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dyl:m_da[ry] d=0
	alu_subx8(m_da[ry], 0x0000);
	sr_xnzvc_u();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_b_ais_dp() // 4010 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx8(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_b_aips_dp() // 4018 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx8(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_b_pais_dp() // 4020 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx8(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_b_das_dp() // 4028 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx8(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_b_dais_dp() // 4030 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=10 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx8(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_b_adr16_dp() // 4038 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx8(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_b_adr32_dp() // 4039 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx8(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_w_ds_dp() // 4040 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dyl:m_da[ry] d=0
	alu_subx(m_da[ry], 0x0000);
	sr_xnzvc_u();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_w_ais_dp() // 4050 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_w_aips_dp() // 4058 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_w_pais_dp() // 4060 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_w_das_dp() // 4068 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_w_dais_dp() // 4070 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=10 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_w_adr16_dp() // 4078 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_w_adr32_dp() // 4079 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_l_ds_dp() // 4080 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 137 nnrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dyl:m_da[ry] d=0
	alu_subx(m_da[ry], 0x0000);
	sr_xnzvc_u();
	// 15e nnrl2
	set_16l(m_da[ry], m_aluo);
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=18:m_da[ry] d=0
	alu_subc(high16(m_da[ry]), 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_l_ais_dp() // 4090 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_l_aips_dp() // 4098 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_l_pais_dp() // 40a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_l_das_dp() // 40a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_l_dais_dp() // 40b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=10 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_l_adr16_dp() // 40b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::negx_l_adr32_dp() // 40b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dbin:m_dbin d=0
	alu_subx(m_dbin, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_sr_ds_dp() // 40c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3a5 strw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_ftu = m_sr;
	// 340 strw2
	set_16l(m_da[ry], m_ftu);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_sr_ais_dp() // 40d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a1 stmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_ftu = m_sr;
	// 324 sftm2
	m_au = m_at;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_sr_aips_dp() // 40d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a1 stmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_ftu = m_sr;
	// 324 sftm2
	m_au = m_at;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_sr_pais_dp() // 40e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a1 stmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_ftu = m_sr;
	// 324 sftm2
	m_au = m_at;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_sr_das_dp() // 40e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a1 stmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_ftu = m_sr;
	// 324 sftm2
	m_au = m_at;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_sr_dais_dp() // 40f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=10 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a1 stmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_ftu = m_sr;
	// 324 sftm2
	m_au = m_at;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_sr_adr16_dp() // 40f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a1 stmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_ftu = m_sr;
	// 324 sftm2
	m_au = m_at;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_sr_adr32_dp() // 40f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3a1 stmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_ftu = m_sr;
	// 324 sftm2
	m_au = m_at;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::chk_w_ds_dd_dp() // 4180 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 152 chkr1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dyl:m_da[ry]
	alu_sub(m_da[rx], m_da[ry]);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_ais_dd_dp() // 4190 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_aips_dd_dp() // 4198 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_pais_dd_dp() // 41a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_das_dd_dp() // 41a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_dais_dd_dp() // 41b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_adr16_dd_dp() // 41b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_adr32_dd_dp() // 41b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_dpc_dd_dp() // 41ba f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_dpci_dd_dp() // 41bb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 151 chkm1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::chk_w_imm16_dd_dp() // 41bc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 152 chkr1
	m_alub = m_da[rx];
	m_au = m_au - 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dtl:m_dt
	alu_sub(m_da[rx], m_dt);
	sr_nzvc();
	m_icount -= 2;
	// 153 chkr2
	m_t = !(m_isr & (SR_V|SR_N));
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.nzvc  i=.l...i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto chkr3;
	else
		goto trap1;
trap1:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x06);
	m_da[16] = m_au;
	m_ftu = 0x0018;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
chkr3:
	// 110 chkr3
	m_t = m_isr & SR_N;
	m_icount -= 2;
	if(m_t)
		goto trap1;
	else
		goto chkr4;
mmrw3:
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
chkr4:
	// 150 chkr4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	goto mmrw3;
	}
}

void m68000_device::lea_ais_ad_dp() // 41d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2f1 leaa1
	m_aob = m_au;
	m_ir = m_irc;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_at = m_da[ry];
	m_ftu = m_dbin;
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lea_das_ad_dp() // 41e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2f2 lead1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// 309 lead2
	m_da[rx] = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lea_dais_ad_dp() // 41f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1fb leax0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3ea leax1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto leax3;
	else
		goto leax2;
leax2:
	// 130 leax2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto leax4;
leax3:
	// 1f0 leax3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto leax4;
leax4:
	// 30a leax4
	m_da[rx] = m_au;
	m_au = m_pc + 4;
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lea_adr16_ad_dp() // 41f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 275 laaw1
	m_aob = m_au;
	m_da[rx] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lea_adr32_ad_dp() // 41f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e4 laal1
	m_aob = m_au;
	set_16h(m_da[rx], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bd laal2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_da[rx], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lea_dpc_ad_dp() // 41fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2f2 lead1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// 309 lead2
	m_da[rx] = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lea_dpci_ad_dp() // 41fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1fb leax0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3ea leax1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto leax3;
	else
		goto leax2;
leax2:
	// 130 leax2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto leax4;
leax3:
	// 1f0 leax3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto leax4;
leax4:
	// 30a leax4
	m_da[rx] = m_au;
	m_au = m_pc + 4;
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_b_ds_dp() // 4200 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=0
	alu_and8(m_da[ry], 0x0000);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_b_ais_dp() // 4210 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and8(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_b_aips_dp() // 4218 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and8(m_da[m_movems], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and8(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_b_pais_dp() // 4220 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and8(m_da[m_movems], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and8(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_b_das_dp() // 4228 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and8(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_b_dais_dp() // 4230 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and8(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_b_adr16_dp() // 4238 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and8(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and8(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_b_adr32_dp() // 4239 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and8(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and8(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_w_ds_dp() // 4240 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=0
	alu_and(m_da[ry], 0x0000);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_w_ais_dp() // 4250 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_w_aips_dp() // 4258 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and(m_da[m_movems], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_w_pais_dp() // 4260 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and(m_da[m_movems], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_w_das_dp() // 4268 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_w_dais_dp() // 4270 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_w_adr16_dp() // 4278 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_w_adr32_dp() // 4279 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_l_ds_dp() // 4280 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 137 nnrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=0
	alu_and(m_da[ry], 0x0000);
	sr_nzvc();
	// 15e nnrl2
	set_16l(m_da[ry], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=18:m_da[ry] d=0
	alu_and(high16(m_da[ry]), 0x0000);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_l_ais_dp() // 4290 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=0
	alu_and(m_alub, 0x0000);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_l_aips_dp() // 4298 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=0
	alu_and(m_alub, 0x0000);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_l_pais_dp() // 42a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=0
	alu_and(m_alub, 0x0000);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_l_das_dp() // 42a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=0
	alu_and(m_alub, 0x0000);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_l_dais_dp() // 42b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=4 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=0
	alu_and(m_alub, 0x0000);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_l_adr16_dp() // 42b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=0
	alu_and(m_alub, 0x0000);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::clr_l_adr32_dp() // 42b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_and(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=0
	alu_and(m_alub, 0x0000);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_b_ds_dp() // 4400 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dyl:m_da[ry] d=0
	alu_sub8(m_da[ry], 0x0000);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_b_ais_dp() // 4410 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub8(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_b_aips_dp() // 4418 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub8(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_b_pais_dp() // 4420 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub8(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_b_das_dp() // 4428 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub8(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_b_dais_dp() // 4430 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub8(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_b_adr16_dp() // 4438 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub8(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_b_adr32_dp() // 4439 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub8(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_w_ds_dp() // 4440 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dyl:m_da[ry] d=0
	alu_sub(m_da[ry], 0x0000);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_w_ais_dp() // 4450 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_w_aips_dp() // 4458 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_w_pais_dp() // 4460 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_w_das_dp() // 4468 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_w_dais_dp() // 4470 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_w_adr16_dp() // 4478 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_w_adr32_dp() // 4479 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_l_ds_dp() // 4480 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 137 nnrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dyl:m_da[ry] d=0
	alu_sub(m_da[ry], 0x0000);
	sr_xnzvc();
	// 15e nnrl2
	set_16l(m_da[ry], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=18:m_da[ry] d=0
	alu_subc(high16(m_da[ry]), 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_l_ais_dp() // 4490 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_l_aips_dp() // 4498 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_l_pais_dp() // 44a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_l_das_dp() // 44a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_l_dais_dp() // 44b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=5 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_l_adr16_dp() // 44b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::neg_l_adr32_dp() // 44b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=0
	alu_sub(m_dbin, 0x0000);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=0
	alu_subc(m_alub, 0x0000);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_ds_ccr_dp() // 44c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 301 rstw1
	m_movemr = m_dbin;
	m_ftu = m_da[ry];
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_ais_ccr_dp() // 44d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_aips_ccr_dp() // 44d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_pais_ccr_dp() // 44e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_das_ccr_dp() // 44e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_dais_ccr_dp() // 44f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_adr16_ccr_dp() // 44f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_adr32_ccr_dp() // 44f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_dpc_ccr_dp() // 44fa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_dpci_ccr_dp() // 44fb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_imm8_ccr_dp() // 44fc ffff
{
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 301 rstw1
	m_movemr = m_dbin;
	m_ftu = m_dt;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_b_ds_dp() // 4600 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=2 m=.nzvc  i=b....i. ALU.not_ a=R.dyl:m_da[ry] d=0
	alu_not8(m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_b_ais_dp() // 4610 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8x(m_dbin, 0xff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=b....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not8(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_b_aips_dp() // 4618 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=alub d=-1
	alu_and8x(m_alub, 0xff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=b....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not8(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_b_pais_dp() // 4620 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=alub d=-1
	alu_and8x(m_alub, 0xff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=b....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not8(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_b_das_dp() // 4628 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8x(m_dbin, 0xff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=b....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not8(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_b_dais_dp() // 4630 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=11 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8x(m_dbin, 0xff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=b....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not8(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_b_adr16_dp() // 4638 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8x(m_dbin, 0xff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=b....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not8(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_b_adr32_dp() // 4639 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8x(m_dbin, 0xff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=b....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not8(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_w_ds_dp() // 4640 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=2 m=.nzvc  i=.....i. ALU.not_ a=R.dyl:m_da[ry] d=0
	alu_not(m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_w_ais_dp() // 4650 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_w_aips_dp() // 4658 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_w_pais_dp() // 4660 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_w_das_dp() // 4668 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_w_dais_dp() // 4670 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=11 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_w_adr16_dp() // 4678 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_w_adr32_dp() // 4679 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b8 nnmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.....i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_l_ds_dp() // 4680 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 137 nnrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=2 m=.nzvc  i=.l...i. ALU.not_ a=R.dyl:m_da[ry] d=0
	alu_not(m_da[ry]);
	sr_nzvc();
	// 15e nnrl2
	set_16l(m_da[ry], m_aluo);
	// alu r=11 c=3 m=.nzvc  i=.l....f ALU.not_ a=18:m_da[ry] d=0
	alu_not(high16(m_da[ry]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_l_ais_dp() // 4690 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.l...i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=11 c=3 m=.nzvc  i=.l....f ALU.not_ a=alub d=0
	alu_not(m_alub);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_l_aips_dp() // 4698 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.l...i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=11 c=3 m=.nzvc  i=.l....f ALU.not_ a=alub d=0
	alu_not(m_alub);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_l_pais_dp() // 46a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.l...i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=11 c=3 m=.nzvc  i=.l....f ALU.not_ a=alub d=0
	alu_not(m_alub);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_l_das_dp() // 46a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.l...i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=11 c=3 m=.nzvc  i=.l....f ALU.not_ a=alub d=0
	alu_not(m_alub);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_l_dais_dp() // 46b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=11 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.l...i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=11 c=3 m=.nzvc  i=.l....f ALU.not_ a=alub d=0
	alu_not(m_alub);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_l_adr16_dp() // 46b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.l...i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=11 c=3 m=.nzvc  i=.l....f ALU.not_ a=alub d=0
	alu_not(m_alub);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::not_l_adr32_dp() // 46b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2bc nnml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=11 c=2 m=.nzvc  i=.l...i. ALU.not_ a=R.dbin:m_dbin d=0
	alu_not(m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15d nnml2
	m_aob = m_at;
	m_dbout = m_aluo;
	m_au = m_at - 2;
	// alu r=11 c=3 m=.nzvc  i=.l....f ALU.not_ a=alub d=0
	alu_not(m_alub);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_ds_sr_dp() // 46c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 301 rstw1
	m_movemr = m_dbin;
	m_ftu = m_da[ry];
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_ais_sr_dp() // 46d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_aips_sr_dp() // 46d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_pais_sr_dp() // 46e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_das_sr_dp() // 46e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_dais_sr_dp() // 46f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 1e3 aixl0
	// alu r=11 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_adr16_sr_dp() // 46f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_adr32_sr_dp() // 46f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_dpc_sr_dp() // 46fa ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_dpci_sr_dp() // 46fb ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 1e3 aixl0
	// alu r=11 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 159 mstw1
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_i16u_sr_dp() // 46fc ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 301 rstw1
	m_movemr = m_dbin;
	m_ftu = m_dt;
	m_au = m_au - 2;
	m_icount -= 2;
	// 321 stiw4
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_icount -= 2;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nbcd_b_ds_dp() // 4800 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 13b nbcr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dyl:m_da[ry] d=0
	alu_sbcd8(m_da[ry], 0x0000);
	sr_xnzvc_u();
	// 117 nbcr2
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nbcd_b_ais_dp() // 4810 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 15c nbcm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dbin:m_dbin d=0
	alu_sbcd8(m_dbin, 0x0000);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nbcd_b_aips_dp() // 4818 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 15c nbcm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dbin:m_dbin d=0
	alu_sbcd8(m_dbin, 0x0000);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nbcd_b_pais_dp() // 4820 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 15c nbcm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dbin:m_dbin d=0
	alu_sbcd8(m_dbin, 0x0000);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nbcd_b_das_dp() // 4828 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 15c nbcm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dbin:m_dbin d=0
	alu_sbcd8(m_dbin, 0x0000);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nbcd_b_dais_dp() // 4830 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=9 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 15c nbcm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dbin:m_dbin d=0
	alu_sbcd8(m_dbin, 0x0000);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nbcd_b_adr16_dp() // 4838 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 15c nbcm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dbin:m_dbin d=0
	alu_sbcd8(m_dbin, 0x0000);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nbcd_b_adr32_dp() // 4839 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 15c nbcm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dbin:m_dbin d=0
	alu_sbcd8(m_dbin, 0x0000);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::swap_ds_dp() // 4840 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 341 swap1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[ry];
	m_pc = m_au;
	set_16h(m_at, m_da[ry]);
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nzvc();
	// 342 swap2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[ry] = merge_16_32(high16(m_at), m_aluo);
	m_au = m_au + 2;
	// alu r=9 c=1 m=.nz..  i=......f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::pea_ais_dp() // 4850 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 17c peaa1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_da[m_sp] - 4;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 106 peax6
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::pea_das_dp() // 4868 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 17d pead1
	m_aob = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 17e pead2
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_at;
	// 17f pead3
	m_at = m_au;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 106 peax6
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::pea_dais_dp() // 4870 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1ff peax0
	// alu r=9 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3ee peax1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto peax3;
	else
		goto peax2;
peax2:
	// 134 peax2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto peax4;
peax3:
	// 1f4 peax3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto peax4;
peax4:
	// 218 peax4
	m_ir = m_irc;
	m_at = m_au;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_pc + 4;
	m_icount -= 2;
	// 219 peax5
	m_aob = m_au;
	m_pc = m_au;
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 106 peax6
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::pea_adr16_dp() // 4878 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 178 paaw1
	m_aob = m_au;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 10a paaw2
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::pea_adr32_dp() // 4879 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1fa paal1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15f paal2
	m_aob = m_au;
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 10a paaw2
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 348 mawl3
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::pea_dpc_dp() // 487a ffff
{
	switch(m_inst_substate) {
	case 0:
	// 17d pead1
	m_aob = m_au;
	m_at = m_pc;
	m_au = m_au + 2;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 17e pead2
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_aluo) + m_at;
	// 17f pead3
	m_at = m_au;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 106 peax6
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::pea_dpci_dp() // 487b ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1ff peax0
	// alu r=9 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3ee peax1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto peax3;
	else
		goto peax2;
peax2:
	// 134 peax2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto peax4;
peax3:
	// 1f4 peax3
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto peax4;
peax4:
	// 218 peax4
	m_ir = m_irc;
	m_at = m_au;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_pc + 4;
	m_icount -= 2;
	// 219 peax5
	m_aob = m_au;
	m_pc = m_au;
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 106 peax6
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ext_w_ds_dp() // 4880 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 133 nnrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=8 c=2 m=.nzvc  i=.l...i. ALU.ext a=R.dyl:m_da[ry] d=0
	alu_ext(m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_list_ais_dp() // 4890 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3a0 stmr1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// 323 stmr2
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
stmr5:
	// 0a5 stmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_listp_pais_dp() // 48a0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3a4 push1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// 21e push2
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_da[ry] - 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	step_movem_predec();
	if(m_t)
		goto push3;
	else
		goto push5;
push5:
	// 083 push5
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_at = m_au;
	m_au = m_au - 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem_predec();
	if(m_t)
		goto push3;
	else
		goto push5;
push3:
	// 043 push3
	m_aob = m_pc;
	m_ir = m_irc;
	m_da[ry] = m_at;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_list_das_dp() // 48a8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1f1 stmd1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3c9 stmd2
	m_aob = m_au;
	m_at = ext32(m_dbin);
	m_au = m_au + 2;
	// 322 stmd3
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_da[ry] + ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
stmr5:
	// 0a5 stmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_list_dais_dp() // 48b0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 325 stmx1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 326 stmx2
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	m_au = m_au - 2;
	// alu r=8 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 02f stmx3
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto stmx5;
	else
		goto stmx4;
stmx4:
	// 138 stmx4
	m_t = !m_movemr;
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
stmx5:
	// 1f8 stmx5
	m_t = !m_movemr;
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
stmr5:
	// 0a5 stmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_list_adr16_dp() // 48b8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1ed smaw1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3c1 smaw2
	m_aob = m_au;
	m_at = ext32(m_dbin);
	m_au = m_au + 2;
	// 04b smaw3
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
stmr5:
	// 0a5 stmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_list_adr32_dp() // 48b9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e5 smal1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 112 smal2
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 305 smal3
	m_aob = m_au;
	set_16l(m_at, m_dbin);
	m_au = m_au + 2;
	// 04b smaw3
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
stmr5:
	// 0a5 stmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr5;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ext_l_ds_dp() // 48c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 232 extr1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=8 c=3 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	// 233 extr2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[ry] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_list_ais_dp() // 48d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3a0 stmr1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// 323 stmr2
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
stmr4:
	// 0e5 stmr4
	m_aob = m_au;
	m_dbout = high16(m_da[m_movems]);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ad stmr6
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_listp_pais_dp() // 48e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3a4 push1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// 21e push2
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_da[ry] - 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	step_movem_predec();
	if(m_t)
		goto push3;
	else
		goto push4;
push4:
	// 0c3 push4
	m_aob = m_au;
	m_dbout = m_da[m_movems];
	m_at = m_au;
	m_au = m_au - 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 21f push5
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = high16(m_da[m_movems]);
	m_at = m_au;
	m_au = m_au - 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem_predec();
	if(m_t)
		goto push3;
	else
		goto push4;
push3:
	// 043 push3
	m_aob = m_pc;
	m_ir = m_irc;
	m_da[ry] = m_at;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_list_das_dp() // 48e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1f1 stmd1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3c9 stmd2
	m_aob = m_au;
	m_at = ext32(m_dbin);
	m_au = m_au + 2;
	// 322 stmd3
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_da[ry] + ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
stmr4:
	// 0e5 stmr4
	m_aob = m_au;
	m_dbout = high16(m_da[m_movems]);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ad stmr6
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_list_dais_dp() // 48f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 325 stmx1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 326 stmx2
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	m_au = m_au - 2;
	// alu r=8 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 02f stmx3
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto stmx5;
	else
		goto stmx4;
stmx4:
	// 138 stmx4
	m_t = !m_movemr;
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
stmx5:
	// 1f8 stmx5
	m_t = !m_movemr;
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
stmr4:
	// 0e5 stmr4
	m_aob = m_au;
	m_dbout = high16(m_da[m_movems]);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ad stmr6
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_list_adr16_dp() // 48f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1ed smaw1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3c1 smaw2
	m_aob = m_au;
	m_at = ext32(m_dbin);
	m_au = m_au + 2;
	// 04b smaw3
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
stmr4:
	// 0e5 stmr4
	m_aob = m_au;
	m_dbout = high16(m_da[m_movems]);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ad stmr6
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_list_adr32_dp() // 48f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e5 smal1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 112 smal2
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 305 smal3
	m_aob = m_au;
	set_16l(m_at, m_dbin);
	m_au = m_au + 2;
	// 04b smaw3
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
stmr4:
	// 0e5 stmr4
	m_aob = m_au;
	m_dbout = high16(m_da[m_movems]);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ad stmr6
	m_aob = m_au;
	m_t = !m_movemr;
	m_dbout = m_da[m_movems];
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	step_movem();
	if(m_t)
		goto mmrw2;
	else
		goto stmr4;
mmrw2:
	// 025 mmrw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_b_ds_dp() // 4a00 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 12d tsrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_b_ais_dp() // 4a10 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_b_aips_dp() // 4a18 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or8(m_da[m_movems], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_b_pais_dp() // 4a20 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or8(m_da[m_movems], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_b_das_dp() // 4a28 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_b_dais_dp() // 4a30 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_b_adr16_dp() // 4a38 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or8(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_b_adr32_dp() // 4a39 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or8(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_w_ds_dp() // 4a40 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 12d tsrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_w_ais_dp() // 4a50 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_w_aips_dp() // 4a58 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or(m_da[m_movems], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_w_pais_dp() // 4a60 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or(m_da[m_movems], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_w_das_dp() // 4a68 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_w_dais_dp() // 4a70 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_w_adr16_dp() // 4a78 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_w_adr32_dp() // 4a79 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c3 tsmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_l_ds_dp() // 4a80 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 125 tsrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	// 362 tsrl2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=1 m=.nz..  i=.l....f ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_l_ais_dp() // 4a90 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=15 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3cb tsml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 361 tsml2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_l_aips_dp() // 4a98 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=15 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3cb tsml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 361 tsml2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_l_pais_dp() // 4aa0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=15 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3cb tsml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 361 tsml2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_l_das_dp() // 4aa8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3cb tsml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 361 tsml2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_l_dais_dp() // 4ab0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=15 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3cb tsml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 361 tsml2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_l_adr16_dp() // 4ab8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3cb tsml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 361 tsml2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tst_l_adr32_dp() // 4ab9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3cb tsml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 361 tsml2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tas_ds_dp() // 4ac0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 345 tasr1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[ry];
	m_pc = m_au;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dyl:m_da[ry]
	alu_or8(m_ftu, m_da[ry]);
	// 346 tasr2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_au + 2;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tas_ais_dp() // 4ad0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0 && access_to_be_redone()) {
		m_icount += 4;
		m_inst_substate = 1;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 343 tasm1
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_or8(m_ftu, m_dbin);
	m_icount -= 2;
	// 344 tasm2
	m_aob = m_au;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	if(!m_tas_write_callback.isnull())
		m_tas_write_callback(m_aob, m_dbout);
	else
		m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tas_aips_dp() // 4ad8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[m_movems];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or8(m_da[m_movems], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0 && access_to_be_redone()) {
		m_icount += 4;
		m_inst_substate = 1;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 343 tasm1
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_or8(m_ftu, m_dbin);
	m_icount -= 2;
	// 344 tasm2
	m_aob = m_au;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	if(!m_tas_write_callback.isnull())
		m_tas_write_callback(m_aob, m_dbout);
	else
		m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tas_pais_dp() // 4ae0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or8(m_da[m_movems], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0 && access_to_be_redone()) {
		m_icount += 4;
		m_inst_substate = 1;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 343 tasm1
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_or8(m_ftu, m_dbin);
	m_icount -= 2;
	// 344 tasm2
	m_aob = m_au;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	if(!m_tas_write_callback.isnull())
		m_tas_write_callback(m_aob, m_dbout);
	else
		m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tas_das_dp() // 4ae8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0 && access_to_be_redone()) {
		m_icount += 4;
		m_inst_substate = 3;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 343 tasm1
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_or8(m_ftu, m_dbin);
	m_icount -= 2;
	// 344 tasm2
	m_aob = m_au;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	if(!m_tas_write_callback.isnull())
		m_tas_write_callback(m_aob, m_dbout);
	else
		m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tas_dais_dp() // 4af0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[m_movems];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0 && access_to_be_redone()) {
		m_icount += 4;
		m_inst_substate = 3;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 343 tasm1
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_or8(m_ftu, m_dbin);
	m_icount -= 2;
	// 344 tasm2
	m_aob = m_au;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	if(!m_tas_write_callback.isnull())
		m_tas_write_callback(m_aob, m_dbout);
	else
		m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tas_adr16_dp() // 4af8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or8(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0 && access_to_be_redone()) {
		m_icount += 4;
		m_inst_substate = 3;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 343 tasm1
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_or8(m_ftu, m_dbin);
	m_icount -= 2;
	// 344 tasm2
	m_aob = m_au;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	if(!m_tas_write_callback.isnull())
		m_tas_write_callback(m_aob, m_dbout);
	else
		m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::tas_adr32_dp() // 4af9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[m_movems];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.moveml:m_da[m_movems] d=R.dbin:m_dbin
	alu_or8(m_da[m_movems], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0 && access_to_be_redone()) {
		m_icount += 4;
		m_inst_substate = 5;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 343 tasm1
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_or8(m_ftu, m_dbin);
	m_icount -= 2;
	// 344 tasm2
	m_aob = m_au;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc;
	// alu r=15 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	if(!m_tas_write_callback.isnull())
		m_tas_write_callback(m_aob, m_dbout);
	else
		m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_ais_list_dp() // 4c90 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 127 ldmr1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 111 ldmr2
	m_aob = m_da[ry];
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
ldmr4:
	// 3a8 ldmr4
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	m_da[m_movems] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_aips_list_dp() // 4c98 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 123 popm1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 115 popm2
	m_aob = m_da[ry];
	m_ir = m_irc;
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto popm6;
	else
		goto popm4;
popm4:
	// 3ac popm4
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	m_da[m_movems] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto popm6;
	else
		goto popm4;
popm6:
	// 32c popm6
	m_aob = m_pc;
	m_da[ry] = m_at;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_das_list_dp() // 4ca8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1fd ldmd1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2f6 ldmd2
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// 276 ldmd3
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 237 ldmd4
	m_aob = m_at;
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
ldmr4:
	// 3a8 ldmr4
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	m_da[m_movems] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_dais_list_dp() // 4cb0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1f5 ldmx0
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 027 ldmx1
	// alu r=0 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 02b ldmx2
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto ldmx4;
	else
		goto ldmx3;
ldmx3:
	// 021 ldmx3
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto ldmx5;
ldmx4:
	// 0e1 ldmx4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto ldmx5;
ldmx5:
	// 02e ldmx5
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=0 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 277 ldmx6
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
ldmr4:
	// 3a8 ldmr4
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	m_da[m_movems] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_adr16_list_dp() // 4cb8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1f9 lmaw1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 30e lmaw2
	m_aob = m_au;
	m_dt = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 111 ldmr2
	m_aob = m_dt;
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_dt;
	m_au = m_dt + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
ldmr4:
	// 3a8 ldmr4
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	m_da[m_movems] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_adr32_list_dp() // 4cb9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e9 lmal1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 0af lmal2
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ee lmal3
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 111 ldmr2
	m_aob = m_dt;
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_dt;
	m_au = m_dt + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
ldmr4:
	// 3a8 ldmr4
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	m_da[m_movems] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_dpc_list_dp() // 4cba ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1fd ldmd1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2f6 ldmd2
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// 276 ldmd3
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 237 ldmd4
	m_aob = m_at;
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
ldmr4:
	// 3a8 ldmr4
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	m_da[m_movems] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_w_dpci_list_dp() // 4cbb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1f5 ldmx0
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 027 ldmx1
	// alu r=0 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 02b ldmx2
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto ldmx4;
	else
		goto ldmx3;
ldmx3:
	// 021 ldmx3
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto ldmx5;
ldmx4:
	// 0e1 ldmx4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto ldmx5;
ldmx5:
	// 02e ldmx5
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=0 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 277 ldmx6
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
ldmr4:
	// 3a8 ldmr4
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	m_da[m_movems] = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr4;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_ais_list_dp() // 4cd0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 127 ldmr1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 111 ldmr2
	m_aob = m_da[ry];
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
ldmr3:
	// 3e8 ldmr3
	m_aob = m_au;
	set_16h(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f0 ldmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	set_16l(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_aips_list_dp() // 4cd8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 123 popm1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 115 popm2
	m_aob = m_da[ry];
	m_ir = m_irc;
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto popm6;
	else
		goto popm3;
popm3:
	// 3ec popm3
	m_aob = m_au;
	set_16h(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f4 popm5
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	set_16l(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto popm6;
	else
		goto popm3;
popm6:
	// 32c popm6
	m_aob = m_pc;
	m_da[ry] = m_at;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_das_list_dp() // 4ce8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1fd ldmd1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2f6 ldmd2
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// 276 ldmd3
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 237 ldmd4
	m_aob = m_at;
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
ldmr3:
	// 3e8 ldmr3
	m_aob = m_au;
	set_16h(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f0 ldmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	set_16l(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_dais_list_dp() // 4cf0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1f5 ldmx0
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 027 ldmx1
	// alu r=0 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 02b ldmx2
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto ldmx4;
	else
		goto ldmx3;
ldmx3:
	// 021 ldmx3
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto ldmx5;
ldmx4:
	// 0e1 ldmx4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto ldmx5;
ldmx5:
	// 02e ldmx5
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 277 ldmx6
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
ldmr3:
	// 3e8 ldmr3
	m_aob = m_au;
	set_16h(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f0 ldmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	set_16l(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_adr16_list_dp() // 4cf8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1f9 lmaw1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 30e lmaw2
	m_aob = m_au;
	m_dt = ext32(m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 111 ldmr2
	m_aob = m_dt;
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_dt;
	m_au = m_dt + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
ldmr3:
	// 3e8 ldmr3
	m_aob = m_au;
	set_16h(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f0 ldmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	set_16l(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_adr32_list_dp() // 4cf9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e9 lmal1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 0af lmal2
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ee lmal3
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 111 ldmr2
	m_aob = m_dt;
	m_t = !m_movemr;
	m_pc = m_au;
	m_at = m_dt;
	m_au = m_dt + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
ldmr3:
	// 3e8 ldmr3
	m_aob = m_au;
	set_16h(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f0 ldmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	set_16l(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_dpc_list_dp() // 4cfa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1fd ldmd1
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 2f6 ldmd2
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// 276 ldmd3
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 237 ldmd4
	m_aob = m_at;
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
ldmr3:
	// 3e8 ldmr3
	m_aob = m_au;
	set_16h(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f0 ldmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	set_16l(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::movem_l_dpci_list_dp() // 4cfb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1f5 ldmx0
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 027 ldmx1
	// alu r=0 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 02b ldmx2
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto ldmx4;
	else
		goto ldmx3;
ldmx3:
	// 021 ldmx3
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto ldmx5;
ldmx4:
	// 0e1 ldmx4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	goto ldmx5;
ldmx5:
	// 02e ldmx5
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 277 ldmx6
	m_t = !m_movemr;
	m_pc = m_au;
	m_au = m_at + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
ldmr3:
	// 3e8 ldmr3
	m_aob = m_au;
	set_16h(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f0 ldmr5
	m_aob = m_au;
	m_t = !m_movemr;
	m_at = m_au;
	set_16l(m_da[m_movems], m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	if(m_t)
		goto mmaw2;
	else
		goto ldmr3;
mmaw2:
	// 328 mmaw2
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::trap_imm4_dp() // 4e40 fff0
{
	switch(m_inst_substate) {
	case 0:
	// 1d0 trap1
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 347 trap2
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook((0x80 | ((m_ird & 0xf) << 2)) >> 2);
	m_da[16] = m_au;
	m_ftu = 0x80 | ((m_ird & 0xf) << 2);
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::link_as_imm16_dp() // 4e50 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 30b link1
	m_aob = m_au;
	m_at = m_da[ry];
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ayl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 2b5 link2
	m_pc = m_au;
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 30c link3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = high16(m_at);
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 30d link4
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 349 mmiw2
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[m_sp] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::unlk_as_dp() // 4e58 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 119 unlk1
	m_aob = m_da[ry];
	m_pc = m_au;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	step_movem();
	// 1fe unlk2
	m_aob = m_au;
	m_ir = m_irc;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 27c unlk3
	m_aob = m_pc;
	m_da[m_sp] = m_au;
	m_au = m_pc + 2;
	// 27d unlk4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[ry] = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_as_usp_dp() // 4e60 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 2f5 lusp1
	m_aob = m_au;
	m_ir = m_irc;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_at = m_da[ry];
	m_ftu = m_dbin;
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[15] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::move_usp_as_dp() // 4e68 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 230 susp1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[15];
	m_at = m_da[15];
	m_au = m_da[ry];
	// 233 extr2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[ry] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::reset_dp() // 4e70 ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 3a6 rset1
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	m_icount -= 2;
	// 27b rset2
	m_ir = m_irc;
	m_au = ext32(m_aluo) - 2;
	m_icount -= 2;
	m_reset_cb(1);
	goto rset3;
rset3:
	// 0e4 rset3
	m_au = m_au - 2;
	m_icount -= 2;
	// 114 rset4
	m_t = !(m_au & 0x3f);
	m_icount -= 2;
	if(m_t)
		goto rset5;
	else
		goto rset3;
rset5:
	m_reset_cb(0);
	// 064 rset5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::nop_dp() // 4e71 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::stop_i16u_dp() // 4e72 ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 3a2 stop1
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=0
	alu_and(m_dbin, 0x0000);
	m_icount -= 2;
	// 327 aaa01
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	update_user_super();
	update_interrupt();
	m_au = m_au - 2;
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	debugger_wait_hook();
	return;
	}
}

void m68000_device::rte_dp() // 4e73 ffff
{
	switch(m_inst_substate) {
	case 0:
	if(!(m_sr & SR_S)) {
		m_inst_state = S_PRIVILEDGE;
		return;
	}
	// 12a rtr1
	if(!m_rte_instr_callback.isnull()) (m_rte_instr_callback)(1);
	m_aob = m_da[m_sp];
	m_au = m_da[m_sp] + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 12b rtr2
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3c5 rtr3
	m_aob = m_au;
	m_at = ext32(m_dbin);
	m_au = m_au + 2;
	// 302 rtr4
	set_16h(m_at, m_dbin);
	m_da[m_sp] = m_au;
	m_new_sr = m_isr = m_ftu & (SR_CCR|SR_SR);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_sr = m_new_sr;
	update_user_super();
	update_interrupt();
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b3 jmal2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rts_dp() // 4e75 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 126 rts1
	m_aob = m_da[m_sp];
	m_au = m_da[m_sp] + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 116 rts2
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 303 rts3
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_da[m_sp] = m_au;
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::trapv_dp() // 4e76 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 06d trpv1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_isr & SR_V;
	m_alub = m_dbin;
	m_ftu = m_sr;
	if(m_t)
		goto trpv3;
	else
		goto trpv2;
trpv2:
	// 0e2 trpv2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_pc = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
trpv3:
	// 022 trpv3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_au = m_da[16] - 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x07);
	m_da[16] = m_au;
	m_ftu = 0x001c;
	m_au = m_au + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rtr_dp() // 4e77 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 12a rtr1
	m_aob = m_da[m_sp];
	m_au = m_da[m_sp] + 2;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 12b rtr2
	m_aob = m_au;
	m_movemr = m_dbin;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 3c5 rtr3
	m_aob = m_au;
	m_at = ext32(m_dbin);
	m_au = m_au + 2;
	// 302 rtr4
	set_16h(m_at, m_dbin);
	m_da[m_sp] = m_au;
	m_sr = m_isr = (m_ftu & SR_CCR) | (m_sr & SR_SR);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b3 jmal2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jsr_ais_dp() // 4e90 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 273 jsra1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 271 jsaw2
	m_aob = m_au;
	m_dbout = high16(m_pc);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 272 jsaw3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_pc;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jsr_das_dp() // 4ea8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b0 jsrd1
	m_au = ext32(m_dbin) + m_da[ry];
	m_icount -= 2;
	// 274 jsrd2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 2;
	// 2b1 jsrd3
	m_pc = m_au;
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 271 jsaw2
	m_aob = m_au;
	m_dbout = high16(m_pc);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 272 jsaw3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_pc;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jsr_dais_dp() // 4eb0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1f3 jsrx0
	// alu r=0 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 2b2 jsrx1
	m_t = m_irc & 0x0800;
	m_au = ext32(m_aluo) + m_da[ry];
	m_icount -= 2;
	if(m_t)
		goto jsrx3;
	else
		goto jsrx2;
jsrx2:
	// 029 jsrx2
	m_au = m_au + ext32(m_da[map_sp(m_irc >> 12)]);
	m_icount -= 2;
	goto jsrd2;
jsrx3:
	// 0e9 jsrx3
	m_au = m_au + m_da[map_sp(m_irc >> 12)];
	m_icount -= 2;
	goto jsrd2;
jsrd2:
	// 274 jsrd2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 2;
	// 2b1 jsrd3
	m_pc = m_au;
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 271 jsaw2
	m_aob = m_au;
	m_dbout = high16(m_pc);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 272 jsaw3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_pc;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jsr_adr16_dp() // 4eb8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 293 jsaw0
	m_at = ext32(m_dbin);
	m_icount -= 2;
	// 270 jsaw1
	m_aob = m_at;
	m_pc = m_au;
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 271 jsaw2
	m_aob = m_au;
	m_dbout = high16(m_pc);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 272 jsaw3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_pc;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jsr_adr32_dp() // 4eb9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1f2 jsal1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 256 jsal2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_pc = m_au;
	set_16l(m_at, m_dbin);
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 271 jsaw2
	m_aob = m_au;
	m_dbout = high16(m_pc);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 272 jsaw3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_pc;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jsr_dpc_dp() // 4eba ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b0 jsrd1
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	// 274 jsrd2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 2;
	// 2b1 jsrd3
	m_pc = m_au;
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 271 jsaw2
	m_aob = m_au;
	m_dbout = high16(m_pc);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 272 jsaw3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_pc;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jsr_dpci_dp() // 4ebb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1f3 jsrx0
	// alu r=0 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 2b2 jsrx1
	m_t = m_irc & 0x0800;
	m_au = ext32(m_aluo) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto jsrx3;
	else
		goto jsrx2;
jsrx2:
	// 029 jsrx2
	m_au = m_au + ext32(m_da[map_sp(m_irc >> 12)]);
	m_icount -= 2;
	goto jsrd2;
jsrx3:
	// 0e9 jsrx3
	m_au = m_au + m_da[map_sp(m_irc >> 12)];
	m_icount -= 2;
	goto jsrd2;
jsrd2:
	// 274 jsrd2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 2;
	// 2b1 jsrd3
	m_pc = m_au;
	m_au = m_da[m_sp] - 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 271 jsaw2
	m_aob = m_au;
	m_dbout = high16(m_pc);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 272 jsaw3
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_pc;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jmp_ais_dp() // 4ed0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 255 jmpa1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jmp_das_dp() // 4ee8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2b4 jmpd1
	m_au = ext32(m_dbin) + m_da[ry];
	m_icount -= 2;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jmp_dais_dp() // 4ef0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1f7 jmpx0
	// alu r=0 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 2b6 jmpx1
	m_t = m_irc & 0x0800;
	m_au = ext32(m_aluo) + m_da[ry];
	m_icount -= 2;
	if(m_t)
		goto jmpx3;
	else
		goto jmpx2;
jmpx2:
	// 02d jmpx2
	m_au = m_au + ext32(m_da[map_sp(m_irc >> 12)]);
	m_icount -= 2;
	goto bbci3;
jmpx3:
	// 0ed jmpx3
	m_au = m_au + m_da[map_sp(m_irc >> 12)];
	m_icount -= 2;
	goto bbci3;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jmp_adr16_dp() // 4ef8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 297 jmaw1
	m_at = ext32(m_dbin);
	m_icount -= 2;
	// 2b3 jmal2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jmp_adr32_dp() // 4ef9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1f6 jmal1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b3 jmal2
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jmp_dpc_dp() // 4efa ffff
{
	switch(m_inst_substate) {
	case 0:
	// 2b4 jmpd1
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::jmp_dpci_dp() // 4efb ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1f7 jmpx0
	// alu r=0 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 2b6 jmpx1
	m_t = m_irc & 0x0800;
	m_au = ext32(m_aluo) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto jmpx3;
	else
		goto jmpx2;
jmpx2:
	// 02d jmpx2
	m_au = m_au + ext32(m_da[map_sp(m_irc >> 12)]);
	m_icount -= 2;
	goto bbci3;
jmpx3:
	// 0ed jmpx3
	m_au = m_au + m_da[map_sp(m_irc >> 12)];
	m_icount -= 2;
	goto bbci3;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_b_imm3_ds_dp() // 5000 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2d8 raqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.ftu:m_ftu d=R.dyl:m_da[ry]
	alu_add8(m_ftu, m_da[ry]);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_b_imm3_ais_dp() // 5010 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_b_imm3_aips_dp() // 5018 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_b_imm3_pais_dp() // 5020 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_b_imm3_das_dp() // 5028 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_b_imm3_dais_dp() // 5030 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_b_imm3_adr16_dp() // 5038 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_b_imm3_adr32_dp() // 5039 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_ds_dp() // 5040 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2d8 raqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ftu:m_ftu d=R.dyl:m_da[ry]
	alu_add(m_ftu, m_da[ry]);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_as_dp() // 5048 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2dc raql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.ftu:m_ftu d=R.ayl:m_da[ry]
	alu_add(m_ftu, m_da[ry]);
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=23:m_dt d=17:m_da[ry]
	alu_addc(high16(m_dt), high16(m_da[ry]));
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_ais_dp() // 5050 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_aips_dp() // 5058 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_pais_dp() // 5060 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_das_dp() // 5068 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_dais_dp() // 5070 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_adr16_dp() // 5078 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_w_imm3_adr32_dp() // 5079 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_ds_dp() // 5080 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2dc raql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.dyl:m_da[ry]
	alu_add(m_ftu, m_da[ry]);
	sr_xnzvc();
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=18:m_da[ry]
	alu_addc(high16(m_dt), high16(m_da[ry]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_as_dp() // 5088 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2dc raql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=2 c=2 m=.....  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.ayl:m_da[ry]
	alu_add(m_ftu, m_da[ry]);
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=2 c=3 m=.....  i=.l....f ALU.addc a=23:m_dt d=17:m_da[ry]
	alu_addc(high16(m_dt), high16(m_da[ry]));
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_ais_dp() // 5090 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_aips_dp() // 5098 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_pais_dp() // 50a0 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_das_dp() // 50a8 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_dais_dp() // 50b0 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_adr16_dp() // 50b8 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addq_l_imm3_adr32_dp() // 50b9 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_add(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=R.alue:m_alue
	alu_addc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::st_ds_dp() // 50c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 1;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbt_ds_rel16_dp() // 50c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = 1;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::st_ais_dp() // 50d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 1;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::st_aips_dp() // 50d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 1;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::st_pais_dp() // 50e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 1;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::st_das_dp() // 50e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 1;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::st_dais_dp() // 50f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 1;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::st_adr16_dp() // 50f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 1;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::st_adr32_dp() // 50f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 1;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_b_imm3_ds_dp() // 5100 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2d8 raqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.ftu:m_ftu d=R.dyl:m_da[ry]
	alu_sub8(m_ftu, m_da[ry]);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_b_imm3_ais_dp() // 5110 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_b_imm3_aips_dp() // 5118 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_b_imm3_pais_dp() // 5120 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_b_imm3_das_dp() // 5128 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_b_imm3_dais_dp() // 5130 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_b_imm3_adr16_dp() // 5138 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_b_imm3_adr32_dp() // 5139 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub8(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_ds_dp() // 5140 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2d8 raqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.dyl:m_da[ry]
	alu_sub(m_ftu, m_da[ry]);
	sr_xnzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_as_dp() // 5148 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2dc raql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.ayl:m_da[ry]
	alu_sub(m_ftu, m_da[ry]);
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=23:m_dt d=17:m_da[ry]
	alu_subc(high16(m_dt), high16(m_da[ry]));
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_ais_dp() // 5150 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_aips_dp() // 5158 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_pais_dp() // 5160 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_das_dp() // 5168 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_dais_dp() // 5170 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_adr16_dp() // 5178 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_w_imm3_adr32_dp() // 5179 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f3 maqw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_ds_dp() // 5180 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 2dc raql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.dyl:m_da[ry]
	alu_sub(m_ftu, m_da[ry]);
	sr_xnzvc();
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=18:m_da[ry]
	alu_subc(high16(m_dt), high16(m_da[ry]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_as_dp() // 5188 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 2dc raql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	// alu r=5 c=2 m=.....  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.ayl:m_da[ry]
	alu_sub(m_ftu, m_da[ry]);
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=5 c=3 m=.....  i=.l....f ALU.subc a=23:m_dt d=17:m_da[ry]
	alu_subc(high16(m_dt), high16(m_da[ry]));
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_ais_dp() // 5190 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_aips_dp() // 5198 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_pais_dp() // 51a0 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_das_dp() // 51a8 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_dais_dp() // 51b0 f1f8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=5 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_adr16_dp() // 51b8 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subq_l_imm3_adr32_dp() // 51b9 f1ff
{
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2f7 maql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dt = ext32(m_ftu);
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ftu:m_ftu d=R.dbin:m_dbin
	alu_sub(m_ftu, m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=R.alue:m_alue
	alu_subc(high16(m_dt), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sf_ds_dp() // 51c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbra_ds_rel16_dp() // 51c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = 0;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::sf_ais_dp() // 51d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sf_aips_dp() // 51d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sf_pais_dp() // 51e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sf_das_dp() // 51e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sf_dais_dp() // 51f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sf_adr16_dp() // 51f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sf_adr32_dp() // 51f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::shi_ds_dp() // 52c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbhi_ds_rel16_dp() // 52c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::shi_ais_dp() // 52d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::shi_aips_dp() // 52d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::shi_pais_dp() // 52e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::shi_das_dp() // 52e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::shi_dais_dp() // 52f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::shi_adr16_dp() // 52f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::shi_adr32_dp() // 52f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sls_ds_dp() // 53c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbls_ds_rel16_dp() // 53c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::sls_ais_dp() // 53d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sls_aips_dp() // 53d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sls_pais_dp() // 53e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sls_das_dp() // 53e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sls_dais_dp() // 53f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sls_adr16_dp() // 53f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sls_adr32_dp() // 53f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scc_ds_dp() // 54c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_C);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbcc_ds_rel16_dp() // 54c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = !(m_sr & SR_C);
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::scc_ais_dp() // 54d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_C);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scc_aips_dp() // 54d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_C);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scc_pais_dp() // 54e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_C);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scc_das_dp() // 54e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_C);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scc_dais_dp() // 54f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_C);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scc_adr16_dp() // 54f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_C);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scc_adr32_dp() // 54f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_C);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scs_ds_dp() // 55c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_C;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbcs_ds_rel16_dp() // 55c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = m_sr & SR_C;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::scs_ais_dp() // 55d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_C;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scs_aips_dp() // 55d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_C;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scs_pais_dp() // 55e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_C;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scs_das_dp() // 55e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_C;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scs_dais_dp() // 55f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_C;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scs_adr16_dp() // 55f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_C;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::scs_adr32_dp() // 55f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_C;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sne_ds_dp() // 56c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_Z);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbne_ds_rel16_dp() // 56c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = !(m_sr & SR_Z);
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::sne_ais_dp() // 56d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_Z);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sne_aips_dp() // 56d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_Z);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sne_pais_dp() // 56e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_Z);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sne_das_dp() // 56e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_Z);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sne_dais_dp() // 56f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_Z);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sne_adr16_dp() // 56f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_Z);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sne_adr32_dp() // 56f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_Z);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::seq_ds_dp() // 57c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_Z;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbeq_ds_rel16_dp() // 57c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = m_sr & SR_Z;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::seq_ais_dp() // 57d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_Z;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::seq_aips_dp() // 57d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_Z;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::seq_pais_dp() // 57e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_Z;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::seq_das_dp() // 57e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_Z;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::seq_dais_dp() // 57f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_Z;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::seq_adr16_dp() // 57f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_Z;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::seq_adr32_dp() // 57f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_Z;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svc_ds_dp() // 58c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbvc_ds_rel16_dp() // 58c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = !(m_sr & SR_V);
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::svc_ais_dp() // 58d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svc_aips_dp() // 58d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svc_pais_dp() // 58e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svc_das_dp() // 58e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svc_dais_dp() // 58f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svc_adr16_dp() // 58f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svc_adr32_dp() // 58f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svs_ds_dp() // 59c0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_V;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbvs_ds_rel16_dp() // 59c8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = m_sr & SR_V;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::svs_ais_dp() // 59d0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_V;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svs_aips_dp() // 59d8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_V;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svs_pais_dp() // 59e0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_V;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svs_das_dp() // 59e8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_V;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svs_dais_dp() // 59f0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_V;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svs_adr16_dp() // 59f8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_V;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::svs_adr32_dp() // 59f9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_V;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::spl_ds_dp() // 5ac0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_N);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbpl_ds_rel16_dp() // 5ac8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = !(m_sr & SR_N);
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::spl_ais_dp() // 5ad0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_N);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::spl_aips_dp() // 5ad8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_N);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::spl_pais_dp() // 5ae0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_N);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::spl_das_dp() // 5ae8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_N);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::spl_dais_dp() // 5af0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_N);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::spl_adr16_dp() // 5af8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_N);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::spl_adr32_dp() // 5af9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = !(m_sr & SR_N);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::smi_ds_dp() // 5bc0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_N;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbmi_ds_rel16_dp() // 5bc8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = m_sr & SR_N;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::smi_ais_dp() // 5bd0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_N;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::smi_aips_dp() // 5bd8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_N;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::smi_pais_dp() // 5be0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_N;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::smi_das_dp() // 5be8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_N;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::smi_dais_dp() // 5bf0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_N;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::smi_adr16_dp() // 5bf8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_N;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::smi_adr32_dp() // 5bf9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = m_sr & SR_N;
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sge_ds_dp() // 5cc0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbge_ds_rel16_dp() // 5cc8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::sge_ais_dp() // 5cd0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sge_aips_dp() // 5cd8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sge_pais_dp() // 5ce0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sge_das_dp() // 5ce8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sge_dais_dp() // 5cf0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sge_adr16_dp() // 5cf8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sge_adr32_dp() // 5cf9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::slt_ds_dp() // 5dc0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dblt_ds_rel16_dp() // 5dc8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::slt_ais_dp() // 5dd0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::slt_aips_dp() // 5dd8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::slt_pais_dp() // 5de0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::slt_das_dp() // 5de8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::slt_dais_dp() // 5df0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::slt_adr16_dp() // 5df8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::slt_adr32_dp() // 5df9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sgt_ds_dp() // 5ec0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dbgt_ds_rel16_dp() // 5ec8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::sgt_ais_dp() // 5ed0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sgt_aips_dp() // 5ed8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sgt_pais_dp() // 5ee0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sgt_das_dp() // 5ee8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sgt_dais_dp() // 5ef0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sgt_adr16_dp() // 5ef8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sgt_adr32_dp() // 5ef9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sle_ds_dp() // 5fc0 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 384 sccr1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccr2;
	else
		goto roaw2;
roaw2:
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
sccr2:
	// 0cb sccr2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::dble_ds_rel16_dp() // 5fc8 fff8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 06c dbcc1
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_au = ext32(m_dbin) + m_pc;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_icount -= 2;
	if(m_t)
		goto dbcc6;
	else
		goto dbcc2;
dbcc2:
	// 046 dbcc2
	m_aob = m_au;
	m_alub = m_da[ry];
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=....... ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	// 175 dbcc3
	m_t = m_isr & SR_Z;
	m_pc = m_au;
	m_au = m_at + 2;
	// alu r=15 c=3 m=.....  i=....... ALU.add a=alub d=-1
	alu_add(m_alub, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	if(m_t)
		goto dbcc5;
	else
		goto dbcc4;
dbcc6:
	// 0c6 dbcc6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc4:
	// 0c7 dbcc4
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dbcc5:
	// 007 dbcc5
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto dbcc4;
	}
}

void m68000_device::sle_ais_dp() // 5fd0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sle_aips_dp() // 5fd8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_dt;
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sle_pais_dp() // 5fe0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_dt;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sle_das_dp() // 5fe8 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sle_dais_dp() // 5ff0 fff8
{
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=15 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_dt;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sle_adr16_dp() // 5ff8 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sle_adr32_dp() // 5ff9 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_dt;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=R.dtl:m_dt d=R.dbin:m_dbin
	alu_or8(m_dt, m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 380 sccb1
	m_aob = m_au;
	m_ir = m_irc;
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_pc = m_au;
	// alu r=15 c=1 m=.....  i=b...... ALU.and_ a=none d=0
	alu_and8(0x0000, 0x0000);
	if(m_t)
		goto sccb2;
	else
		goto sccb3;
sccb3:
	// 04f sccb3
	m_pc = m_au;
	m_au = m_at;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto morw2;
sccb2:
	// 0cf sccb2
	m_au = m_at;
	// alu r=15 c=2 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=-1
	alu_or8(m_aluo, 0xff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto morw2;
morw2:
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=15 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bra_rel16_dp() // 6000 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = 1;
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bra_rel8_dp() // 6000 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = 1;
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bsr_rel16_dp() // 6100 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 0a9 bsrw1
	m_at = m_au;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[m_sp] - 4;
	m_icount -= 2;
	// 10e bsrw2
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0aa bsrw3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bsr_rel8_dp() // 6100 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 089 bsri1
	m_at = m_pc;
	m_au = m_da[m_sp] - 4;
	// alu r=0 c=1 m=.....  i=....... ALU.and_ a=R.pcl:m_pc d=-1
	alu_and(m_pc, 0xffff);
	m_icount -= 2;
	// 102 bsri2
	m_aob = m_au;
	m_dbout = high16(m_at);
	m_da[m_sp] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 1:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0a8 bsri3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = ext32(m_ftu) + m_pc;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 3:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bhi_rel16_dp() // 6200 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bhi_rel8_dp() // 6200 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = (m_sr & (SR_C|SR_Z)) == 0;
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bls_rel16_dp() // 6300 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bls_rel8_dp() // 6300 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = (m_sr & (SR_C|SR_Z)) != 0;
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bcc_rel16_dp() // 6400 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = !(m_sr & SR_C);
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bcc_rel8_dp() // 6400 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = !(m_sr & SR_C);
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bcs_rel16_dp() // 6500 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = m_sr & SR_C;
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bcs_rel8_dp() // 6500 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = m_sr & SR_C;
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bne_rel16_dp() // 6600 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = !(m_sr & SR_Z);
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bne_rel8_dp() // 6600 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = !(m_sr & SR_Z);
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::beq_rel16_dp() // 6700 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = m_sr & SR_Z;
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::beq_rel8_dp() // 6700 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = m_sr & SR_Z;
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bvc_rel16_dp() // 6800 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = !(m_sr & SR_V);
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bvc_rel8_dp() // 6800 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = !(m_sr & SR_V);
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bvs_rel16_dp() // 6900 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = m_sr & SR_V;
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bvs_rel8_dp() // 6900 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = m_sr & SR_V;
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bpl_rel16_dp() // 6a00 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = !(m_sr & SR_N);
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bpl_rel8_dp() // 6a00 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = !(m_sr & SR_N);
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bmi_rel16_dp() // 6b00 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = m_sr & SR_N;
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bmi_rel8_dp() // 6b00 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = m_sr & SR_N;
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bge_rel16_dp() // 6c00 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bge_rel8_dp() // 6c00 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = ((m_sr & (SR_N|SR_V)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V)) == 0);
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::blt_rel16_dp() // 6d00 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::blt_rel8_dp() // 6d00 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bgt_rel16_dp() // 6e00 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::bgt_rel8_dp() // 6e00 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = ((m_sr & (SR_N|SR_V|SR_Z)) == (SR_N|SR_V)) || ((m_sr & (SR_N|SR_V|SR_Z)) == 0);
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ble_rel16_dp() // 6f00 ffff
{
	switch(m_inst_substate) {
	case 0:
	// 068 bbcw1
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_au = ext32(m_dbin) + m_pc;
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbcw3;
bbcw3:
	// 085 bbcw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	// 1e1 malw3
	m_aob = m_au;
	m_movemr = m_dbin;
	m_pc = m_au;
	m_ftu = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ble_rel8_dp() // 6f00 ff00
{
	switch(m_inst_substate) {
	case 0:
	// 308 bbci1
	m_t = (m_sr & SR_Z) || ((m_sr & (SR_N|SR_V)) == SR_N) || ((m_sr & (SR_N|SR_V)) == SR_V);
	m_au = m_pc + ext32(m_ftu);
	m_icount -= 2;
	if(m_t)
		goto bbci3;
	else
		goto bbci2;
bbci2:
	// 045 bbci2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	goto b;
bbci3:
	// 0c5 bbci3
	m_aob = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	goto b;
b:
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::moveq_imm8o_dd_dp() // 7000 f100
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 23b rlql1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_da[rx] = ext32(m_ftu);
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	sr_nzvc();
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_ds_dd_dp() // 8000 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_or8(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_ais_dd_dp() // 8010 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_aips_dd_dp() // 8018 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_pais_dd_dp() // 8020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_das_dd_dp() // 8028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dais_dd_dp() // 8030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_adr16_dd_dp() // 8038 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_adr32_dd_dp() // 8039 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dpc_dd_dp() // 803a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dpci_dd_dp() // 803b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_imm8_dd_dp() // 803c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_or8(m_dt, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_ds_dd_dp() // 8040 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_or(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_ais_dd_dp() // 8050 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_aips_dd_dp() // 8058 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_pais_dd_dp() // 8060 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_das_dd_dp() // 8068 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dais_dd_dp() // 8070 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_adr16_dd_dp() // 8078 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_adr32_dd_dp() // 8079 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dpc_dd_dp() // 807a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dpci_dd_dp() // 807b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_imm16_dd_dp() // 807c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_or(m_dt, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_ds_dd_dp() // 8080 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_or(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.aluo:m_aluo
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=18:m_da[ry] d=16:m_da[rx]
	alu_or(high16(m_da[ry]), high16(m_da[rx]));
	sr_nzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_ais_dd_dp() // 8090 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_aips_dd_dp() // 8098 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_pais_dd_dp() // 80a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_das_dd_dp() // 80a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dais_dd_dp() // 80b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=14 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_adr16_dd_dp() // 80b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_adr32_dd_dp() // 80b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dpc_dd_dp() // 80ba f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dpci_dd_dp() // 80bb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=14 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_or(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=alub d=16:m_da[rx]
	alu_or(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_imm32_dd_dp() // 80bc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_or(m_dt, m_da[rx]);
	sr_nzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.aluo:m_aluo
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=23:m_dt d=16:m_da[rx]
	alu_or(high16(m_dt), high16(m_da[rx]));
	sr_nzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_ds_dd_dp() // 80c0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 0a6 dvur1
	m_alub = m_da[ry];
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_da[ry]);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_ais_dd_dp() // 80d0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_aips_dd_dp() // 80d8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_pais_dd_dp() // 80e0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_das_dd_dp() // 80e8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_dais_dd_dp() // 80f0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=1 c=5 m=.....  i=.l.d... ALU.over a=R.dbin:m_dbin d=0
	alu_over(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 23:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 23;
		} else
			m_inst_substate = 24;
		return;
	}
	[[fallthrough]]; case 24:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_adr16_dd_dp() // 80f8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_adr32_dd_dp() // 80f9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 23:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 23;
		} else
			m_inst_substate = 24;
		return;
	}
	[[fallthrough]]; case 24:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_dpc_dd_dp() // 80fa f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_dpci_dd_dp() // 80fb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=1 c=5 m=.....  i=.l.d... ALU.over a=R.dbin:m_dbin d=0
	alu_over(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 23:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 23;
		} else
			m_inst_substate = 24;
		return;
	}
	[[fallthrough]]; case 24:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0a4 dvum1
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divu_w_imm16_dd_dp() // 80fc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 0a6 dvur1
	m_alub = m_dt;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dt);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 213 dvum2
	m_t = m_isr & SR_Z;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=16:m_da[rx]
	alu_sub(m_alub, high16(m_da[rx]));
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvur2;
	else
		goto dvum3;
dvum3:
	// 023 dvum3
	m_t = m_isr & SR_C;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum5;
	else
		goto dvum4;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum5:
	// 291 dvum5
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum8:
	// 252 dvum8
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvumc;
	else
		goto dvumb;
dvum7:
	// 2d2 dvum7
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvum9;
	else
		goto dvum6;
dvumb:
	// 3e9 dvumb
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvume;
	else
		goto dvum6;
dvumc:
	// 369 dvumc
	m_t = m_isr & SR_C;
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvumf;
	else
		goto dvumd;
dvum6:
	// 2d0 dvum6
	m_t = m_isr & SR_N;
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	if(m_t)
		goto dvum7;
	else
		goto dvum8;
dvum9:
	// 250 dvum9
	set_16h(m_da[rx], m_aluo);
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aluo:m_aluo d=0
	alu_and(m_aluo, 0x0000);
	m_icount -= 2;
	goto dvumd;
dvume:
	// 290 dvume
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvum5;
dvumd:
	// 0c0 dvumd
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	m_au = m_pc + 2;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	goto dvum0;
dvumf:
	// 080 dvumf
	m_aob = m_pc;
	m_ir = m_irc;
	m_alub = m_aluo;
	set_16h(m_da[rx], m_at);
	m_au = m_pc + 2;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	goto dvum0;
dvum0:
	// 212 dvum0
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_alue);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.alue:m_alue
	alu_sub(m_alub, m_alue);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sbcd_ds_dd_dp() // 8100 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1cd rbrb1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sbcd8(m_da[ry], m_da[rx]);
	sr_xnzvc_u();
	// 11b rbrb2
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 238 rbrb3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sbcd_pais_paid_dp() // 8108 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 107 asbb1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 135 asbb2
	m_aob = m_au;
	m_da[ry] = m_au;
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 136 asbb3
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 04e asbb4
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_at = m_au;
	m_da[rx] = m_au;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 040 asbb5
	m_aob = m_pc;
	// alu r=9 c=2 m=xnzvc  i=b....i. ALU.sbcd a=alub d=R.dbin:m_dbin
	alu_sbcd8(m_alub, m_dbin);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=9 c=3 m=xnzvc  i=b.....f ALU.sbcd a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dd_ais_dp() // 8110 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dd_aips_dp() // 8118 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dd_pais_dp() // 8120 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dd_das_dp() // 8128 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dd_dais_dp() // 8130 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dd_adr16_dp() // 8138 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_b_dd_adr32_dp() // 8139 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=b....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=b...... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dd_ais_dp() // 8150 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dd_aips_dp() // 8158 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dd_pais_dp() // 8160 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dd_das_dp() // 8168 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dd_dais_dp() // 8170 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=14 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dd_adr16_dp() // 8178 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_w_dd_adr32_dp() // 8179 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=14 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.....i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=....... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dd_ais_dp() // 8190 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=16:m_da[rx] d=R.alue:m_alue
	alu_or(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dd_aips_dp() // 8198 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=16:m_da[rx] d=R.alue:m_alue
	alu_or(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dd_pais_dp() // 81a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=16:m_da[rx] d=R.alue:m_alue
	alu_or(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dd_das_dp() // 81a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=16:m_da[rx] d=R.alue:m_alue
	alu_or(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dd_dais_dp() // 81b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=14 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=16:m_da[rx] d=R.alue:m_alue
	alu_or(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dd_adr16_dp() // 81b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=16:m_da[rx] d=R.alue:m_alue
	alu_or(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::or_l_dd_adr32_dp() // 81b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=14 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=14 c=2 m=.nzvc  i=.l...i. ALU.or_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_or(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=14 c=3 m=.nzvc  i=.l....f ALU.or_ a=16:m_da[rx] d=R.alue:m_alue
	alu_or(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=14 c=0 m=.....  i=.l..... ALU.or_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::divs_w_ds_dd_dp() // 81c0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ae dvs02
	m_alub = m_da[ry];
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_da[ry]);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_ais_dd_dp() // 81d0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_aips_dd_dp() // 81d8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_pais_dd_dp() // 81e0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_das_dd_dp() // 81e8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_dais_dd_dp() // 81f0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=1 c=5 m=.....  i=.l.d... ALU.over a=R.dbin:m_dbin d=0
	alu_over(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 23:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 23;
		} else
			m_inst_substate = 24;
		return;
	}
	[[fallthrough]]; case 24:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_adr16_dd_dp() // 81f8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_adr32_dd_dp() // 81f9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 15:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 23:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 23;
		} else
			m_inst_substate = 24;
		return;
	}
	[[fallthrough]]; case 24:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_dpc_dd_dp() // 81fa f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_dpci_dd_dp() // 81fb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=1 c=5 m=.....  i=.l.d... ALU.over a=R.dbin:m_dbin d=0
	alu_over(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 23:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 23;
		} else
			m_inst_substate = 24;
		return;
	}
	[[fallthrough]]; case 24:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ac dvs01
	m_alub = m_dbin;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 21:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 21;
		} else
			m_inst_substate = 22;
		return;
	}
	[[fallthrough]]; case 22:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::divs_w_imm16_dd_dp() // 81fc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 0ae dvs02
	m_alub = m_dt;
	m_alue = m_da[rx];
	m_pc = m_au;
	set_16h(m_at, m_dt);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.dtl:m_dt d=-1
	alu_and(m_dt, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 0c9 dvs03
	m_t = (m_isr & SR_Z) ? 2 : (m_isr & SR_N) ? 1 : 0;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	if(m_t == 0)
		goto dvs04;
	else if(m_t == 1)
		goto dvs05;
	else
		goto dvur2;
dvs04:
	// 0a3 dvs04
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvs05:
	// 063 dvs05
	m_alub = m_aluo;
	set_16l(m_at, high16(m_da[rx]));
	m_au = merge_16_32(0, m_ftu) + 1;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs06;
dvur2:
	// 0e3 dvur2
	m_ftu = m_sr;
	m_au = m_pc - 2;
	m_icount -= 2;
	// 217 dvur3
	m_sr = (m_sr & ~SR_T) | SR_S;
	update_user_super();
	update_interrupt();
	m_pc = m_au;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.aul:m_au d=-1
	alu_and(m_au, 0xffff);
	m_au = m_da[16] - 2;
	m_icount -= 2;
	// 3c2 trap3
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.ftu:m_ftu d=-1
	alu_and(m_ftu, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 360 trap4
	m_aob = m_au;
	m_dbout = m_aluo;
	debugger_exception_hook(0x05);
	m_da[16] = m_au;
	m_ftu = 0x0014;
	m_au = m_au + 2;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=R.pch:m_pc d=-1
	alu_and(high16(m_pc), 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 0ef trap5
	m_aob = m_au;
	m_dbout = m_aluo;
	m_at = ext32(m_ftu);
	m_au = m_au - 4;
	// alu r=1 c=1 m=.....  i=.l.d... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 367 trap6
	m_aob = m_at;
	m_pc = m_at;
	m_au = m_at + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 11a trap7
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 15:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 15;
		} else
			m_inst_substate = 16;
		return;
	}
	[[fallthrough]]; case 16:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 2b7 trap8
	m_aob = merge_16_32(high16(m_at), m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin) + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 17:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 17;
		} else
			m_inst_substate = 18;
		return;
	}
	[[fallthrough]]; case 18:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	// 11c trap9
	m_icount -= 2;
	// 363 b
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// 34c mmrw3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 19:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 19;
		} else
			m_inst_substate = 20;
		return;
	}
	[[fallthrough]]; case 20:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs06:
	// 176 dvs06
	m_t = m_isr & SR_N;
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.dxl:m_da[rx] d=0
	alu_sub(m_da[rx], 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs10;
	else
		goto dvs07;
dvs07:
	// 042 dvs07
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.atl:m_at
	alu_sub(m_alub, m_at);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs10:
	// 0c2 dvs10
	m_alue = m_aluo;
	// alu r=1 c=3 m=.....  i=.l.d... ALU.subc a=16:m_da[rx] d=0
	alu_subc(high16(m_da[rx]), 0x0000);
	m_icount -= 2;
	// 177 dvs11
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	goto dvs08;
dvs08:
	// 216 dvs08
	m_t = m_isr & SR_C;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs09;
	else
		goto dvumz;
dvumz:
	// 2d5 dvumz
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs09:
	// 295 dvs09
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvuma:
	// 0e6 dvuma
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=1 c=5 m=.nzvc  i=.l.d.i. ALU.over a=none d=none
	alu_over(0x0000);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvs0c:
	// 2d6 dvs0c
	m_t = !(m_au & 0x3f);
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs0e;
	else
		goto dvs0d;
dvs0d:
	// 3ed dvs0d
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs0f;
	else
		goto dvs0a;
dvs0e:
	// 32d dvs0e
	m_t = m_isr & SR_C;
	m_icount -= 2;
	if(m_t)
		goto dvs12;
	else
		goto dvs13;
dvs0a:
	// 2d4 dvs0a
	m_au = m_au - 1;
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs0c;
dvs0f:
	// 294 dvs0f
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.atl:m_at d=-1
	alu_and(m_at, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	goto dvs09;
dvs13:
	// 254 dvs13
	set_16l(m_at, m_aluo);
	// alu r=1 c=6 m=.....  i=.l.d... ALU.sla1 a=R.aluo:m_aluo d=-1
	alu_sla1(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs12:
	// 214 dvs12
	m_au = m_au - 1;
	// alu r=1 c=4 m=.....  i=.l.d... ALU.sla0 a=R.aluo:m_aluo d=-1
	alu_sla0(m_aluo);
	m_icount -= 2;
	goto dvs14;
dvs14:
	// 210 dvs14
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.ath:m_at d=-1
	alu_and(high16(m_at), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	// 211 dvs15
	m_t = m_isr & SR_N;
	m_alub = m_alue;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=16:m_da[rx] d=-1
	alu_and(high16(m_da[rx]), 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1d;
	else
		goto dvs16;
dvs16:
	// 041 dvs16
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1a;
	else
		goto dvs17;
dvs1d:
	// 0c1 dvs1d
	m_t = m_isr & SR_N;
	set_16h(m_at, m_at);
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto dvs1e;
	else
		goto dvs1f;
dvs17:
	// 04d dvs17
	m_aob = m_pc;
	m_ir = m_irc;
	m_t = m_isr & SR_N;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto dvuma;
	else
		goto leaa2;
dvs1a:
	// 0cd dvs1a
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 0ce dvs1b
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvs1c;
	else
		goto dvum4;
dvs1f:
	// 08a dvs1f
	m_ir = m_irc;
	// alu r=1 c=2 m=.nzvc  i=.l.d.i. ALU.sub a=alub d=0
	alu_sub(m_alub, 0x0000);
	sr_nzvc();
	m_icount -= 2;
	// 049 dvs20
	m_aob = m_pc;
	m_t = (m_isr & (SR_Z|SR_N)) != 0;
	set_16l(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc();
	if(m_t)
		goto leaa2;
	else
		goto dvuma;
dvs1e:
	// 0ca dvs1e
	m_t = m_isr & SR_N;
	m_alub = m_aluo;
	set_16l(m_at, m_aluo);
	// alu r=1 c=2 m=.....  i=.l.d... ALU.sub a=R.ath:m_at d=0
	alu_sub(high16(m_at), 0x0000);
	m_icount -= 2;
	if(m_t)
		goto dvum4;
	else
		goto dvs1c;
leaa2:
	// 066 leaa2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_at;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
dvum4:
	// 2d1 dvum4
	m_aob = m_pc;
	m_ir = m_irc;
	m_au = m_pc + 2;
	goto dvuma;
dvs1c:
	// 251 dvs1c
	m_aob = m_pc;
	m_ir = m_irc;
	set_16h(m_at, m_aluo);
	m_au = m_pc + 2;
	// alu r=1 c=1 m=.nzvc  i=.l.d.i. ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nzvc();
	goto leaa2;
	}
}

void m68000_device::sub_b_ds_dd_dp() // 9000 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub8(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_ais_dd_dp() // 9010 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_aips_dd_dp() // 9018 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_pais_dd_dp() // 9020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_das_dd_dp() // 9028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dais_dd_dp() // 9030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_adr16_dd_dp() // 9038 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_adr32_dd_dp() // 9039 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dpc_dd_dp() // 903a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dpci_dd_dp() // 903b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_imm8_dd_dp() // 903c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_sub8(m_dt, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_ds_dd_dp() // 9040 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_as_dd_dp() // 9048 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.ayl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_ais_dd_dp() // 9050 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_aips_dd_dp() // 9058 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_pais_dd_dp() // 9060 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_das_dd_dp() // 9068 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dais_dd_dp() // 9070 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_adr16_dd_dp() // 9078 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_adr32_dd_dp() // 9079 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dpc_dd_dp() // 907a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dpci_dd_dp() // 907b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_imm16_dd_dp() // 907c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_sub(m_dt, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_ds_dd_dp() // 9080 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=18:m_da[ry] d=16:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_as_dd_dp() // 9088 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.ayl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=17:m_da[ry] d=16:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_ais_dd_dp() // 9090 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_aips_dd_dp() // 9098 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_pais_dd_dp() // 90a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_das_dd_dp() // 90a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dais_dd_dp() // 90b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=5 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_adr16_dd_dp() // 90b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_adr32_dd_dp() // 90b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dpc_dd_dp() // 90ba f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dpci_dd_dp() // 90bb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=5 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_imm32_dd_dp() // 90bc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_sub(m_dt, m_da[rx]);
	sr_xnzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=23:m_dt d=16:m_da[rx]
	alu_subc(high16(m_dt), high16(m_da[rx]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_ds_ad_dp() // 90c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c9 rorm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dyl:m_da[ry] d=R.axl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_as_ad_dp() // 90c8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c9 rorm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.ayl:m_da[ry] d=R.axl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_ais_ad_dp() // 90d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_aips_ad_dp() // 90d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_pais_ad_dp() // 90e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_das_ad_dp() // 90e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_dais_ad_dp() // 90f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_adr16_ad_dp() // 90f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_adr32_ad_dp() // 90f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_dpc_ad_dp() // 90fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_dpci_ad_dp() // 90fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_w_imm16_ad_dp() // 90fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c9 rorm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dtl:m_dt d=R.axl:m_da[rx]
	alu_sub(m_dt, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subx_b_ds_dd_dp() // 9100 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_subx8(m_da[ry], m_da[rx]);
	sr_xnzvc_u();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subx_b_pais_paid_dp() // 9108 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 10f asxw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 131 asxw2
	m_aob = m_au;
	m_da[ry] = m_au;
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 132 asxw3
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 04a asxw4
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_at = m_au;
	m_da[rx] = m_au;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 065 asxw5
	m_aob = m_pc;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=b....i. ALU.subx a=alub d=R.dbin:m_dbin
	alu_subx8(m_alub, m_dbin);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dd_ais_dp() // 9110 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dd_aips_dp() // 9118 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dd_pais_dp() // 9120 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dd_das_dp() // 9128 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dd_dais_dp() // 9130 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dd_adr16_dp() // 9138 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_b_dd_adr32_dp() // 9139 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=b....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subx_w_ds_dd_dp() // 9140 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_subx(m_da[ry], m_da[rx]);
	sr_xnzvc_u();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subx_w_pais_paid_dp() // 9148 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 10f asxw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 131 asxw2
	m_aob = m_au;
	m_da[ry] = m_au;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 132 asxw3
	m_au = m_da[rx] - 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 04a asxw4
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_at = m_au;
	m_da[rx] = m_au;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 065 asxw5
	m_aob = m_pc;
	m_au = m_at;
	// alu r=10 c=2 m=xnzvc  i=.....i. ALU.subx a=alub d=R.dbin:m_dbin
	alu_subx(m_alub, m_dbin);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dd_ais_dp() // 9150 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dd_aips_dp() // 9158 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dd_pais_dp() // 9160 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dd_das_dp() // 9168 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dd_dais_dp() // 9170 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dd_adr16_dp() // 9178 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_w_dd_adr32_dp() // 9179 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.....i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subx_l_ds_dd_dp() // 9180 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_subx(m_da[ry], m_da[rx]);
	sr_xnzvc_u();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=18:m_da[ry] d=16:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::subx_l_pais_paid_dp() // 9188 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 10b asxl1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 048 asxl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_au = m_au - 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 139 asxl3
	m_aob = m_au;
	m_da[ry] = m_au;
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 13a asxl4
	m_au = m_da[rx] - 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 04c asxl5
	m_aob = m_au;
	m_alub = m_dbin;
	m_au = m_au - 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 047 asxl6
	m_aob = m_au;
	m_at = m_au;
	m_da[rx] = m_au;
	m_au = m_au + 2;
	// alu r=10 c=2 m=xnzvc  i=.l...i. ALU.subx a=R.aluo:m_aluo d=R.dbin:m_dbin
	alu_subx(m_aluo, m_dbin);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 061 asxl7
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 062 asxl8
	m_aob = m_pc;
	m_au = m_at;
	// alu r=10 c=3 m=xnzvc  i=.l....f ALU.subc a=alub d=R.dbin:m_dbin
	alu_subc(m_alub, m_dbin);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dd_ais_dp() // 9190 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=16:m_da[rx] d=R.alue:m_alue
	alu_subc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dd_aips_dp() // 9198 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=16:m_da[rx] d=R.alue:m_alue
	alu_subc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dd_pais_dp() // 91a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=16:m_da[rx] d=R.alue:m_alue
	alu_subc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dd_das_dp() // 91a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=16:m_da[rx] d=R.alue:m_alue
	alu_subc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dd_dais_dp() // 91b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=5 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=16:m_da[rx] d=R.alue:m_alue
	alu_subc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dd_adr16_dp() // 91b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=16:m_da[rx] d=R.alue:m_alue
	alu_subc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::sub_l_dd_adr32_dp() // 91b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=5 c=2 m=xnzvc  i=.l...i. ALU.sub a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_sub(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=5 c=3 m=xnzvc  i=.l....f ALU.subc a=16:m_da[rx] d=R.alue:m_alue
	alu_subc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_ds_ad_dp() // 91c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dyl:m_da[ry] d=R.axl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=18:m_da[ry] d=15:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_as_ad_dp() // 91c8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.ayl:m_da[ry] d=R.axl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=17:m_da[ry] d=15:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_ais_ad_dp() // 91d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_aips_ad_dp() // 91d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_pais_ad_dp() // 91e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_das_ad_dp() // 91e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_dais_ad_dp() // 91f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_adr16_ad_dp() // 91f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_adr32_ad_dp() // 91f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_dpc_ad_dp() // 91fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_dpci_ad_dp() // 91fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::suba_l_imm32_ad_dp() // 91fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=5 c=2 m=.....  i=.....i. ALU.sub a=R.dtl:m_dt d=R.axl:m_da[rx]
	alu_sub(m_dt, m_da[rx]);
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=5 c=3 m=.....  i=......f ALU.subc a=23:m_dt d=15:m_da[rx]
	alu_subc(high16(m_dt), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_ds_dd_dp() // b000 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1d1 cprw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub8(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_ais_dd_dp() // b010 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_aips_dd_dp() // b018 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_pais_dd_dp() // b020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_das_dd_dp() // b028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_dais_dd_dp() // b030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_adr16_dd_dp() // b038 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_adr32_dd_dp() // b039 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_dpc_dd_dp() // b03a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_dpci_dd_dp() // b03b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_b_imm8_dd_dp() // b03c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1d1 cprw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_sub8(m_dt, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_ds_dd_dp() // b040 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1d1 cprw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_as_dd_dp() // b048 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1d1 cprw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.ayl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_ais_dd_dp() // b050 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_aips_dd_dp() // b058 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_pais_dd_dp() // b060 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_das_dd_dp() // b068 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_dais_dd_dp() // b070 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_adr16_dd_dp() // b078 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_adr32_dd_dp() // b079 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_dpc_dd_dp() // b07a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_dpci_dd_dp() // b07b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d3 cpmw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_w_imm16_dd_dp() // b07c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1d1 cprw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_sub(m_dt, m_da[rx]);
	sr_nzvc();
	// 23a rcaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_ds_dd_dp() // b080 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1d5 cprl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 173 cprl2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=18:m_da[ry] d=16:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_as_dd_dp() // b088 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1d5 cprl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.ayl:m_da[ry] d=R.dxl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 173 cprl2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=17:m_da[ry] d=16:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_ais_dd_dp() // b090 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_aips_dd_dp() // b098 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_pais_dd_dp() // b0a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_das_dd_dp() // b0a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_dais_dd_dp() // b0b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=6 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_adr16_dd_dp() // b0b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_adr32_dd_dp() // b0b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_dpc_dd_dp() // b0ba f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_dpci_dd_dp() // b0bb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=6 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=16:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmp_l_imm32_dd_dp() // b0bc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1d5 cprl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_sub(m_dt, m_da[rx]);
	sr_nzvc();
	// 173 cprl2
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=23:m_dt d=16:m_da[rx]
	alu_subc(high16(m_dt), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_ds_ad_dp() // b0c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1d9 cprm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dyl:m_da[ry] d=R.axl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_as_ad_dp() // b0c8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1d9 cprm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.ayl:m_da[ry] d=R.axl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_ais_ad_dp() // b0d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_aips_ad_dp() // b0d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_pais_ad_dp() // b0e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_das_ad_dp() // b0e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_dais_ad_dp() // b0f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_adr16_ad_dp() // b0f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_adr32_ad_dp() // b0f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_dpc_ad_dp() // b0fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_dpci_ad_dp() // b0fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cf cpmm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_w_imm16_ad_dp() // b0fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1d9 cprm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.axl:m_da[rx]
	alu_sub(m_dt, m_da[rx]);
	sr_nzvc();
	// 174 cprm2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=R.ath:m_at d=15:m_da[rx]
	alu_subc(high16(m_at), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_b_dd_ds_dp() // b100 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dxl:m_da[rx] d=R.dyl:m_da[ry]
	alu_eor8(m_da[rx], m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpm_b_aips_aipd_dp() // b108 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 06b cmmw1
	m_aob = m_da[ry];
	m_pc = m_au;
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 086 cmmw2
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 122 cmmw3
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_au = m_da[rx] + (rx < 15 ? 1 : 2);
	// alu r=6 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 170 cmmw4
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=2 m=.nzvc  i=b....i. ALU.sub a=R.aluo:m_aluo d=R.dbin:m_dbin
	alu_sub8(m_aluo, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_b_dd_ais_dp() // b110 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_b_dd_aips_dp() // b118 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_b_dd_pais_dp() // b120 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_b_dd_das_dp() // b128 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_b_dd_dais_dp() // b130 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_b_dd_adr16_dp() // b138 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_b_dd_adr32_dp() // b139 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=b....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=b...... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_w_dd_ds_dp() // b140 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 100 roaw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dxl:m_da[rx] d=R.dyl:m_da[ry]
	alu_eor(m_da[rx], m_da[ry]);
	sr_nzvc();
	// 08b roaw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpm_w_aips_aipd_dp() // b148 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 06b cmmw1
	m_aob = m_da[ry];
	m_pc = m_au;
	m_au = m_da[ry] + 2;
	// 086 cmmw2
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 122 cmmw3
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_au = m_da[rx] + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 170 cmmw4
	m_aob = m_pc;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.aluo:m_aluo d=R.dbin:m_dbin
	alu_sub(m_aluo, m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_w_dd_ais_dp() // b150 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_w_dd_aips_dp() // b158 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_w_dd_pais_dp() // b160 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_w_dd_das_dp() // b168 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_w_dd_dais_dp() // b170 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=13 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_w_dd_adr16_dp() // b178 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_w_dd_adr32_dp() // b179 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=13 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.....i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=....... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_l_dd_ds_dp() // b180 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 10c roal1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dxl:m_da[rx] d=R.dyl:m_da[ry]
	alu_eor(m_da[rx], m_da[ry]);
	sr_nzvc();
	// 259 roal2
	set_16l(m_da[ry], m_aluo);
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25a roal3
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=16:m_da[rx] d=18:m_da[ry]
	alu_eor(high16(m_da[rx]), high16(m_da[ry]));
	sr_nzvc_u();
	m_icount -= 2;
	// 25b roal4
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpm_l_aips_aipd_dp() // b188 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 06f cmml1
	m_aob = m_da[ry];
	m_pc = m_au;
	m_au = m_da[ry] + 2;
	// 08e cmml2
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 154 cmml3
	m_aob = m_at;
	m_alub = m_dbin;
	m_da[ry] = m_au;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 12e cmml4
	m_aob = m_da[rx];
	m_ir = m_irc;
	m_au = m_da[rx] + 2;
	// alu r=6 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 155 cmml5
	m_aob = m_au;
	m_alue = m_dbin;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 156 cmml6
	m_aob = m_pc;
	m_da[rx] = m_au;
	m_au = m_pc + 2;
	// alu r=6 c=2 m=.nzvc  i=.l...i. ALU.sub a=R.aluo:m_aluo d=R.dbin:m_dbin
	alu_sub(m_aluo, m_dbin);
	sr_nzvc();
	// 157 cmml7
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	// alu r=6 c=3 m=.nzvc  i=.l....f ALU.subc a=alub d=R.alue:m_alue
	alu_subc(m_alub, m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_l_dd_ais_dp() // b190 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=16:m_da[rx] d=R.alue:m_alue
	alu_eor(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_l_dd_aips_dp() // b198 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=16:m_da[rx] d=R.alue:m_alue
	alu_eor(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_l_dd_pais_dp() // b1a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=16:m_da[rx] d=R.alue:m_alue
	alu_eor(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_l_dd_das_dp() // b1a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=16:m_da[rx] d=R.alue:m_alue
	alu_eor(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_l_dd_dais_dp() // b1b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=13 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=16:m_da[rx] d=R.alue:m_alue
	alu_eor(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_l_dd_adr16_dp() // b1b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=16:m_da[rx] d=R.alue:m_alue
	alu_eor(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::eor_l_dd_adr32_dp() // b1b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=13 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=13 c=2 m=.nzvc  i=.l...i. ALU.eor a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_eor(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=13 c=3 m=.nzvc  i=.l....f ALU.eor a=16:m_da[rx] d=R.alue:m_alue
	alu_eor(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=13 c=0 m=.....  i=.l..... ALU.eor a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_ds_ad_dp() // b1c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1d5 cprl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dyl:m_da[ry] d=R.axl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 173 cprl2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=18:m_da[ry] d=15:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_as_ad_dp() // b1c8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1d5 cprl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.ayl:m_da[ry] d=R.axl:m_da[rx]
	alu_sub(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 173 cprl2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=17:m_da[ry] d=15:m_da[rx]
	alu_subc(high16(m_da[ry]), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_ais_ad_dp() // b1d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_aips_ad_dp() // b1d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_pais_ad_dp() // b1e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_das_ad_dp() // b1e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_dais_ad_dp() // b1f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_adr16_ad_dp() // b1f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_adr32_ad_dp() // b1f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_dpc_ad_dp() // b1fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_dpci_ad_dp() // b1fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=6 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=6 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1d7 cpml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_sub(m_dbin, m_da[rx]);
	sr_nzvc();
	// 172 cpml2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=alub d=15:m_da[rx]
	alu_subc(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::cmpa_l_imm32_ad_dp() // b1fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1d5 cprl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=6 c=2 m=.nzvc  i=.....i. ALU.sub a=R.dtl:m_dt d=R.axl:m_da[rx]
	alu_sub(m_dt, m_da[rx]);
	sr_nzvc();
	// 173 cprl2
	// alu r=6 c=3 m=.nzvc  i=......f ALU.subc a=23:m_dt d=15:m_da[rx]
	alu_subc(high16(m_dt), high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_ds_dd_dp() // c000 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_and8(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_ais_dd_dp() // c010 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_aips_dd_dp() // c018 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_pais_dd_dp() // c020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_das_dd_dp() // c028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dais_dd_dp() // c030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_adr16_dd_dp() // c038 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_adr32_dd_dp() // c039 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dpc_dd_dp() // c03a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dpci_dd_dp() // c03b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and8(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_imm8_dd_dp() // c03c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_and8(m_dt, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_ds_dd_dp() // c040 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_and(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_ais_dd_dp() // c050 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_aips_dd_dp() // c058 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_pais_dd_dp() // c060 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_das_dd_dp() // c068 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dais_dd_dp() // c070 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_adr16_dd_dp() // c078 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_adr32_dd_dp() // c079 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dpc_dd_dp() // c07a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dpci_dd_dp() // c07b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_imm16_dd_dp() // c07c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_and(m_dt, m_da[rx]);
	sr_nzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_ds_dd_dp() // c080 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_and(m_da[ry], m_da[rx]);
	sr_nzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.aluo:m_aluo
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=18:m_da[ry] d=16:m_da[rx]
	alu_and(high16(m_da[ry]), high16(m_da[rx]));
	sr_nzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_ais_dd_dp() // c090 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_aips_dd_dp() // c098 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_pais_dd_dp() // c0a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_das_dd_dp() // c0a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dais_dd_dp() // c0b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=4 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_adr16_dd_dp() // c0b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_adr32_dd_dp() // c0b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dpc_dd_dp() // c0ba f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dpci_dd_dp() // c0bb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=4 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_and(m_dbin, m_da[rx]);
	sr_nzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=alub d=16:m_da[rx]
	alu_and(m_alub, high16(m_da[rx]));
	sr_nzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_imm32_dd_dp() // c0bc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_and(m_dt, m_da[rx]);
	sr_nzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.aluo:m_aluo
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=23:m_dt d=16:m_da[rx]
	alu_and(high16(m_dt), high16(m_da[rx]));
	sr_nzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_ds_dd_dp() // c0c0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 15b mulr1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_da[ry];
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_ais_dd_dp() // c0d0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_aips_dd_dp() // c0d8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_pais_dd_dp() // c0e0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_das_dd_dp() // c0e8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_dais_dd_dp() // c0f0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=7 c=5 m=.....  i=.lm.... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_adr16_dd_dp() // c0f8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_adr32_dd_dp() // c0f9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_dpc_dd_dp() // c0fa f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_dpci_dd_dp() // c0fb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=7 c=5 m=.....  i=.lm.... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::mulu_w_imm16_dd_dp() // c0fc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15b mulr1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dt;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm3;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : m_alue & 2 ? 1 : 2;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32mu(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else
		goto mulm4;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::abcd_ds_dd_dp() // c100 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1cd rbrb1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=3 c=2 m=xnzvc  i=b....i. ALU.abcd a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_abcd8(m_da[ry], m_da[rx]);
	sr_xnzvc_u();
	// 11b rbrb2
	m_au = m_at;
	// alu r=3 c=3 m=xnzvc  i=b.....f ALU.add a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 238 rbrb3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::abcd_pais_paid_dp() // c108 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 107 asbb1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 135 asbb2
	m_aob = m_au;
	m_da[ry] = m_au;
	// alu r=3 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 136 asbb3
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 04e asbb4
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_at = m_au;
	m_da[rx] = m_au;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 040 asbb5
	m_aob = m_pc;
	// alu r=3 c=2 m=xnzvc  i=b....i. ALU.abcd a=alub d=R.dbin:m_dbin
	alu_abcd8(m_alub, m_dbin);
	sr_xnzvc_u();
	// 113 asbb6
	m_au = m_at;
	// alu r=3 c=3 m=xnzvc  i=b.....f ALU.add a=R.aluo:m_aluo d=?
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dd_ais_dp() // c110 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dd_aips_dp() // c118 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dd_pais_dp() // c120 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dd_das_dp() // c128 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dd_dais_dp() // c130 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dd_adr16_dp() // c138 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_b_dd_adr32_dp() // c139 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=b....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and8(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::exg_dd_ds_dp() // c140 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 3e3 exge1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = m_da[rx];
	m_au = m_da[ry];
	// 231 exge2
	m_da[rx] = m_au;
	m_da[ry] = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::exg_ad_as_dp() // c148 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e3 exge1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = m_da[rx];
	m_au = m_da[ry];
	// 231 exge2
	m_da[rx] = m_au;
	m_da[ry] = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dd_ais_dp() // c150 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dd_aips_dp() // c158 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dd_pais_dp() // c160 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dd_das_dp() // c168 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dd_dais_dp() // c170 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dd_adr16_dp() // c178 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_w_dd_adr32_dp() // c179 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.....i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::exg_dd_as_dp() // c188 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 3e3 exge1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = m_da[rx];
	m_au = m_da[ry];
	// 231 exge2
	m_da[rx] = m_au;
	m_da[ry] = m_at;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 08d rcal3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dd_ais_dp() // c190 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=16:m_da[rx] d=R.alue:m_alue
	alu_and(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dd_aips_dp() // c198 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=16:m_da[rx] d=R.alue:m_alue
	alu_and(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dd_pais_dp() // c1a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=16:m_da[rx] d=R.alue:m_alue
	alu_and(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dd_das_dp() // c1a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=16:m_da[rx] d=R.alue:m_alue
	alu_and(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dd_dais_dp() // c1b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=4 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=16:m_da[rx] d=R.alue:m_alue
	alu_and(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dd_adr16_dp() // c1b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=16:m_da[rx] d=R.alue:m_alue
	alu_and(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::and_l_dd_adr32_dp() // c1b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=4 c=2 m=.nzvc  i=.l...i. ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=4 c=3 m=.nzvc  i=.l....f ALU.and_ a=16:m_da[rx] d=R.alue:m_alue
	alu_and(high16(m_da[rx]), m_alue);
	sr_nzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::muls_w_ds_dd_dp() // c1c0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 15b mulr1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_da[ry];
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_ais_dd_dp() // c1d0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_aips_dd_dp() // c1d8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_pais_dd_dp() // c1e0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_das_dd_dp() // c1e8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_dais_dd_dp() // c1f0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=7 c=5 m=.....  i=.lm.... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_adr16_dd_dp() // c1f8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_adr32_dd_dp() // c1f9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_dpc_dd_dp() // c1fa f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_dpci_dd_dp() // c1fb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=7 c=5 m=.....  i=.lm.... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=7 c=1 m=.....  i=.lm.... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 15a mulm1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dbin;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::muls_w_imm16_dd_dp() // c1fc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 15b mulr1
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_da[rx];
	m_alue = m_dt;
	m_at = m_au;
	m_au = ext32(m_ftu);
	// alu r=7 c=1 m=.nzvc  i=.lm..i. ALU.and_ a=R.dxl:m_da[rx] d=0
	alu_and(m_da[rx], 0x0000);
	sr_nzvc();
	// 3c4 mulm2
	m_t = m_alue & 1;
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto mulm5;
	else
		goto mulm4;
mulm4:
	// 0e0 mulm4
	m_t = !(m_au & 0x3f) ? 0 : (m_alue & 3) == 1 ? 1 : (m_alue & 3) == 2 ? 2 : 3;
	set_16l(m_pc, m_at);
	m_au = m_au - 1;
	// alu r=7 c=4 m=.nzvc  i=.lm...f ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32ms(m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	if(m_t == 0)
		goto mulm6;
	else if(m_t == 1)
		goto mulm3;
	else if(m_t == 2)
		goto mulm5;
	else
		goto mulm4;
mulm5:
	// 0a0 mulm5
	// alu r=7 c=2 m=.nzvc  i=.lm...f ALU.sub a=alub d=R.aluo:m_aluo
	alu_sub(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
mulm6:
	// 020 mulm6
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_pc, high16(m_at));
	m_da[rx] = merge_16_32(m_aluo, m_alue);
	m_au = m_at + 2;
	// alu r=7 c=1 m=.nzvc  i=.lm...f ALU.and_ a=R.aluo:m_aluo d=-1
	alu_and(m_aluo, 0xffff);
	sr_nzvc_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
mulm3:
	// 060 mulm3
	// alu r=7 c=3 m=.nzvc  i=.lm...f ALU.add a=alub d=R.aluo:m_aluo
	alu_add(m_alub, m_aluo);
	sr_nzvc_u();
	m_icount -= 2;
	goto mulm4;
	}
}

void m68000_device::add_b_ds_dd_dp() // d000 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_add8(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_ais_dd_dp() // d010 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_aips_dd_dp() // d018 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_pais_dd_dp() // d020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_das_dd_dp() // d028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dais_dd_dp() // d030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_adr16_dd_dp() // d038 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_adr32_dd_dp() // d039 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dpc_dd_dp() // d03a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dpci_dd_dp() // d03b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add8(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_imm8_dd_dp() // d03c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_add8(m_dt, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_ds_dd_dp() // d040 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_add(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_as_dd_dp() // d048 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.ayl:m_da[ry] d=R.dxl:m_da[rx]
	alu_add(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_ais_dd_dp() // d050 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_aips_dd_dp() // d058 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_pais_dd_dp() // d060 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_das_dd_dp() // d068 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dais_dd_dp() // d070 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_adr16_dd_dp() // d078 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_adr32_dd_dp() // d079 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dpc_dd_dp() // d07a f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dpci_dd_dp() // d07b f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c3 romw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_imm16_dd_dp() // d07c f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_add(m_dt, m_da[rx]);
	sr_xnzvc();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_ds_dd_dp() // d080 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_add(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=18:m_da[ry] d=16:m_da[rx]
	alu_addc(high16(m_da[ry]), high16(m_da[rx]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_as_dd_dp() // d088 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.ayl:m_da[ry] d=R.dxl:m_da[rx]
	alu_add(m_da[ry], m_da[rx]);
	sr_xnzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=17:m_da[ry] d=16:m_da[rx]
	alu_addc(high16(m_da[ry]), high16(m_da[rx]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_ais_dd_dp() // d090 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_aips_dd_dp() // d098 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_pais_dd_dp() // d0a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_das_dd_dp() // d0a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dais_dd_dp() // d0b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_adr16_dd_dp() // d0b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_adr32_dd_dp() // d0b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dpc_dd_dp() // d0ba f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dpci_dd_dp() // d0bb f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dbin:m_dbin d=R.dxl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	sr_xnzvc();
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=alub d=16:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_imm32_dd_dp() // d0bc f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dtl:m_dt d=R.dxl:m_da[rx]
	alu_add(m_dt, m_da[rx]);
	sr_xnzvc();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=23:m_dt d=16:m_da[rx]
	alu_addc(high16(m_dt), high16(m_da[rx]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_ds_ad_dp() // d0c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c9 rorm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dyl:m_da[ry] d=R.axl:m_da[rx]
	alu_add(m_da[ry], m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_as_ad_dp() // d0c8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c9 rorm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.ayl:m_da[ry] d=R.axl:m_da[rx]
	alu_add(m_da[ry], m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_ais_ad_dp() // d0d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_aips_ad_dp() // d0d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = 0;
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_pais_ad_dp() // d0e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_das_ad_dp() // d0e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_dais_ad_dp() // d0f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_adr16_ad_dp() // d0f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_adr32_ad_dp() // d0f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_dpc_ad_dp() // d0fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_dpci_ad_dp() // d0fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = 0;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1c7 romm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_w_imm16_ad_dp() // d0fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c9 rorm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dtl:m_dt d=R.axl:m_da[rx]
	alu_add(m_dt, m_da[rx]);
	// 3c8 rorm2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25f rorm3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=R.ath:m_at d=15:m_da[rx]
	alu_addc(high16(m_at), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addx_b_ds_dd_dp() // d100 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=12 c=2 m=xnzvc  i=b....i. ALU.addx a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_addx8(m_da[ry], m_da[rx]);
	sr_xnzvc_u();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=12 c=0 m=.....  i=b...... ALU.addx a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addx_b_pais_paid_dp() // d108 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 10f asxw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	// alu r=12 c=0 m=.....  i=b...... ALU.addx a=none d=R.dbin:m_dbin
	m_icount -= 2;
	// 131 asxw2
	m_aob = m_au;
	m_da[ry] = m_au;
	// alu r=12 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 132 asxw3
	m_au = m_da[rx] - (rx < 15 ? 1 : 2);
	// alu r=12 c=0 m=.....  i=b...... ALU.addx a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 04a asxw4
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_at = m_au;
	m_da[rx] = m_au;
	// alu r=12 c=0 m=.....  i=b...... ALU.addx a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 065 asxw5
	m_aob = m_pc;
	m_au = m_at;
	// alu r=12 c=2 m=xnzvc  i=b....i. ALU.addx a=alub d=R.dbin:m_dbin
	alu_addx8(m_alub, m_dbin);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	// alu r=12 c=0 m=.....  i=b...... ALU.addx a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dd_ais_dp() // d110 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dd_aips_dp() // d118 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + (ry < 15 ? 1 : 2);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dd_pais_dp() // d120 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - (ry < 15 ? 1 : 2);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=alub d=-1
	alu_and8(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dd_das_dp() // d128 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dd_dais_dp() // d130 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=b...... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dd_adr16_dp() // d138 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_b_dd_adr32_dp() // d139 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and8(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1, m_aob & 1 ? 0x00ff : 0xff00);
	if(!(m_aob & 1))
		m_edb >>= 8;
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=b....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add8(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8xl(m_dbout, m_aluo);
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout, (m_aob & 1) ? 0x00ff : 0xff00);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addx_w_ds_dd_dp() // d140 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c1 rorw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=12 c=2 m=xnzvc  i=.....i. ALU.addx a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_addx(m_da[ry], m_da[rx]);
	sr_xnzvc_u();
	// 27a rrgw2
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=12 c=0 m=.....  i=....... ALU.addx a=R.aluo:m_aluo d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addx_w_pais_paid_dp() // d148 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 10f asxw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	// alu r=12 c=0 m=.....  i=....... ALU.addx a=none d=R.dbin:m_dbin
	m_icount -= 2;
	// 131 asxw2
	m_aob = m_au;
	m_da[ry] = m_au;
	// alu r=12 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 132 asxw3
	m_au = m_da[rx] - 2;
	// alu r=12 c=0 m=.....  i=....... ALU.addx a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 04a asxw4
	m_aob = m_au;
	m_ir = m_irc;
	m_alub = m_dbin;
	m_at = m_au;
	m_da[rx] = m_au;
	// alu r=12 c=0 m=.....  i=....... ALU.addx a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 065 asxw5
	m_aob = m_pc;
	m_au = m_at;
	// alu r=12 c=2 m=xnzvc  i=.....i. ALU.addx a=alub d=R.dbin:m_dbin
	alu_addx(m_alub, m_dbin);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=12 c=0 m=.....  i=....... ALU.addx a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dd_ais_dp() // d150 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dd_aips_dp() // d158 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dd_pais_dp() // d160 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dd_das_dp() // d168 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dd_dais_dp() // d170 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dd_adr16_dp() // d178 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_w_dd_adr32_dp() // d179 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 299 morw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.....i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addx_l_ds_dd_dp() // d180 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=12 c=2 m=xnzvc  i=.l...i. ALU.addx a=R.dyl:m_da[ry] d=R.dxl:m_da[rx]
	alu_addx(m_da[ry], m_da[rx]);
	sr_xnzvc_u();
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	// alu r=12 c=0 m=.....  i=.l..... ALU.addx a=none d=R.aluo:m_aluo
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=12 c=3 m=xnzvc  i=.l....f ALU.addx a=18:m_da[ry] d=16:m_da[rx]
	alu_addx(high16(m_da[ry]), high16(m_da[rx]));
	sr_xnzvc_u();
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	// alu r=12 c=0 m=.....  i=.l..... ALU.addx a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::addx_l_pais_paid_dp() // d188 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 10b asxl1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = 0;
	m_au = m_da[ry] - 2;
	// alu r=12 c=0 m=.....  i=.l..... ALU.addx a=none d=R.dbin:m_dbin
	m_icount -= 2;
	// 048 asxl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_au = m_au - 2;
	// alu r=12 c=0 m=.....  i=.l..... ALU.addx a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 139 asxl3
	m_aob = m_au;
	m_da[ry] = m_au;
	// alu r=12 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 13a asxl4
	m_au = m_da[rx] - 2;
	// alu r=12 c=0 m=.....  i=.l..... ALU.addx a=none d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 04c asxl5
	m_aob = m_au;
	m_alub = m_dbin;
	m_au = m_au - 2;
	// alu r=12 c=0 m=.....  i=.l..... ALU.addx a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 047 asxl6
	m_aob = m_au;
	m_at = m_au;
	m_da[rx] = m_au;
	m_au = m_au + 2;
	// alu r=12 c=2 m=xnzvc  i=.l...i. ALU.addx a=R.aluo:m_aluo d=R.dbin:m_dbin
	alu_addx(m_aluo, m_dbin);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 061 asxl7
	m_aob = m_au;
	m_ir = m_irc;
	m_dbout = m_aluo;
	m_au = ext32(m_dbin);
	// alu r=12 c=0 m=.....  i=.l..... ALU.addx a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 062 asxl8
	m_aob = m_pc;
	m_au = m_at;
	// alu r=12 c=3 m=xnzvc  i=.l....f ALU.addx a=alub d=R.dbin:m_dbin
	alu_addx(m_alub, m_dbin);
	sr_xnzvc_u();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 11:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=12 c=0 m=.....  i=.l..... ALU.addx a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dd_ais_dp() // d190 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=16:m_da[rx] d=R.alue:m_alue
	alu_addc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dd_aips_dp() // d198 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=16:m_da[rx] d=R.alue:m_alue
	alu_addc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dd_pais_dp() // d1a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=16:m_da[rx] d=R.alue:m_alue
	alu_addc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dd_das_dp() // d1a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=16:m_da[rx] d=R.alue:m_alue
	alu_addc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dd_dais_dp() // d1b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=.l..... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 13:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=16:m_da[rx] d=R.alue:m_alue
	alu_addc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dd_adr16_dp() // d1b8 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=16:m_da[rx] d=R.alue:m_alue
	alu_addc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::add_l_dd_adr32_dp() // d1b9 f1ff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 29d morl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_at;
	// alu r=2 c=2 m=xnzvc  i=.l...i. ALU.add a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_add(m_da[rx], m_dbin);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 34d morl2
	m_aob = m_au;
	m_dbout = m_aluo;
	m_au = m_au - 2;
	// alu r=2 c=3 m=xnzvc  i=.l....f ALU.addc a=16:m_da[rx] d=R.alue:m_alue
	alu_addc(high16(m_da[rx]), m_alue);
	sr_xnzvc_u();
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 11:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 11;
		} else
			m_inst_substate = 12;
		return;
	}
	[[fallthrough]]; case 12:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 13:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 13;
		} else
			m_inst_substate = 14;
		return;
	}
	[[fallthrough]]; case 14:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_ds_ad_dp() // d1c0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dyl:m_da[ry] d=R.axl:m_da[rx]
	alu_add(m_da[ry], m_da[rx]);
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=18:m_da[ry] d=15:m_da[rx]
	alu_addc(high16(m_da[ry]), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_as_ad_dp() // d1c8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_da[ry]);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.ayl:m_da[ry] d=R.axl:m_da[rx]
	alu_add(m_da[ry], m_da[rx]);
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=17:m_da[ry] d=15:m_da[rx]
	alu_addc(high16(m_da[ry]), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_ais_ad_dp() // d1d0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00b adrl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_aips_ad_dp() // d1d8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00f pinl1
	m_aob = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 21a pinl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_au + 2;
	// 21b pinl3
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_pais_ad_dp() // d1e0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 179 pdcl1
	m_au = m_da[ry] - 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_icount -= 2;
	// 17a pdcl2
	m_aob = m_au;
	m_da[ry] = m_au;
	m_au = m_au + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_das_ad_dp() // d1e8 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_dais_ad_dp() // d1f0 f1f8
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_adr16_ad_dp() // d1f8 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 00e abww1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_adr32_ad_dp() // d1f9 f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e6 ablw1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 00d ablw2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = 0;
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 008 ablw3
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 005 adrl2
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_dpc_ad_dp() // d1fa f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c6 adsl1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_pc;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_dpci_ad_dp() // d1fb f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e7 aixw0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e6 aixw1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_pc + ext32(m_aluo);
	if(m_t)
		goto aixw4;
	else
		goto aixw2;
aixw2:
	// 124 aixw2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
aixw4:
	// 1e4 aixw4
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsl2;
adsl2:
	// 00c adsl2
	m_aob = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 026 adsl3
	m_aob = m_au;
	m_alub = m_dbin;
	m_alue = m_dbin;
	m_at = m_au;
	m_au = m_pc + 4;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 1cb roml1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dbin);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dbin:m_dbin d=R.axl:m_da[rx]
	alu_add(m_dbin, m_da[rx]);
	// 25c roml2
	set_16l(m_da[rx], m_aluo);
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=alub d=15:m_da[rx]
	alu_addc(m_alub, high16(m_da[rx]));
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::adda_l_imm32_ad_dp() // d1fc f1ff
{
	int rx = map_sp(((m_irdi >> 9) & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 0a7 e#l1
	m_aob = m_au;
	set_16h(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 0ea e#w1
	m_aob = m_au;
	m_pc = m_au;
	set_16h(m_at, m_dbin);
	set_16l(m_dt, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 1c5 rorl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_at = ext32(m_dt);
	// alu r=2 c=2 m=.....  i=.....i. ALU.add a=R.dtl:m_dt d=R.axl:m_da[rx]
	alu_add(m_dt, m_da[rx]);
	// 3c0 rorl2
	set_16l(m_da[rx], m_aluo);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 25e rorl3
	// alu r=2 c=3 m=.....  i=......f ALU.addc a=23:m_dt d=15:m_da[rx]
	alu_addc(high16(m_dt), high16(m_da[rx]));
	m_icount -= 2;
	// 25d roml3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16h(m_da[rx], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_b_imm3_ds_dp() // e000 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=2 c=4 m=xnzvc  i=b....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_b_imm3_ds_dp() // e008 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=5 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=5 c=4 m=xnzvc  i=b....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_b_imm3_ds_dp() // e010 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=8 c=1 m=.....  i=b...r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_and8x(high16(m_da[ry]), 0xff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=8 c=1 m=.nzvc  i=b...ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8x(m_da[ry], 0xff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=8 c=4 m=xnzvc  i=b....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_b_imm3_ds_dp() // e018 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=10 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=10 c=4 m=.nzvc  i=b....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror8(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_b_dd_ds_dp() // e020 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=2 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=2 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=2 c=4 m=xnzvc  i=b....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_b_dd_ds_dp() // e028 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=5 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=5 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=5 c=4 m=xnzvc  i=b....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_b_dd_ds_dp() // e030 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=8 c=1 m=.....  i=b...r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_and8x(high16(m_da[ry]), 0xff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=8 c=1 m=.nzvc  i=b...ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8x(m_da[ry], 0xff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=8 c=4 m=xnzvc  i=b....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_b_dd_ds_dp() // e038 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=10 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=10 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=10 c=4 m=.nzvc  i=b....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror8(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_w_imm3_ds_dp() // e040 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_w_imm3_ds_dp() // e048 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_w_imm3_ds_dp() // e050 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_andx(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_andx(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_w_imm3_ds_dp() // e058 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_w_dd_ds_dp() // e060 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_w_dd_ds_dp() // e068 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_w_dd_ds_dp() // e070 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_andx(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_andx(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_w_dd_ds_dp() // e078 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_l_imm3_ds_dp() // e080 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 385 srrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=2 c=4 m=xnzvc  i=.l...i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_l_imm3_ds_dp() // e088 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 385 srrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=5 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=5 c=4 m=xnzvc  i=.l...i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_l_imm3_ds_dp() // e090 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 385 srrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=8 c=1 m=.....  i=.l..r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_andx(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=8 c=1 m=.nzvc  i=.l..ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_andx(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=8 c=4 m=xnzvc  i=.l...i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=8 c=1 m=.nz..  i=.l..r.f ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_l_imm3_ds_dp() // e098 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 385 srrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=10 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=10 c=4 m=.nzvc  i=.l...i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror32(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_l_dd_ds_dp() // e0a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 386 sril1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=2 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=2 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=2 c=4 m=xnzvc  i=.l...i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_l_dd_ds_dp() // e0a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 386 sril1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=5 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=5 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=5 c=4 m=xnzvc  i=.l...i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_l_dd_ds_dp() // e0b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 386 sril1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=8 c=1 m=.....  i=.l..r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_andx(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=8 c=1 m=.nzvc  i=.l..ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_andx(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=8 c=4 m=xnzvc  i=.l...i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=8 c=1 m=.nz..  i=.l..r.f ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_l_dd_ds_dp() // e0b8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 386 sril1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=10 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=10 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=10 c=4 m=.nzvc  i=.l...i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror32(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_ais_dp() // e0d0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_aips_dp() // e0d8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_pais_dp() // e0e0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_das_dp() // e0e8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_dais_dp() // e0f0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=2 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_adr16_dp() // e0f8 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asr_adr32_dp() // e0f9 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=2 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=2 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=2 c=4 m=xnzvc  i=.....i. ALU.asr a=R.aluo:m_aluo d=-1
	alu_asr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_b_imm3_ds_dp() // e100 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=3 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=3 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=3 c=4 m=xnzvc  i=b....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_b_imm3_ds_dp() // e108 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=4 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=4 c=4 m=xnzvc  i=b....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_b_imm3_ds_dp() // e110 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_and8x(high16(m_da[ry]), 0xff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=11 c=1 m=.nzvc  i=b...ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8x(m_da[ry], 0xff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=11 c=4 m=xnzvc  i=b....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_b_imm3_ds_dp() // e118 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=9 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=9 c=4 m=.nzvc  i=b....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol8(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_b_dd_ds_dp() // e120 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=3 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=3 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=3 c=4 m=xnzvc  i=b....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_b_dd_ds_dp() // e128 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=4 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=4 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=4 c=4 m=xnzvc  i=b....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=b...... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_b_dd_ds_dp() // e130 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=11 c=1 m=.....  i=b...r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_and8x(high16(m_da[ry]), 0xff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=11 c=1 m=.nzvc  i=b...ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8x(m_da[ry], 0xff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=11 c=4 m=xnzvc  i=b....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl8(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_b_dd_ds_dp() // e138 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=9 c=1 m=.....  i=b...... ALU.and_ a=18:m_da[ry] d=-1
	alu_and8(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=9 c=1 m=.nzvc  i=b....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and8(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=9 c=4 m=.nzvc  i=b....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol8(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_8(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_w_imm3_ds_dp() // e140 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_w_imm3_ds_dp() // e148 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_w_imm3_ds_dp() // e150 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_andx(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_andx(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_w_imm3_ds_dp() // e158 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 381 srrw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_w_dd_ds_dp() // e160 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_w_dd_ds_dp() // e168 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_w_dd_ds_dp() // e170 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_andx(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_andx(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_w_dd_ds_dp() // e178 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 382 sriw1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 383 srrw2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
srrw3:
	// 2d3 srrw3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto nbcr3;
	else
		goto srrw3;
nbcr3:
	// 253 nbcr3
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	set_16l(m_da[ry], m_aluo);
	m_au = m_pc + 2;
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_l_imm3_ds_dp() // e180 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 385 srrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=3 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=3 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=3 c=4 m=xnzvc  i=.l...i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=3 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_l_imm3_ds_dp() // e188 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 385 srrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=4 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=4 c=4 m=xnzvc  i=.l...i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=R.alue:m_alue
	alu_and(m_aluo, m_alue);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_l_imm3_ds_dp() // e190 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 385 srrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_andx(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=11 c=1 m=.nzvc  i=.l..ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_andx(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=11 c=4 m=xnzvc  i=.l...i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.nz..  i=.l..r.f ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_l_imm3_ds_dp() // e198 f1f8
{
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 385 srrl1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_ftu);
	// alu r=9 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=9 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=9 c=4 m=.nzvc  i=.l...i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol32(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=9 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_l_dd_ds_dp() // e1a0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 386 sril1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=3 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=3 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=3 c=4 m=xnzvc  i=.l...i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=3 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_l_dd_ds_dp() // e1a8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 386 sril1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=4 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=4 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=4 c=4 m=xnzvc  i=.l...i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	// alu r=4 c=0 m=.....  i=.l..... ALU.and_ a=R.aluo:m_aluo d=R.alue:m_alue
	alu_and(m_aluo, m_alue);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_l_dd_ds_dp() // e1b0 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 386 sril1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=11 c=1 m=.....  i=.l..r.. ALU.and_ a=18:m_da[ry] d=-1
	alu_andx(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=11 c=1 m=.nzvc  i=.l..ri. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_andx(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=11 c=4 m=xnzvc  i=.l...i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl32(m_aluo);
	sr_xnzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.nz..  i=.l..r.f ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_l_dd_ds_dp() // e1b8 f1f8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = m_irdi & 7;
	switch(m_inst_substate) {
	case 0:
	// 386 sril1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = ext32(m_da[rx]);
	// alu r=9 c=1 m=.....  i=.l..... ALU.and_ a=18:m_da[ry] d=-1
	alu_and(high16(m_da[ry]), 0xffff);
	// 387 srrl2
	m_t = !(m_au & 0x3f);
	m_alue = m_aluo;
	m_au = m_au - 1;
	// alu r=9 c=1 m=.nzvc  i=.l...i. ALU.and_ a=R.dyl:m_da[ry] d=-1
	alu_and(m_da[ry], 0xffff);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl3:
	// 2d7 srrl3
	m_t = !(m_au & 0x3f);
	m_au = m_au - 1;
	// alu r=9 c=4 m=.nzvc  i=.l...i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol32(m_aluo);
	sr_nzvc();
	m_icount -= 2;
	if(m_t)
		goto srrl4;
	else
		goto srrl3;
srrl4:
	// 257 srrl4
	m_alub = m_alue;
	m_da[ry] = merge_16_32(m_alue, m_aluo);
	m_icount -= 2;
	// 306 srrl5
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_au = m_pc + 2;
	// alu r=9 c=1 m=.nz..  i=.l....f ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	sr_nz_u();
	set_ftu_const();
	m_icount -= 2;
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_ais_dp() // e1d0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_aips_dp() // e1d8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_pais_dp() // e1e0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_das_dp() // e1e8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_dais_dp() // e1f0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=3 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_adr16_dp() // e1f8 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::asl_adr32_dp() // e1f9 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=3 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=3 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=3 c=4 m=xnzvc  i=.....i. ALU.asl a=R.aluo:m_aluo d=-1
	alu_asl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_ais_dp() // e2d0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_aips_dp() // e2d8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_pais_dp() // e2e0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_das_dp() // e2e8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_dais_dp() // e2f0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=5 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_adr16_dp() // e2f8 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsr_adr32_dp() // e2f9 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=5 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=5 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=5 c=4 m=xnzvc  i=.....i. ALU.lsr a=R.aluo:m_aluo d=-1
	alu_lsr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_ais_dp() // e3d0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_aips_dp() // e3d8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_pais_dp() // e3e0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_das_dp() // e3e8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.dbin:m_dbin
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_dais_dp() // e3f0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=4 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.aluo:m_aluo d=none
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=R.rzl:m_da[map_sp(m_irc >> 12)]
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=none
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_adr16_dp() // e3f8 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::lsl_adr32_dp() // e3f9 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=none
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=R.dxl:m_da[rx] d=R.dbin:m_dbin
	alu_and(m_da[rx], m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=4 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=4 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=4 c=4 m=xnzvc  i=.....i. ALU.lsl a=R.aluo:m_aluo d=-1
	alu_lsl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	// alu r=4 c=0 m=.....  i=....... ALU.and_ a=none d=none
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_ais_dp() // e4d0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_aips_dp() // e4d8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_pais_dp() // e4e0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_das_dp() // e4e8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_dais_dp() // e4f0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=8 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_adr16_dp() // e4f8 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxr_adr32_dp() // e4f9 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=8 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=8 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=8 c=4 m=xnzvc  i=.....i. ALU.roxr a=R.aluo:m_aluo d=-1
	alu_roxr(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_ais_dp() // e5d0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_aips_dp() // e5d8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_pais_dp() // e5e0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=alub d=-1
	alu_andx(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_das_dp() // e5e8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_dais_dp() // e5f0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=11 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_adr16_dp() // e5f8 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::roxl_adr32_dp() // e5f9 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=11 c=1 m=.....  i=....r.. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=11 c=1 m=.nzvc  i=....ri. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_andx(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=11 c=4 m=xnzvc  i=.....i. ALU.roxl a=R.aluo:m_aluo d=-1
	alu_roxl(m_aluo);
	sr_xnzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_ais_dp() // e6d0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_aips_dp() // e6d8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_pais_dp() // e6e0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_das_dp() // e6e8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_dais_dp() // e6f0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=10 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_adr16_dp() // e6f8 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::ror_adr32_dp() // e6f9 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=10 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=10 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=10 c=4 m=.nzvc  i=.....i. ALU.ror a=R.aluo:m_aluo d=-1
	alu_ror(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_ais_dp() // e7d0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 006 adrw1
	m_aob = m_da[ry];
	m_at = m_da[ry];
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_aips_dp() // e7d8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 21c pinw1
	m_aob = m_da[ry];
	m_alub = m_dbin;
	m_dcr = m_da[rx];
	m_at = m_da[ry];
	m_au = m_da[ry] + 2;
	// 21d pinw2
	m_da[ry] = m_au;
	m_au = m_pc + 2;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_pais_dp() // e7e0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 103 pdcw1
	m_alub = m_dbin;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_au = m_da[ry] - 2;
	m_icount -= 2;
	// 17b pdcw2
	m_aob = m_au;
	m_at = m_au;
	m_da[ry] = m_au;
	m_au = m_pc;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=alub d=-1
	alu_and(m_alub, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 5:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_das_dp() // e7e8 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1c2 adsw1
	m_aob = m_au;
	m_au = ext32(m_dbin) + m_da[ry];
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_dais_dp() // e7f0 fff8
{
	int rx = (m_irdi >> 9) & 7;
	int ry = map_sp((m_irdi & 7) | 8);
	switch(m_inst_substate) {
	case 0:
	// 1e3 aixl0
	// alu r=9 c=5 m=.....  i=....... ALU.ext a=R.dbin:m_dbin d=0
	alu_ext(m_dbin);
	m_icount -= 2;
	// 3e2 aixl1
	m_aob = m_au;
	m_t = m_irc & 0x0800;
	m_au = m_da[ry] + ext32(m_aluo);
	if(m_t)
		goto aixl5;
	else
		goto aixl2;
aixl2:
	// 120 aixl2
	m_au = ext32(m_da[map_sp(m_irc >> 12)]) + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
aixl5:
	// 1e0 aixl5
	m_au = m_da[map_sp(m_irc >> 12)] + m_au;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 9:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	step_movem();
	goto adsw2;
adsw2:
	// 02a adsw2
	m_aob = m_au;
	m_at = m_au;
	m_au = m_pc + 4;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	// 024 adrw2
	m_dcr = m_da[rx];
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_adr16_dp() // e7f8 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 00a abwl1
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	m_at = ext32(m_dbin);
	m_au = ext32(m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 7:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

void m68000_device::rol_adr32_dp() // e7f9 ffff
{
	int rx = (m_irdi >> 9) & 7;
	switch(m_inst_substate) {
	case 0:
	// 1e2 abll1
	m_aob = m_au;
	set_16h(m_at, m_dbin);
	m_au = m_au + 2;
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 1:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 1;
		} else
			m_inst_substate = 2;
		return;
	}
	[[fallthrough]]; case 2:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 009 abll2
	m_aob = m_au;
	m_pc = m_au;
	m_dcr = m_da[rx];
	set_16l(m_at, m_dbin);
	m_au = merge_16_32(high16(m_at), m_dbin);
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 3:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 3;
		} else
			m_inst_substate = 4;
		return;
	}
	[[fallthrough]]; case 4:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 004 abll3
	m_aob = m_at;
	m_au = m_pc + 2;
	// alu r=9 c=1 m=.....  i=....... ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	m_base_ssw = SSW_DATA | SSW_R;
	[[fallthrough]]; case 5:
	m_edb = m_program.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 5;
		} else
			m_inst_substate = 6;
		return;
	}
	[[fallthrough]]; case 6:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_dbin = m_edb;
	// 3c7 sftm1
	m_aob = m_au;
	m_ir = m_irc;
	m_pc = m_au;
	m_au = m_au + 2;
	// alu r=9 c=1 m=.nzvc  i=.....i. ALU.and_ a=R.dbin:m_dbin d=-1
	alu_and(m_dbin, 0xffff);
	sr_nzvc();
	// 304 stmw2
	m_au = m_at;
	// alu r=9 c=4 m=.nzvc  i=.....i. ALU.rol a=R.aluo:m_aluo d=-1
	alu_rol(m_aluo);
	sr_nzvc();
	m_base_ssw = SSW_PROGRAM | SSW_R;
	[[fallthrough]]; case 7:
	m_edb = m_opcodes.read_interruptible(m_aob & ~1);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 7;
		} else
			m_inst_substate = 8;
		return;
	}
	[[fallthrough]]; case 8:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	m_irc = m_edb;
	m_dbin = m_edb;
	// 38d morw2
	m_aob = m_au;
	m_ird = m_ir;
	if(m_next_state != S_TRACE) m_next_state = m_int_next_state;
	m_dbout = m_aluo;
	m_au = m_pc + 2;
	m_base_ssw = SSW_DATA;
	[[fallthrough]]; case 9:
	m_program.write_interruptible(m_aob & ~1, m_dbout);
	m_icount -= 4;
	if(m_icount <= 0) {
		if(access_to_be_redone()) {
			m_icount += 4;
			m_inst_substate = 9;
		} else
			m_inst_substate = 10;
		return;
	}
	[[fallthrough]]; case 10:
	if(m_aob & 1) {
		m_icount -= 4;
		m_inst_state = S_ADDRESS_ERROR;
		m_inst_substate = 0;
		return;
	}
	set_ftu_const();
	m_inst_state = m_next_state ? m_next_state : m_decode_table[m_ird];
	m_inst_substate = 0;
	if(m_sr & SR_T)
		m_next_state = S_TRACE;
	return;
	}
}

const m68000_device::handler m68000_device::s_handlers_dp[] = {
	&m68000_device::state_reset_dp,
	&m68000_device::state_bus_error_dp,
	&m68000_device::state_address_error_dp,
	&m68000_device::state_double_fault_dp,
	&m68000_device::state_interrupt_dp,
	&m68000_device::state_trace_dp,
	&m68000_device::state_illegal_dp,
	&m68000_device::state_priviledge_dp,
	&m68000_device::state_linea_dp,
	&m68000_device::state_linef_dp,
	&m68000_device::ori_b_imm8_ds_dp,
	&m68000_device::ori_b_imm8_ais_dp,
	&m68000_device::ori_b_imm8_aips_dp,
	&m68000_device::ori_b_imm8_pais_dp,
	&m68000_device::ori_b_imm8_das_dp,
	&m68000_device::ori_b_imm8_dais_dp,
	&m68000_device::ori_b_imm8_adr16_dp,
	&m68000_device::ori_b_imm8_adr32_dp,
	&m68000_device::ori_imm8_ccr_dp,
	&m68000_device::ori_w_imm16_ds_dp,
	&m68000_device::ori_w_imm16_ais_dp,
	&m68000_device::ori_w_imm16_aips_dp,
	&m68000_device::ori_w_imm16_pais_dp,
	&m68000_device::ori_w_imm16_das_dp,
	&m68000_device::ori_w_imm16_dais_dp,
	&m68000_device::ori_w_imm16_adr16_dp,
	&m68000_device::ori_w_imm16_adr32_dp,
	&m68000_device::ori_i16u_sr_dp,
	&m68000_device::ori_l_imm32_ds_dp,
	&m68000_device::ori_l_imm32_ais_dp,
	&m68000_device::ori_l_imm32_aips_dp,
	&m68000_device::ori_l_imm32_pais_dp,
	&m68000_device::ori_l_imm32_das_dp,
	&m68000_device::ori_l_imm32_dais_dp,
	&m68000_device::ori_l_imm32_adr16_dp,
	&m68000_device::ori_l_imm32_adr32_dp,
	&m68000_device::btst_dd_ds_dp,
	&m68000_device::movep_w_das_dd_dp,
	&m68000_device::btst_dd_ais_dp,
	&m68000_device::btst_dd_aips_dp,
	&m68000_device::btst_dd_pais_dp,
	&m68000_device::btst_dd_das_dp,
	&m68000_device::btst_dd_dais_dp,
	&m68000_device::btst_dd_adr16_dp,
	&m68000_device::btst_dd_adr32_dp,
	&m68000_device::btst_dd_dpc_dp,
	&m68000_device::btst_dd_dpci_dp,
	&m68000_device::btst_dd_imm_dp,
	&m68000_device::bchg_dd_ds_dp,
	&m68000_device::movep_l_das_dd_dp,
	&m68000_device::bchg_dd_ais_dp,
	&m68000_device::bchg_dd_aips_dp,
	&m68000_device::bchg_dd_pais_dp,
	&m68000_device::bchg_dd_das_dp,
	&m68000_device::bchg_dd_dais_dp,
	&m68000_device::bchg_dd_adr16_dp,
	&m68000_device::bchg_dd_adr32_dp,
	&m68000_device::bclr_dd_ds_dp,
	&m68000_device::movep_w_dd_das_dp,
	&m68000_device::bclr_dd_ais_dp,
	&m68000_device::bclr_dd_aips_dp,
	&m68000_device::bclr_dd_pais_dp,
	&m68000_device::bclr_dd_das_dp,
	&m68000_device::bclr_dd_dais_dp,
	&m68000_device::bclr_dd_adr16_dp,
	&m68000_device::bclr_dd_adr32_dp,
	&m68000_device::bset_dd_ds_dp,
	&m68000_device::movep_l_dd_das_dp,
	&m68000_device::bset_dd_ais_dp,
	&m68000_device::bset_dd_aips_dp,
	&m68000_device::bset_dd_pais_dp,
	&m68000_device::bset_dd_das_dp,
	&m68000_device::bset_dd_dais_dp,
	&m68000_device::bset_dd_adr16_dp,
	&m68000_device::bset_dd_adr32_dp,
	&m68000_device::andi_b_imm8_ds_dp,
	&m68000_device::andi_b_imm8_ais_dp,
	&m68000_device::andi_b_imm8_aips_dp,
	&m68000_device::andi_b_imm8_pais_dp,
	&m68000_device::andi_b_imm8_das_dp,
	&m68000_device::andi_b_imm8_dais_dp,
	&m68000_device::andi_b_imm8_adr16_dp,
	&m68000_device::andi_b_imm8_adr32_dp,
	&m68000_device::andi_imm8_ccr_dp,
	&m68000_device::andi_w_imm16_ds_dp,
	&m68000_device::andi_w_imm16_ais_dp,
	&m68000_device::andi_w_imm16_aips_dp,
	&m68000_device::andi_w_imm16_pais_dp,
	&m68000_device::andi_w_imm16_das_dp,
	&m68000_device::andi_w_imm16_dais_dp,
	&m68000_device::andi_w_imm16_adr16_dp,
	&m68000_device::andi_w_imm16_adr32_dp,
	&m68000_device::andi_i16u_sr_dp,
	&m68000_device::andi_l_imm32_ds_dp,
	&m68000_device::andi_l_imm32_ais_dp,
	&m68000_device::andi_l_imm32_aips_dp,
	&m68000_device::andi_l_imm32_pais_dp,
	&m68000_device::andi_l_imm32_das_dp,
	&m68000_device::andi_l_imm32_dais_dp,
	&m68000_device::andi_l_imm32_adr16_dp,
	&m68000_device::andi_l_imm32_adr32_dp,
	&m68000_device::subi_b_imm8_ds_dp,
	&m68000_device::subi_b_imm8_ais_dp,
	&m68000_device::subi_b_imm8_aips_dp,
	&m68000_device::subi_b_imm8_pais_dp,
	&m68000_device::subi_b_imm8_das_dp,
	&m68000_device::subi_b_imm8_dais_dp,
	&m68000_device::subi_b_imm8_adr16_dp,
	&m68000_device::subi_b_imm8_adr32_dp,
	&m68000_device::subi_w_imm16_ds_dp,
	&m68000_device::subi_w_imm16_ais_dp,
	&m68000_device::subi_w_imm16_aips_dp,
	&m68000_device::subi_w_imm16_pais_dp,
	&m68000_device::subi_w_imm16_das_dp,
	&m68000_device::subi_w_imm16_dais_dp,
	&m68000_device::subi_w_imm16_adr16_dp,
	&m68000_device::subi_w_imm16_adr32_dp,
	&m68000_device::subi_l_imm32_ds_dp,
	&m68000_device::subi_l_imm32_ais_dp,
	&m68000_device::subi_l_imm32_aips_dp,
	&m68000_device::subi_l_imm32_pais_dp,
	&m68000_device::subi_l_imm32_das_dp,
	&m68000_device::subi_l_imm32_dais_dp,
	&m68000_device::subi_l_imm32_adr16_dp,
	&m68000_device::subi_l_imm32_adr32_dp,
	&m68000_device::addi_b_imm8_ds_dp,
	&m68000_device::addi_b_imm8_ais_dp,
	&m68000_device::addi_b_imm8_aips_dp,
	&m68000_device::addi_b_imm8_pais_dp,
	&m68000_device::addi_b_imm8_das_dp,
	&m68000_device::addi_b_imm8_dais_dp,
	&m68000_device::addi_b_imm8_adr16_dp,
	&m68000_device::addi_b_imm8_adr32_dp,
	&m68000_device::addi_w_imm16_ds_dp,
	&m68000_device::addi_w_imm16_ais_dp,
	&m68000_device::addi_w_imm16_aips_dp,
	&m68000_device::addi_w_imm16_pais_dp,
	&m68000_device::addi_w_imm16_das_dp,
	&m68000_device::addi_w_imm16_dais_dp,
	&m68000_device::addi_w_imm16_adr16_dp,
	&m68000_device::addi_w_imm16_adr32_dp,
	&m68000_device::addi_l_imm32_ds_dp,
	&m68000_device::addi_l_imm32_ais_dp,
	&m68000_device::addi_l_imm32_aips_dp,
	&m68000_device::addi_l_imm32_pais_dp,
	&m68000_device::addi_l_imm32_das_dp,
	&m68000_device::addi_l_imm32_dais_dp,
	&m68000_device::addi_l_imm32_adr16_dp,
	&m68000_device::addi_l_imm32_adr32_dp,
	&m68000_device::btst_imm8_ds_dp,
	&m68000_device::btst_imm8_ais_dp,
	&m68000_device::btst_imm8_aips_dp,
	&m68000_device::btst_imm8_pais_dp,
	&m68000_device::btst_imm8_das_dp,
	&m68000_device::btst_imm8_dais_dp,
	&m68000_device::btst_imm8_adr16_dp,
	&m68000_device::btst_imm8_adr32_dp,
	&m68000_device::btst_imm8_dpc_dp,
	&m68000_device::btst_imm8_dpci_dp,
	&m68000_device::bchg_imm8_ds_dp,
	&m68000_device::bchg_imm8_ais_dp,
	&m68000_device::bchg_imm8_aips_dp,
	&m68000_device::bchg_imm8_pais_dp,
	&m68000_device::bchg_imm8_das_dp,
	&m68000_device::bchg_imm8_dais_dp,
	&m68000_device::bchg_imm8_adr16_dp,
	&m68000_device::bchg_imm8_adr32_dp,
	&m68000_device::bclr_imm8_ds_dp,
	&m68000_device::bclr_imm8_ais_dp,
	&m68000_device::bclr_imm8_aips_dp,
	&m68000_device::bclr_imm8_pais_dp,
	&m68000_device::bclr_imm8_das_dp,
	&m68000_device::bclr_imm8_dais_dp,
	&m68000_device::bclr_imm8_adr16_dp,
	&m68000_device::bclr_imm8_adr32_dp,
	&m68000_device::bset_imm8_ds_dp,
	&m68000_device::bset_imm8_ais_dp,
	&m68000_device::bset_imm8_aips_dp,
	&m68000_device::bset_imm8_pais_dp,
	&m68000_device::bset_imm8_das_dp,
	&m68000_device::bset_imm8_dais_dp,
	&m68000_device::bset_imm8_adr16_dp,
	&m68000_device::bset_imm8_adr32_dp,
	&m68000_device::eori_b_imm8_ds_dp,
	&m68000_device::eori_b_imm8_ais_dp,
	&m68000_device::eori_b_imm8_aips_dp,
	&m68000_device::eori_b_imm8_pais_dp,
	&m68000_device::eori_b_imm8_das_dp,
	&m68000_device::eori_b_imm8_dais_dp,
	&m68000_device::eori_b_imm8_adr16_dp,
	&m68000_device::eori_b_imm8_adr32_dp,
	&m68000_device::eori_imm8_ccr_dp,
	&m68000_device::eori_w_imm16_ds_dp,
	&m68000_device::eori_w_imm16_ais_dp,
	&m68000_device::eori_w_imm16_aips_dp,
	&m68000_device::eori_w_imm16_pais_dp,
	&m68000_device::eori_w_imm16_das_dp,
	&m68000_device::eori_w_imm16_dais_dp,
	&m68000_device::eori_w_imm16_adr16_dp,
	&m68000_device::eori_w_imm16_adr32_dp,
	&m68000_device::eori_i16u_sr_dp,
	&m68000_device::eori_l_imm32_ds_dp,
	&m68000_device::eori_l_imm32_ais_dp,
	&m68000_device::eori_l_imm32_aips_dp,
	&m68000_device::eori_l_imm32_pais_dp,
	&m68000_device::eori_l_imm32_das_dp,
	&m68000_device::eori_l_imm32_dais_dp,
	&m68000_device::eori_l_imm32_adr16_dp,
	&m68000_device::eori_l_imm32_adr32_dp,
	&m68000_device::cmpi_b_imm8_ds_dp,
	&m68000_device::cmpi_b_imm8_ais_dp,
	&m68000_device::cmpi_b_imm8_aips_dp,
	&m68000_device::cmpi_b_imm8_pais_dp,
	&m68000_device::cmpi_b_imm8_das_dp,
	&m68000_device::cmpi_b_imm8_dais_dp,
	&m68000_device::cmpi_b_imm8_adr16_dp,
	&m68000_device::cmpi_b_imm8_adr32_dp,
	&m68000_device::cmpi_w_imm16_ds_dp,
	&m68000_device::cmpi_w_imm16_ais_dp,
	&m68000_device::cmpi_w_imm16_aips_dp,
	&m68000_device::cmpi_w_imm16_pais_dp,
	&m68000_device::cmpi_w_imm16_das_dp,
	&m68000_device::cmpi_w_imm16_dais_dp,
	&m68000_device::cmpi_w_imm16_adr16_dp,
	&m68000_device::cmpi_w_imm16_adr32_dp,
	&m68000_device::cmpi_l_imm32_ds_dp,
	&m68000_device::cmpi_l_imm32_ais_dp,
	&m68000_device::cmpi_l_imm32_aips_dp,
	&m68000_device::cmpi_l_imm32_pais_dp,
	&m68000_device::cmpi_l_imm32_das_dp,
	&m68000_device::cmpi_l_imm32_dais_dp,
	&m68000_device::cmpi_l_imm32_adr16_dp,
	&m68000_device::cmpi_l_imm32_adr32_dp,
	&m68000_device::move_b_ds_dd_dp,
	&m68000_device::move_b_ais_dd_dp,
	&m68000_device::move_b_aips_dd_dp,
	&m68000_device::move_b_pais_dd_dp,
	&m68000_device::move_b_das_dd_dp,
	&m68000_device::move_b_dais_dd_dp,
	&m68000_device::move_b_adr16_dd_dp,
	&m68000_device::move_b_adr32_dd_dp,
	&m68000_device::move_b_dpc_dd_dp,
	&m68000_device::move_b_dpci_dd_dp,
	&m68000_device::move_b_imm8_dd_dp,
	&m68000_device::move_b_ds_aid_dp,
	&m68000_device::move_b_ais_aid_dp,
	&m68000_device::move_b_aips_aid_dp,
	&m68000_device::move_b_pais_aid_dp,
	&m68000_device::move_b_das_aid_dp,
	&m68000_device::move_b_dais_aid_dp,
	&m68000_device::move_b_adr16_aid_dp,
	&m68000_device::move_b_adr32_aid_dp,
	&m68000_device::move_b_dpc_aid_dp,
	&m68000_device::move_b_dpci_aid_dp,
	&m68000_device::move_b_imm8_aid_dp,
	&m68000_device::move_b_ds_aipd_dp,
	&m68000_device::move_b_ais_aipd_dp,
	&m68000_device::move_b_aips_aipd_dp,
	&m68000_device::move_b_pais_aipd_dp,
	&m68000_device::move_b_das_aipd_dp,
	&m68000_device::move_b_dais_aipd_dp,
	&m68000_device::move_b_adr16_aipd_dp,
	&m68000_device::move_b_adr32_aipd_dp,
	&m68000_device::move_b_dpc_aipd_dp,
	&m68000_device::move_b_dpci_aipd_dp,
	&m68000_device::move_b_imm8_aipd_dp,
	&m68000_device::move_b_ds_paid_dp,
	&m68000_device::move_b_ais_paid_dp,
	&m68000_device::move_b_aips_paid_dp,
	&m68000_device::move_b_pais_paid_dp,
	&m68000_device::move_b_das_paid_dp,
	&m68000_device::move_b_dais_paid_dp,
	&m68000_device::move_b_adr16_paid_dp,
	&m68000_device::move_b_adr32_paid_dp,
	&m68000_device::move_b_dpc_paid_dp,
	&m68000_device::move_b_dpci_paid_dp,
	&m68000_device::move_b_imm8_paid_dp,
	&m68000_device::move_b_ds_dad_dp,
	&m68000_device::move_b_ais_dad_dp,
	&m68000_device::move_b_aips_dad_dp,
	&m68000_device::move_b_pais_dad_dp,
	&m68000_device::move_b_das_dad_dp,
	&m68000_device::move_b_dais_dad_dp,
	&m68000_device::move_b_adr16_dad_dp,
	&m68000_device::move_b_adr32_dad_dp,
	&m68000_device::move_b_dpc_dad_dp,
	&m68000_device::move_b_dpci_dad_dp,
	&m68000_device::move_b_imm8_dad_dp,
	&m68000_device::move_b_ds_daid_dp,
	&m68000_device::move_b_ais_daid_dp,
	&m68000_device::move_b_aips_daid_dp,
	&m68000_device::move_b_pais_daid_dp,
	&m68000_device::move_b_das_daid_dp,
	&m68000_device::move_b_dais_daid_dp,
	&m68000_device::move_b_adr16_daid_dp,
	&m68000_device::move_b_adr32_daid_dp,
	&m68000_device::move_b_dpc_daid_dp,
	&m68000_device::move_b_dpci_daid_dp,
	&m68000_device::move_b_imm8_daid_dp,
	&m68000_device::move_b_ds_adr16_dp,
	&m68000_device::move_b_ais_adr16_dp,
	&m68000_device::move_b_aips_adr16_dp,
	&m68000_device::move_b_pais_adr16_dp,
	&m68000_device::move_b_das_adr16_dp,
	&m68000_device::move_b_dais_adr16_dp,
	&m68000_device::move_b_adr16_adr16_dp,
	&m68000_device::move_b_adr32_adr16_dp,
	&m68000_device::move_b_dpc_adr16_dp,
	&m68000_device::move_b_dpci_adr16_dp,
	&m68000_device::move_b_imm8_adr16_dp,
	&m68000_device::move_b_ds_adr32_dp,
	&m68000_device::move_b_ais_adr32_dp,
	&m68000_device::move_b_aips_adr32_dp,
	&m68000_device::move_b_pais_adr32_dp,
	&m68000_device::move_b_das_adr32_dp,
	&m68000_device::move_b_dais_adr32_dp,
	&m68000_device::move_b_adr16_adr32_dp,
	&m68000_device::move_b_adr32_adr32_dp,
	&m68000_device::move_b_dpc_adr32_dp,
	&m68000_device::move_b_dpci_adr32_dp,
	&m68000_device::move_b_imm8_adr32_dp,
	&m68000_device::move_l_ds_dd_dp,
	&m68000_device::move_l_as_dd_dp,
	&m68000_device::move_l_ais_dd_dp,
	&m68000_device::move_l_aips_dd_dp,
	&m68000_device::move_l_pais_dd_dp,
	&m68000_device::move_l_das_dd_dp,
	&m68000_device::move_l_dais_dd_dp,
	&m68000_device::move_l_adr16_dd_dp,
	&m68000_device::move_l_adr32_dd_dp,
	&m68000_device::move_l_dpc_dd_dp,
	&m68000_device::move_l_dpci_dd_dp,
	&m68000_device::move_l_imm32_dd_dp,
	&m68000_device::movea_l_ds_ad_dp,
	&m68000_device::movea_l_as_ad_dp,
	&m68000_device::movea_l_ais_ad_dp,
	&m68000_device::movea_l_aips_ad_dp,
	&m68000_device::movea_l_pais_ad_dp,
	&m68000_device::movea_l_das_ad_dp,
	&m68000_device::movea_l_dais_ad_dp,
	&m68000_device::movea_l_adr16_ad_dp,
	&m68000_device::movea_l_adr32_ad_dp,
	&m68000_device::movea_l_dpc_ad_dp,
	&m68000_device::movea_l_dpci_ad_dp,
	&m68000_device::movea_l_imm32_ad_dp,
	&m68000_device::move_l_ds_aid_dp,
	&m68000_device::move_l_as_aid_dp,
	&m68000_device::move_l_ais_aid_dp,
	&m68000_device::move_l_aips_aid_dp,
	&m68000_device::move_l_pais_aid_dp,
	&m68000_device::move_l_das_aid_dp,
	&m68000_device::move_l_dais_aid_dp,
	&m68000_device::move_l_adr16_aid_dp,
	&m68000_device::move_l_adr32_aid_dp,
	&m68000_device::move_l_dpc_aid_dp,
	&m68000_device::move_l_dpci_aid_dp,
	&m68000_device::move_l_imm32_aid_dp,
	&m68000_device::move_l_ds_aipd_dp,
	&m68000_device::move_l_as_aipd_dp,
	&m68000_device::move_l_ais_aipd_dp,
	&m68000_device::move_l_aips_aipd_dp,
	&m68000_device::move_l_pais_aipd_dp,
	&m68000_device::move_l_das_aipd_dp,
	&m68000_device::move_l_dais_aipd_dp,
	&m68000_device::move_l_adr16_aipd_dp,
	&m68000_device::move_l_adr32_aipd_dp,
	&m68000_device::move_l_dpc_aipd_dp,
	&m68000_device::move_l_dpci_aipd_dp,
	&m68000_device::move_l_imm32_aipd_dp,
	&m68000_device::move_l_ds_paid_dp,
	&m68000_device::move_l_as_paid_dp,
	&m68000_device::move_l_ais_paid_dp,
	&m68000_device::move_l_aips_paid_dp,
	&m68000_device::move_l_pais_paid_dp,
	&m68000_device::move_l_das_paid_dp,
	&m68000_device::move_l_dais_paid_dp,
	&m68000_device::move_l_adr16_paid_dp,
	&m68000_device::move_l_adr32_paid_dp,
	&m68000_device::move_l_dpc_paid_dp,
	&m68000_device::move_l_dpci_paid_dp,
	&m68000_device::move_l_imm32_paid_dp,
	&m68000_device::move_l_ds_dad_dp,
	&m68000_device::move_l_as_dad_dp,
	&m68000_device::move_l_ais_dad_dp,
	&m68000_device::move_l_aips_dad_dp,
	&m68000_device::move_l_pais_dad_dp,
	&m68000_device::move_l_das_dad_dp,
	&m68000_device::move_l_dais_dad_dp,
	&m68000_device::move_l_adr16_dad_dp,
	&m68000_device::move_l_adr32_dad_dp,
	&m68000_device::move_l_dpc_dad_dp,
	&m68000_device::move_l_dpci_dad_dp,
	&m68000_device::move_l_imm32_dad_dp,
	&m68000_device::move_l_ds_daid_dp,
	&m68000_device::move_l_as_daid_dp,
	&m68000_device::move_l_ais_daid_dp,
	&m68000_device::move_l_aips_daid_dp,
	&m68000_device::move_l_pais_daid_dp,
	&m68000_device::move_l_das_daid_dp,
	&m68000_device::move_l_dais_daid_dp,
	&m68000_device::move_l_adr16_daid_dp,
	&m68000_device::move_l_adr32_daid_dp,
	&m68000_device::move_l_dpc_daid_dp,
	&m68000_device::move_l_dpci_daid_dp,
	&m68000_device::move_l_imm32_daid_dp,
	&m68000_device::move_l_ds_adr16_dp,
	&m68000_device::move_l_as_adr16_dp,
	&m68000_device::move_l_ais_adr16_dp,
	&m68000_device::move_l_aips_adr16_dp,
	&m68000_device::move_l_pais_adr16_dp,
	&m68000_device::move_l_das_adr16_dp,
	&m68000_device::move_l_dais_adr16_dp,
	&m68000_device::move_l_adr16_adr16_dp,
	&m68000_device::move_l_adr32_adr16_dp,
	&m68000_device::move_l_dpc_adr16_dp,
	&m68000_device::move_l_dpci_adr16_dp,
	&m68000_device::move_l_imm32_adr16_dp,
	&m68000_device::move_l_ds_adr32_dp,
	&m68000_device::move_l_as_adr32_dp,
	&m68000_device::move_l_ais_adr32_dp,
	&m68000_device::move_l_aips_adr32_dp,
	&m68000_device::move_l_pais_adr32_dp,
	&m68000_device::move_l_das_adr32_dp,
	&m68000_device::move_l_dais_adr32_dp,
	&m68000_device::move_l_adr16_adr32_dp,
	&m68000_device::move_l_adr32_adr32_dp,
	&m68000_device::move_l_dpc_adr32_dp,
	&m68000_device::move_l_dpci_adr32_dp,
	&m68000_device::move_l_imm32_adr32_dp,
	&m68000_device::move_w_ds_dd_dp,
	&m68000_device::move_w_as_dd_dp,
	&m68000_device::move_w_ais_dd_dp,
	&m68000_device::move_w_aips_dd_dp,
	&m68000_device::move_w_pais_dd_dp,
	&m68000_device::move_w_das_dd_dp,
	&m68000_device::move_w_dais_dd_dp,
	&m68000_device::move_w_adr16_dd_dp,
	&m68000_device::move_w_adr32_dd_dp,
	&m68000_device::move_w_dpc_dd_dp,
	&m68000_device::move_w_dpci_dd_dp,
	&m68000_device::move_w_imm16_dd_dp,
	&m68000_device::movea_w_ds_ad_dp,
	&m68000_device::movea_w_as_ad_dp,
	&m68000_device::movea_w_ais_ad_dp,
	&m68000_device::movea_w_aips_ad_dp,
	&m68000_device::movea_w_pais_ad_dp,
	&m68000_device::movea_w_das_ad_dp,
	&m68000_device::movea_w_dais_ad_dp,
	&m68000_device::movea_w_adr16_ad_dp,
	&m68000_device::movea_w_adr32_ad_dp,
	&m68000_device::movea_w_dpc_ad_dp,
	&m68000_device::movea_w_dpci_ad_dp,
	&m68000_device::movea_w_imm16_ad_dp,
	&m68000_device::move_w_ds_aid_dp,
	&m68000_device::move_w_as_aid_dp,
	&m68000_device::move_w_ais_aid_dp,
	&m68000_device::move_w_aips_aid_dp,
	&m68000_device::move_w_pais_aid_dp,
	&m68000_device::move_w_das_aid_dp,
	&m68000_device::move_w_dais_aid_dp,
	&m68000_device::move_w_adr16_aid_dp,
	&m68000_device::move_w_adr32_aid_dp,
	&m68000_device::move_w_dpc_aid_dp,
	&m68000_device::move_w_dpci_aid_dp,
	&m68000_device::move_w_imm16_aid_dp,
	&m68000_device::move_w_ds_aipd_dp,
	&m68000_device::move_w_as_aipd_dp,
	&m68000_device::move_w_ais_aipd_dp,
	&m68000_device::move_w_aips_aipd_dp,
	&m68000_device::move_w_pais_aipd_dp,
	&m68000_device::move_w_das_aipd_dp,
	&m68000_device::move_w_dais_aipd_dp,
	&m68000_device::move_w_adr16_aipd_dp,
	&m68000_device::move_w_adr32_aipd_dp,
	&m68000_device::move_w_dpc_aipd_dp,
	&m68000_device::move_w_dpci_aipd_dp,
	&m68000_device::move_w_imm16_aipd_dp,
	&m68000_device::move_w_ds_paid_dp,
	&m68000_device::move_w_as_paid_dp,
	&m68000_device::move_w_ais_paid_dp,
	&m68000_device::move_w_aips_paid_dp,
	&m68000_device::move_w_pais_paid_dp,
	&m68000_device::move_w_das_paid_dp,
	&m68000_device::move_w_dais_paid_dp,
	&m68000_device::move_w_adr16_paid_dp,
	&m68000_device::move_w_adr32_paid_dp,
	&m68000_device::move_w_dpc_paid_dp,
	&m68000_device::move_w_dpci_paid_dp,
	&m68000_device::move_w_imm16_paid_dp,
	&m68000_device::move_w_ds_dad_dp,
	&m68000_device::move_w_as_dad_dp,
	&m68000_device::move_w_ais_dad_dp,
	&m68000_device::move_w_aips_dad_dp,
	&m68000_device::move_w_pais_dad_dp,
	&m68000_device::move_w_das_dad_dp,
	&m68000_device::move_w_dais_dad_dp,
	&m68000_device::move_w_adr16_dad_dp,
	&m68000_device::move_w_adr32_dad_dp,
	&m68000_device::move_w_dpc_dad_dp,
	&m68000_device::move_w_dpci_dad_dp,
	&m68000_device::move_w_imm16_dad_dp,
	&m68000_device::move_w_ds_daid_dp,
	&m68000_device::move_w_as_daid_dp,
	&m68000_device::move_w_ais_daid_dp,
	&m68000_device::move_w_aips_daid_dp,
	&m68000_device::move_w_pais_daid_dp,
	&m68000_device::move_w_das_daid_dp,
	&m68000_device::move_w_dais_daid_dp,
	&m68000_device::move_w_adr16_daid_dp,
	&m68000_device::move_w_adr32_daid_dp,
	&m68000_device::move_w_dpc_daid_dp,
	&m68000_device::move_w_dpci_daid_dp,
	&m68000_device::move_w_imm16_daid_dp,
	&m68000_device::move_w_ds_adr16_dp,
	&m68000_device::move_w_as_adr16_dp,
	&m68000_device::move_w_ais_adr16_dp,
	&m68000_device::move_w_aips_adr16_dp,
	&m68000_device::move_w_pais_adr16_dp,
	&m68000_device::move_w_das_adr16_dp,
	&m68000_device::move_w_dais_adr16_dp,
	&m68000_device::move_w_adr16_adr16_dp,
	&m68000_device::move_w_adr32_adr16_dp,
	&m68000_device::move_w_dpc_adr16_dp,
	&m68000_device::move_w_dpci_adr16_dp,
	&m68000_device::move_w_imm16_adr16_dp,
	&m68000_device::move_w_ds_adr32_dp,
	&m68000_device::move_w_as_adr32_dp,
	&m68000_device::move_w_ais_adr32_dp,
	&m68000_device::move_w_aips_adr32_dp,
	&m68000_device::move_w_pais_adr32_dp,
	&m68000_device::move_w_das_adr32_dp,
	&m68000_device::move_w_dais_adr32_dp,
	&m68000_device::move_w_adr16_adr32_dp,
	&m68000_device::move_w_adr32_adr32_dp,
	&m68000_device::move_w_dpc_adr32_dp,
	&m68000_device::move_w_dpci_adr32_dp,
	&m68000_device::move_w_imm16_adr32_dp,
	&m68000_device::negx_b_ds_dp,
	&m68000_device::negx_b_ais_dp,
	&m68000_device::negx_b_aips_dp,
	&m68000_device::negx_b_pais_dp,
	&m68000_device::negx_b_das_dp,
	&m68000_device::negx_b_dais_dp,
	&m68000_device::negx_b_adr16_dp,
	&m68000_device::negx_b_adr32_dp,
	&m68000_device::negx_w_ds_dp,
	&m68000_device::negx_w_ais_dp,
	&m68000_device::negx_w_aips_dp,
	&m68000_device::negx_w_pais_dp,
	&m68000_device::negx_w_das_dp,
	&m68000_device::negx_w_dais_dp,
	&m68000_device::negx_w_adr16_dp,
	&m68000_device::negx_w_adr32_dp,
	&m68000_device::negx_l_ds_dp,
	&m68000_device::negx_l_ais_dp,
	&m68000_device::negx_l_aips_dp,
	&m68000_device::negx_l_pais_dp,
	&m68000_device::negx_l_das_dp,
	&m68000_device::negx_l_dais_dp,
	&m68000_device::negx_l_adr16_dp,
	&m68000_device::negx_l_adr32_dp,
	&m68000_device::move_sr_ds_dp,
	&m68000_device::move_sr_ais_dp,
	&m68000_device::move_sr_aips_dp,
	&m68000_device::move_sr_pais_dp,
	&m68000_device::move_sr_das_dp,
	&m68000_device::move_sr_dais_dp,
	&m68000_device::move_sr_adr16_dp,
	&m68000_device::move_sr_adr32_dp,
	&m68000_device::chk_w_ds_dd_dp,
	&m68000_device::chk_w_ais_dd_dp,
	&m68000_device::chk_w_aips_dd_dp,
	&m68000_device::chk_w_pais_dd_dp,
	&m68000_device::chk_w_das_dd_dp,
	&m68000_device::chk_w_dais_dd_dp,
	&m68000_device::chk_w_adr16_dd_dp,
	&m68000_device::chk_w_adr32_dd_dp,
	&m68000_device::chk_w_dpc_dd_dp,
	&m68000_device::chk_w_dpci_dd_dp,
	&m68000_device::chk_w_imm16_dd_dp,
	&m68000_device::lea_ais_ad_dp,
	&m68000_device::lea_das_ad_dp,
	&m68000_device::lea_dais_ad_dp,
	&m68000_device::lea_adr16_ad_dp,
	&m68000_device::lea_adr32_ad_dp,
	&m68000_device::lea_dpc_ad_dp,
	&m68000_device::lea_dpci_ad_dp,
	&m68000_device::clr_b_ds_dp,
	&m68000_device::clr_b_ais_dp,
	&m68000_device::clr_b_aips_dp,
	&m68000_device::clr_b_pais_dp,
	&m68000_device::clr_b_das_dp,
	&m68000_device::clr_b_dais_dp,
	&m68000_device::clr_b_adr16_dp,
	&m68000_device::clr_b_adr32_dp,
	&m68000_device::clr_w_ds_dp,
	&m68000_device::clr_w_ais_dp,
	&m68000_device::clr_w_aips_dp,
	&m68000_device::clr_w_pais_dp,
	&m68000_device::clr_w_das_dp,
	&m68000_device::clr_w_dais_dp,
	&m68000_device::clr_w_adr16_dp,
	&m68000_device::clr_w_adr32_dp,
	&m68000_device::clr_l_ds_dp,
	&m68000_device::clr_l_ais_dp,
	&m68000_device::clr_l_aips_dp,
	&m68000_device::clr_l_pais_dp,
	&m68000_device::clr_l_das_dp,
	&m68000_device::clr_l_dais_dp,
	&m68000_device::clr_l_adr16_dp,
	&m68000_device::clr_l_adr32_dp,
	&m68000_device::neg_b_ds_dp,
	&m68000_device::neg_b_ais_dp,
	&m68000_device::neg_b_aips_dp,
	&m68000_device::neg_b_pais_dp,
	&m68000_device::neg_b_das_dp,
	&m68000_device::neg_b_dais_dp,
	&m68000_device::neg_b_adr16_dp,
	&m68000_device::neg_b_adr32_dp,
	&m68000_device::neg_w_ds_dp,
	&m68000_device::neg_w_ais_dp,
	&m68000_device::neg_w_aips_dp,
	&m68000_device::neg_w_pais_dp,
	&m68000_device::neg_w_das_dp,
	&m68000_device::neg_w_dais_dp,
	&m68000_device::neg_w_adr16_dp,
	&m68000_device::neg_w_adr32_dp,
	&m68000_device::neg_l_ds_dp,
	&m68000_device::neg_l_ais_dp,
	&m68000_device::neg_l_aips_dp,
	&m68000_device::neg_l_pais_dp,
	&m68000_device::neg_l_das_dp,
	&m68000_device::neg_l_dais_dp,
	&m68000_device::neg_l_adr16_dp,
	&m68000_device::neg_l_adr32_dp,
	&m68000_device::move_ds_ccr_dp,
	&m68000_device::move_ais_ccr_dp,
	&m68000_device::move_aips_ccr_dp,
	&m68000_device::move_pais_ccr_dp,
	&m68000_device::move_das_ccr_dp,
	&m68000_device::move_dais_ccr_dp,
	&m68000_device::move_adr16_ccr_dp,
	&m68000_device::move_adr32_ccr_dp,
	&m68000_device::move_dpc_ccr_dp,
	&m68000_device::move_dpci_ccr_dp,
	&m68000_device::move_imm8_ccr_dp,
	&m68000_device::not_b_ds_dp,
	&m68000_device::not_b_ais_dp,
	&m68000_device::not_b_aips_dp,
	&m68000_device::not_b_pais_dp,
	&m68000_device::not_b_das_dp,
	&m68000_device::not_b_dais_dp,
	&m68000_device::not_b_adr16_dp,
	&m68000_device::not_b_adr32_dp,
	&m68000_device::not_w_ds_dp,
	&m68000_device::not_w_ais_dp,
	&m68000_device::not_w_aips_dp,
	&m68000_device::not_w_pais_dp,
	&m68000_device::not_w_das_dp,
	&m68000_device::not_w_dais_dp,
	&m68000_device::not_w_adr16_dp,
	&m68000_device::not_w_adr32_dp,
	&m68000_device::not_l_ds_dp,
	&m68000_device::not_l_ais_dp,
	&m68000_device::not_l_aips_dp,
	&m68000_device::not_l_pais_dp,
	&m68000_device::not_l_das_dp,
	&m68000_device::not_l_dais_dp,
	&m68000_device::not_l_adr16_dp,
	&m68000_device::not_l_adr32_dp,
	&m68000_device::move_ds_sr_dp,
	&m68000_device::move_ais_sr_dp,
	&m68000_device::move_aips_sr_dp,
	&m68000_device::move_pais_sr_dp,
	&m68000_device::move_das_sr_dp,
	&m68000_device::move_dais_sr_dp,
	&m68000_device::move_adr16_sr_dp,
	&m68000_device::move_adr32_sr_dp,
	&m68000_device::move_dpc_sr_dp,
	&m68000_device::move_dpci_sr_dp,
	&m68000_device::move_i16u_sr_dp,
	&m68000_device::nbcd_b_ds_dp,
	&m68000_device::nbcd_b_ais_dp,
	&m68000_device::nbcd_b_aips_dp,
	&m68000_device::nbcd_b_pais_dp,
	&m68000_device::nbcd_b_das_dp,
	&m68000_device::nbcd_b_dais_dp,
	&m68000_device::nbcd_b_adr16_dp,
	&m68000_device::nbcd_b_adr32_dp,
	&m68000_device::swap_ds_dp,
	&m68000_device::pea_ais_dp,
	&m68000_device::pea_das_dp,
	&m68000_device::pea_dais_dp,
	&m68000_device::pea_adr16_dp,
	&m68000_device::pea_adr32_dp,
	&m68000_device::pea_dpc_dp,
	&m68000_device::pea_dpci_dp,
	&m68000_device::ext_w_ds_dp,
	&m68000_device::movem_w_list_ais_dp,
	&m68000_device::movem_w_listp_pais_dp,
	&m68000_device::movem_w_list_das_dp,
	&m68000_device::movem_w_list_dais_dp,
	&m68000_device::movem_w_list_adr16_dp,
	&m68000_device::movem_w_list_adr32_dp,
	&m68000_device::ext_l_ds_dp,
	&m68000_device::movem_l_list_ais_dp,
	&m68000_device::movem_l_listp_pais_dp,
	&m68000_device::movem_l_list_das_dp,
	&m68000_device::movem_l_list_dais_dp,
	&m68000_device::movem_l_list_adr16_dp,
	&m68000_device::movem_l_list_adr32_dp,
	&m68000_device::tst_b_ds_dp,
	&m68000_device::tst_b_ais_dp,
	&m68000_device::tst_b_aips_dp,
	&m68000_device::tst_b_pais_dp,
	&m68000_device::tst_b_das_dp,
	&m68000_device::tst_b_dais_dp,
	&m68000_device::tst_b_adr16_dp,
	&m68000_device::tst_b_adr32_dp,
	&m68000_device::tst_w_ds_dp,
	&m68000_device::tst_w_ais_dp,
	&m68000_device::tst_w_aips_dp,
	&m68000_device::tst_w_pais_dp,
	&m68000_device::tst_w_das_dp,
	&m68000_device::tst_w_dais_dp,
	&m68000_device::tst_w_adr16_dp,
	&m68000_device::tst_w_adr32_dp,
	&m68000_device::tst_l_ds_dp,
	&m68000_device::tst_l_ais_dp,
	&m68000_device::tst_l_aips_dp,
	&m68000_device::tst_l_pais_dp,
	&m68000_device::tst_l_das_dp,
	&m68000_device::tst_l_dais_dp,
	&m68000_device::tst_l_adr16_dp,
	&m68000_device::tst_l_adr32_dp,
	&m68000_device::tas_ds_dp,
	&m68000_device::tas_ais_dp,
	&m68000_device::tas_aips_dp,
	&m68000_device::tas_pais_dp,
	&m68000_device::tas_das_dp,
	&m68000_device::tas_dais_dp,
	&m68000_device::tas_adr16_dp,
	&m68000_device::tas_adr32_dp,
	&m68000_device::movem_w_ais_list_dp,
	&m68000_device::movem_w_aips_list_dp,
	&m68000_device::movem_w_das_list_dp,
	&m68000_device::movem_w_dais_list_dp,
	&m68000_device::movem_w_adr16_list_dp,
	&m68000_device::movem_w_adr32_list_dp,
	&m68000_device::movem_w_dpc_list_dp,
	&m68000_device::movem_w_dpci_list_dp,
	&m68000_device::movem_l_ais_list_dp,
	&m68000_device::movem_l_aips_list_dp,
	&m68000_device::movem_l_das_list_dp,
	&m68000_device::movem_l_dais_list_dp,
	&m68000_device::movem_l_adr16_list_dp,
	&m68000_device::movem_l_adr32_list_dp,
	&m68000_device::movem_l_dpc_list_dp,
	&m68000_device::movem_l_dpci_list_dp,
	&m68000_device::trap_imm4_dp,
	&m68000_device::link_as_imm16_dp,
	&m68000_device::unlk_as_dp,
	&m68000_device::move_as_usp_dp,
	&m68000_device::move_usp_as_dp,
	&m68000_device::reset_dp,
	&m68000_device::nop_dp,
	&m68000_device::stop_i16u_dp,
	&m68000_device::rte_dp,
	&m68000_device::rts_dp,
	&m68000_device::trapv_dp,
	&m68000_device::rtr_dp,
	&m68000_device::jsr_ais_dp,
	&m68000_device::jsr_das_dp,
	&m68000_device::jsr_dais_dp,
	&m68000_device::jsr_adr16_dp,
	&m68000_device::jsr_adr32_dp,
	&m68000_device::jsr_dpc_dp,
	&m68000_device::jsr_dpci_dp,
	&m68000_device::jmp_ais_dp,
	&m68000_device::jmp_das_dp,
	&m68000_device::jmp_dais_dp,
	&m68000_device::jmp_adr16_dp,
	&m68000_device::jmp_adr32_dp,
	&m68000_device::jmp_dpc_dp,
	&m68000_device::jmp_dpci_dp,
	&m68000_device::addq_b_imm3_ds_dp,
	&m68000_device::addq_b_imm3_ais_dp,
	&m68000_device::addq_b_imm3_aips_dp,
	&m68000_device::addq_b_imm3_pais_dp,
	&m68000_device::addq_b_imm3_das_dp,
	&m68000_device::addq_b_imm3_dais_dp,
	&m68000_device::addq_b_imm3_adr16_dp,
	&m68000_device::addq_b_imm3_adr32_dp,
	&m68000_device::addq_w_imm3_ds_dp,
	&m68000_device::addq_w_imm3_as_dp,
	&m68000_device::addq_w_imm3_ais_dp,
	&m68000_device::addq_w_imm3_aips_dp,
	&m68000_device::addq_w_imm3_pais_dp,
	&m68000_device::addq_w_imm3_das_dp,
	&m68000_device::addq_w_imm3_dais_dp,
	&m68000_device::addq_w_imm3_adr16_dp,
	&m68000_device::addq_w_imm3_adr32_dp,
	&m68000_device::addq_l_imm3_ds_dp,
	&m68000_device::addq_l_imm3_as_dp,
	&m68000_device::addq_l_imm3_ais_dp,
	&m68000_device::addq_l_imm3_aips_dp,
	&m68000_device::addq_l_imm3_pais_dp,
	&m68000_device::addq_l_imm3_das_dp,
	&m68000_device::addq_l_imm3_dais_dp,
	&m68000_device::addq_l_imm3_adr16_dp,
	&m68000_device::addq_l_imm3_adr32_dp,
	&m68000_device::st_ds_dp,
	&m68000_device::dbt_ds_rel16_dp,
	&m68000_device::st_ais_dp,
	&m68000_device::st_aips_dp,
	&m68000_device::st_pais_dp,
	&m68000_device::st_das_dp,
	&m68000_device::st_dais_dp,
	&m68000_device::st_adr16_dp,
	&m68000_device::st_adr32_dp,
	&m68000_device::subq_b_imm3_ds_dp,
	&m68000_device::subq_b_imm3_ais_dp,
	&m68000_device::subq_b_imm3_aips_dp,
	&m68000_device::subq_b_imm3_pais_dp,
	&m68000_device::subq_b_imm3_das_dp,
	&m68000_device::subq_b_imm3_dais_dp,
	&m68000_device::subq_b_imm3_adr16_dp,
	&m68000_device::subq_b_imm3_adr32_dp,
	&m68000_device::subq_w_imm3_ds_dp,
	&m68000_device::subq_w_imm3_as_dp,
	&m68000_device::subq_w_imm3_ais_dp,
	&m68000_device::subq_w_imm3_aips_dp,
	&m68000_device::subq_w_imm3_pais_dp,
	&m68000_device::subq_w_imm3_das_dp,
	&m68000_device::subq_w_imm3_dais_dp,
	&m68000_device::subq_w_imm3_adr16_dp,
	&m68000_device::subq_w_imm3_adr32_dp,
	&m68000_device::subq_l_imm3_ds_dp,
	&m68000_device::subq_l_imm3_as_dp,
	&m68000_device::subq_l_imm3_ais_dp,
	&m68000_device::subq_l_imm3_aips_dp,
	&m68000_device::subq_l_imm3_pais_dp,
	&m68000_device::subq_l_imm3_das_dp,
	&m68000_device::subq_l_imm3_dais_dp,
	&m68000_device::subq_l_imm3_adr16_dp,
	&m68000_device::subq_l_imm3_adr32_dp,
	&m68000_device::sf_ds_dp,
	&m68000_device::dbra_ds_rel16_dp,
	&m68000_device::sf_ais_dp,
	&m68000_device::sf_aips_dp,
	&m68000_device::sf_pais_dp,
	&m68000_device::sf_das_dp,
	&m68000_device::sf_dais_dp,
	&m68000_device::sf_adr16_dp,
	&m68000_device::sf_adr32_dp,
	&m68000_device::shi_ds_dp,
	&m68000_device::dbhi_ds_rel16_dp,
	&m68000_device::shi_ais_dp,
	&m68000_device::shi_aips_dp,
	&m68000_device::shi_pais_dp,
	&m68000_device::shi_das_dp,
	&m68000_device::shi_dais_dp,
	&m68000_device::shi_adr16_dp,
	&m68000_device::shi_adr32_dp,
	&m68000_device::sls_ds_dp,
	&m68000_device::dbls_ds_rel16_dp,
	&m68000_device::sls_ais_dp,
	&m68000_device::sls_aips_dp,
	&m68000_device::sls_pais_dp,
	&m68000_device::sls_das_dp,
	&m68000_device::sls_dais_dp,
	&m68000_device::sls_adr16_dp,
	&m68000_device::sls_adr32_dp,
	&m68000_device::scc_ds_dp,
	&m68000_device::dbcc_ds_rel16_dp,
	&m68000_device::scc_ais_dp,
	&m68000_device::scc_aips_dp,
	&m68000_device::scc_pais_dp,
	&m68000_device::scc_das_dp,
	&m68000_device::scc_dais_dp,
	&m68000_device::scc_adr16_dp,
	&m68000_device::scc_adr32_dp,
	&m68000_device::scs_ds_dp,
	&m68000_device::dbcs_ds_rel16_dp,
	&m68000_device::scs_ais_dp,
	&m68000_device::scs_aips_dp,
	&m68000_device::scs_pais_dp,
	&m68000_device::scs_das_dp,
	&m68000_device::scs_dais_dp,
	&m68000_device::scs_adr16_dp,
	&m68000_device::scs_adr32_dp,
	&m68000_device::sne_ds_dp,
	&m68000_device::dbne_ds_rel16_dp,
	&m68000_device::sne_ais_dp,
	&m68000_device::sne_aips_dp,
	&m68000_device::sne_pais_dp,
	&m68000_device::sne_das_dp,
	&m68000_device::sne_dais_dp,
	&m68000_device::sne_adr16_dp,
	&m68000_device::sne_adr32_dp,
	&m68000_device::seq_ds_dp,
	&m68000_device::dbeq_ds_rel16_dp,
	&m68000_device::seq_ais_dp,
	&m68000_device::seq_aips_dp,
	&m68000_device::seq_pais_dp,
	&m68000_device::seq_das_dp,
	&m68000_device::seq_dais_dp,
	&m68000_device::seq_adr16_dp,
	&m68000_device::seq_adr32_dp,
	&m68000_device::svc_ds_dp,
	&m68000_device::dbvc_ds_rel16_dp,
	&m68000_device::svc_ais_dp,
	&m68000_device::svc_aips_dp,
	&m68000_device::svc_pais_dp,
	&m68000_device::svc_das_dp,
	&m68000_device::svc_dais_dp,
	&m68000_device::svc_adr16_dp,
	&m68000_device::svc_adr32_dp,
	&m68000_device::svs_ds_dp,
	&m68000_device::dbvs_ds_rel16_dp,
	&m68000_device::svs_ais_dp,
	&m68000_device::svs_aips_dp,
	&m68000_device::svs_pais_dp,
	&m68000_device::svs_das_dp,
	&m68000_device::svs_dais_dp,
	&m68000_device::svs_adr16_dp,
	&m68000_device::svs_adr32_dp,
	&m68000_device::spl_ds_dp,
	&m68000_device::dbpl_ds_rel16_dp,
	&m68000_device::spl_ais_dp,
	&m68000_device::spl_aips_dp,
	&m68000_device::spl_pais_dp,
	&m68000_device::spl_das_dp,
	&m68000_device::spl_dais_dp,
	&m68000_device::spl_adr16_dp,
	&m68000_device::spl_adr32_dp,
	&m68000_device::smi_ds_dp,
	&m68000_device::dbmi_ds_rel16_dp,
	&m68000_device::smi_ais_dp,
	&m68000_device::smi_aips_dp,
	&m68000_device::smi_pais_dp,
	&m68000_device::smi_das_dp,
	&m68000_device::smi_dais_dp,
	&m68000_device::smi_adr16_dp,
	&m68000_device::smi_adr32_dp,
	&m68000_device::sge_ds_dp,
	&m68000_device::dbge_ds_rel16_dp,
	&m68000_device::sge_ais_dp,
	&m68000_device::sge_aips_dp,
	&m68000_device::sge_pais_dp,
	&m68000_device::sge_das_dp,
	&m68000_device::sge_dais_dp,
	&m68000_device::sge_adr16_dp,
	&m68000_device::sge_adr32_dp,
	&m68000_device::slt_ds_dp,
	&m68000_device::dblt_ds_rel16_dp,
	&m68000_device::slt_ais_dp,
	&m68000_device::slt_aips_dp,
	&m68000_device::slt_pais_dp,
	&m68000_device::slt_das_dp,
	&m68000_device::slt_dais_dp,
	&m68000_device::slt_adr16_dp,
	&m68000_device::slt_adr32_dp,
	&m68000_device::sgt_ds_dp,
	&m68000_device::dbgt_ds_rel16_dp,
	&m68000_device::sgt_ais_dp,
	&m68000_device::sgt_aips_dp,
	&m68000_device::sgt_pais_dp,
	&m68000_device::sgt_das_dp,
	&m68000_device::sgt_dais_dp,
	&m68000_device::sgt_adr16_dp,
	&m68000_device::sgt_adr32_dp,
	&m68000_device::sle_ds_dp,
	&m68000_device::dble_ds_rel16_dp,
	&m68000_device::sle_ais_dp,
	&m68000_device::sle_aips_dp,
	&m68000_device::sle_pais_dp,
	&m68000_device::sle_das_dp,
	&m68000_device::sle_dais_dp,
	&m68000_device::sle_adr16_dp,
	&m68000_device::sle_adr32_dp,
	&m68000_device::bra_rel16_dp,
	&m68000_device::bra_rel8_dp,
	&m68000_device::bsr_rel16_dp,
	&m68000_device::bsr_rel8_dp,
	&m68000_device::bhi_rel16_dp,
	&m68000_device::bhi_rel8_dp,
	&m68000_device::bls_rel16_dp,
	&m68000_device::bls_rel8_dp,
	&m68000_device::bcc_rel16_dp,
	&m68000_device::bcc_rel8_dp,
	&m68000_device::bcs_rel16_dp,
	&m68000_device::bcs_rel8_dp,
	&m68000_device::bne_rel16_dp,
	&m68000_device::bne_rel8_dp,
	&m68000_device::beq_rel16_dp,
	&m68000_device::beq_rel8_dp,
	&m68000_device::bvc_rel16_dp,
	&m68000_device::bvc_rel8_dp,
	&m68000_device::bvs_rel16_dp,
	&m68000_device::bvs_rel8_dp,
	&m68000_device::bpl_rel16_dp,
	&m68000_device::bpl_rel8_dp,
	&m68000_device::bmi_rel16_dp,
	&m68000_device::bmi_rel8_dp,
	&m68000_device::bge_rel16_dp,
	&m68000_device::bge_rel8_dp,
	&m68000_device::blt_rel16_dp,
	&m68000_device::blt_rel8_dp,
	&m68000_device::bgt_rel16_dp,
	&m68000_device::bgt_rel8_dp,
	&m68000_device::ble_rel16_dp,
	&m68000_device::ble_rel8_dp,
	&m68000_device::moveq_imm8o_dd_dp,
	&m68000_device::or_b_ds_dd_dp,
	&m68000_device::or_b_ais_dd_dp,
	&m68000_device::or_b_aips_dd_dp,
	&m68000_device::or_b_pais_dd_dp,
	&m68000_device::or_b_das_dd_dp,
	&m68000_device::or_b_dais_dd_dp,
	&m68000_device::or_b_adr16_dd_dp,
	&m68000_device::or_b_adr32_dd_dp,
	&m68000_device::or_b_dpc_dd_dp,
	&m68000_device::or_b_dpci_dd_dp,
	&m68000_device::or_b_imm8_dd_dp,
	&m68000_device::or_w_ds_dd_dp,
	&m68000_device::or_w_ais_dd_dp,
	&m68000_device::or_w_aips_dd_dp,
	&m68000_device::or_w_pais_dd_dp,
	&m68000_device::or_w_das_dd_dp,
	&m68000_device::or_w_dais_dd_dp,
	&m68000_device::or_w_adr16_dd_dp,
	&m68000_device::or_w_adr32_dd_dp,
	&m68000_device::or_w_dpc_dd_dp,
	&m68000_device::or_w_dpci_dd_dp,
	&m68000_device::or_w_imm16_dd_dp,
	&m68000_device::or_l_ds_dd_dp,
	&m68000_device::or_l_ais_dd_dp,
	&m68000_device::or_l_aips_dd_dp,
	&m68000_device::or_l_pais_dd_dp,
	&m68000_device::or_l_das_dd_dp,
	&m68000_device::or_l_dais_dd_dp,
	&m68000_device::or_l_adr16_dd_dp,
	&m68000_device::or_l_adr32_dd_dp,
	&m68000_device::or_l_dpc_dd_dp,
	&m68000_device::or_l_dpci_dd_dp,
	&m68000_device::or_l_imm32_dd_dp,
	&m68000_device::divu_w_ds_dd_dp,
	&m68000_device::divu_w_ais_dd_dp,
	&m68000_device::divu_w_aips_dd_dp,
	&m68000_device::divu_w_pais_dd_dp,
	&m68000_device::divu_w_das_dd_dp,
	&m68000_device::divu_w_dais_dd_dp,
	&m68000_device::divu_w_adr16_dd_dp,
	&m68000_device::divu_w_adr32_dd_dp,
	&m68000_device::divu_w_dpc_dd_dp,
	&m68000_device::divu_w_dpci_dd_dp,
	&m68000_device::divu_w_imm16_dd_dp,
	&m68000_device::sbcd_ds_dd_dp,
	&m68000_device::sbcd_pais_paid_dp,
	&m68000_device::or_b_dd_ais_dp,
	&m68000_device::or_b_dd_aips_dp,
	&m68000_device::or_b_dd_pais_dp,
	&m68000_device::or_b_dd_das_dp,
	&m68000_device::or_b_dd_dais_dp,
	&m68000_device::or_b_dd_adr16_dp,
	&m68000_device::or_b_dd_adr32_dp,
	&m68000_device::or_w_dd_ais_dp,
	&m68000_device::or_w_dd_aips_dp,
	&m68000_device::or_w_dd_pais_dp,
	&m68000_device::or_w_dd_das_dp,
	&m68000_device::or_w_dd_dais_dp,
	&m68000_device::or_w_dd_adr16_dp,
	&m68000_device::or_w_dd_adr32_dp,
	&m68000_device::or_l_dd_ais_dp,
	&m68000_device::or_l_dd_aips_dp,
	&m68000_device::or_l_dd_pais_dp,
	&m68000_device::or_l_dd_das_dp,
	&m68000_device::or_l_dd_dais_dp,
	&m68000_device::or_l_dd_adr16_dp,
	&m68000_device::or_l_dd_adr32_dp,
	&m68000_device::divs_w_ds_dd_dp,
	&m68000_device::divs_w_ais_dd_dp,
	&m68000_device::divs_w_aips_dd_dp,
	&m68000_device::divs_w_pais_dd_dp,
	&m68000_device::divs_w_das_dd_dp,
	&m68000_device::divs_w_dais_dd_dp,
	&m68000_device::divs_w_adr16_dd_dp,
	&m68000_device::divs_w_adr32_dd_dp,
	&m68000_device::divs_w_dpc_dd_dp,
	&m68000_device::divs_w_dpci_dd_dp,
	&m68000_device::divs_w_imm16_dd_dp,
	&m68000_device::sub_b_ds_dd_dp,
	&m68000_device::sub_b_ais_dd_dp,
	&m68000_device::sub_b_aips_dd_dp,
	&m68000_device::sub_b_pais_dd_dp,
	&m68000_device::sub_b_das_dd_dp,
	&m68000_device::sub_b_dais_dd_dp,
	&m68000_device::sub_b_adr16_dd_dp,
	&m68000_device::sub_b_adr32_dd_dp,
	&m68000_device::sub_b_dpc_dd_dp,
	&m68000_device::sub_b_dpci_dd_dp,
	&m68000_device::sub_b_imm8_dd_dp,
	&m68000_device::sub_w_ds_dd_dp,
	&m68000_device::sub_w_as_dd_dp,
	&m68000_device::sub_w_ais_dd_dp,
	&m68000_device::sub_w_aips_dd_dp,
	&m68000_device::sub_w_pais_dd_dp,
	&m68000_device::sub_w_das_dd_dp,
	&m68000_device::sub_w_dais_dd_dp,
	&m68000_device::sub_w_adr16_dd_dp,
	&m68000_device::sub_w_adr32_dd_dp,
	&m68000_device::sub_w_dpc_dd_dp,
	&m68000_device::sub_w_dpci_dd_dp,
	&m68000_device::sub_w_imm16_dd_dp,
	&m68000_device::sub_l_ds_dd_dp,
	&m68000_device::sub_l_as_dd_dp,
	&m68000_device::sub_l_ais_dd_dp,
	&m68000_device::sub_l_aips_dd_dp,
	&m68000_device::sub_l_pais_dd_dp,
	&m68000_device::sub_l_das_dd_dp,
	&m68000_device::sub_l_dais_dd_dp,
	&m68000_device::sub_l_adr16_dd_dp,
	&m68000_device::sub_l_adr32_dd_dp,
	&m68000_device::sub_l_dpc_dd_dp,
	&m68000_device::sub_l_dpci_dd_dp,
	&m68000_device::sub_l_imm32_dd_dp,
	&m68000_device::suba_w_ds_ad_dp,
	&m68000_device::suba_w_as_ad_dp,
	&m68000_device::suba_w_ais_ad_dp,
	&m68000_device::suba_w_aips_ad_dp,
	&m68000_device::suba_w_pais_ad_dp,
	&m68000_device::suba_w_das_ad_dp,
	&m68000_device::suba_w_dais_ad_dp,
	&m68000_device::suba_w_adr16_ad_dp,
	&m68000_device::suba_w_adr32_ad_dp,
	&m68000_device::suba_w_dpc_ad_dp,
	&m68000_device::suba_w_dpci_ad_dp,
	&m68000_device::suba_w_imm16_ad_dp,
	&m68000_device::subx_b_ds_dd_dp,
	&m68000_device::subx_b_pais_paid_dp,
	&m68000_device::sub_b_dd_ais_dp,
	&m68000_device::sub_b_dd_aips_dp,
	&m68000_device::sub_b_dd_pais_dp,
	&m68000_device::sub_b_dd_das_dp,
	&m68000_device::sub_b_dd_dais_dp,
	&m68000_device::sub_b_dd_adr16_dp,
	&m68000_device::sub_b_dd_adr32_dp,
	&m68000_device::subx_w_ds_dd_dp,
	&m68000_device::subx_w_pais_paid_dp,
	&m68000_device::sub_w_dd_ais_dp,
	&m68000_device::sub_w_dd_aips_dp,
	&m68000_device::sub_w_dd_pais_dp,
	&m68000_device::sub_w_dd_das_dp,
	&m68000_device::sub_w_dd_dais_dp,
	&m68000_device::sub_w_dd_adr16_dp,
	&m68000_device::sub_w_dd_adr32_dp,
	&m68000_device::subx_l_ds_dd_dp,
	&m68000_device::subx_l_pais_paid_dp,
	&m68000_device::sub_l_dd_ais_dp,
	&m68000_device::sub_l_dd_aips_dp,
	&m68000_device::sub_l_dd_pais_dp,
	&m68000_device::sub_l_dd_das_dp,
	&m68000_device::sub_l_dd_dais_dp,
	&m68000_device::sub_l_dd_adr16_dp,
	&m68000_device::sub_l_dd_adr32_dp,
	&m68000_device::suba_l_ds_ad_dp,
	&m68000_device::suba_l_as_ad_dp,
	&m68000_device::suba_l_ais_ad_dp,
	&m68000_device::suba_l_aips_ad_dp,
	&m68000_device::suba_l_pais_ad_dp,
	&m68000_device::suba_l_das_ad_dp,
	&m68000_device::suba_l_dais_ad_dp,
	&m68000_device::suba_l_adr16_ad_dp,
	&m68000_device::suba_l_adr32_ad_dp,
	&m68000_device::suba_l_dpc_ad_dp,
	&m68000_device::suba_l_dpci_ad_dp,
	&m68000_device::suba_l_imm32_ad_dp,
	&m68000_device::cmp_b_ds_dd_dp,
	&m68000_device::cmp_b_ais_dd_dp,
	&m68000_device::cmp_b_aips_dd_dp,
	&m68000_device::cmp_b_pais_dd_dp,
	&m68000_device::cmp_b_das_dd_dp,
	&m68000_device::cmp_b_dais_dd_dp,
	&m68000_device::cmp_b_adr16_dd_dp,
	&m68000_device::cmp_b_adr32_dd_dp,
	&m68000_device::cmp_b_dpc_dd_dp,
	&m68000_device::cmp_b_dpci_dd_dp,
	&m68000_device::cmp_b_imm8_dd_dp,
	&m68000_device::cmp_w_ds_dd_dp,
	&m68000_device::cmp_w_as_dd_dp,
	&m68000_device::cmp_w_ais_dd_dp,
	&m68000_device::cmp_w_aips_dd_dp,
	&m68000_device::cmp_w_pais_dd_dp,
	&m68000_device::cmp_w_das_dd_dp,
	&m68000_device::cmp_w_dais_dd_dp,
	&m68000_device::cmp_w_adr16_dd_dp,
	&m68000_device::cmp_w_adr32_dd_dp,
	&m68000_device::cmp_w_dpc_dd_dp,
	&m68000_device::cmp_w_dpci_dd_dp,
	&m68000_device::cmp_w_imm16_dd_dp,
	&m68000_device::cmp_l_ds_dd_dp,
	&m68000_device::cmp_l_as_dd_dp,
	&m68000_device::cmp_l_ais_dd_dp,
	&m68000_device::cmp_l_aips_dd_dp,
	&m68000_device::cmp_l_pais_dd_dp,
	&m68000_device::cmp_l_das_dd_dp,
	&m68000_device::cmp_l_dais_dd_dp,
	&m68000_device::cmp_l_adr16_dd_dp,
	&m68000_device::cmp_l_adr32_dd_dp,
	&m68000_device::cmp_l_dpc_dd_dp,
	&m68000_device::cmp_l_dpci_dd_dp,
	&m68000_device::cmp_l_imm32_dd_dp,
	&m68000_device::cmpa_w_ds_ad_dp,
	&m68000_device::cmpa_w_as_ad_dp,
	&m68000_device::cmpa_w_ais_ad_dp,
	&m68000_device::cmpa_w_aips_ad_dp,
	&m68000_device::cmpa_w_pais_ad_dp,
	&m68000_device::cmpa_w_das_ad_dp,
	&m68000_device::cmpa_w_dais_ad_dp,
	&m68000_device::cmpa_w_adr16_ad_dp,
	&m68000_device::cmpa_w_adr32_ad_dp,
	&m68000_device::cmpa_w_dpc_ad_dp,
	&m68000_device::cmpa_w_dpci_ad_dp,
	&m68000_device::cmpa_w_imm16_ad_dp,
	&m68000_device::eor_b_dd_ds_dp,
	&m68000_device::cmpm_b_aips_aipd_dp,
	&m68000_device::eor_b_dd_ais_dp,
	&m68000_device::eor_b_dd_aips_dp,
	&m68000_device::eor_b_dd_pais_dp,
	&m68000_device::eor_b_dd_das_dp,
	&m68000_device::eor_b_dd_dais_dp,
	&m68000_device::eor_b_dd_adr16_dp,
	&m68000_device::eor_b_dd_adr32_dp,
	&m68000_device::eor_w_dd_ds_dp,
	&m68000_device::cmpm_w_aips_aipd_dp,
	&m68000_device::eor_w_dd_ais_dp,
	&m68000_device::eor_w_dd_aips_dp,
	&m68000_device::eor_w_dd_pais_dp,
	&m68000_device::eor_w_dd_das_dp,
	&m68000_device::eor_w_dd_dais_dp,
	&m68000_device::eor_w_dd_adr16_dp,
	&m68000_device::eor_w_dd_adr32_dp,
	&m68000_device::eor_l_dd_ds_dp,
	&m68000_device::cmpm_l_aips_aipd_dp,
	&m68000_device::eor_l_dd_ais_dp,
	&m68000_device::eor_l_dd_aips_dp,
	&m68000_device::eor_l_dd_pais_dp,
	&m68000_device::eor_l_dd_das_dp,
	&m68000_device::eor_l_dd_dais_dp,
	&m68000_device::eor_l_dd_adr16_dp,
	&m68000_device::eor_l_dd_adr32_dp,
	&m68000_device::cmpa_l_ds_ad_dp,
	&m68000_device::cmpa_l_as_ad_dp,
	&m68000_device::cmpa_l_ais_ad_dp,
	&m68000_device::cmpa_l_aips_ad_dp,
	&m68000_device::cmpa_l_pais_ad_dp,
	&m68000_device::cmpa_l_das_ad_dp,
	&m68000_device::cmpa_l_dais_ad_dp,
	&m68000_device::cmpa_l_adr16_ad_dp,
	&m68000_device::cmpa_l_adr32_ad_dp,
	&m68000_device::cmpa_l_dpc_ad_dp,
	&m68000_device::cmpa_l_dpci_ad_dp,
	&m68000_device::cmpa_l_imm32_ad_dp,
	&m68000_device::and_b_ds_dd_dp,
	&m68000_device::and_b_ais_dd_dp,
	&m68000_device::and_b_aips_dd_dp,
	&m68000_device::and_b_pais_dd_dp,
	&m68000_device::and_b_das_dd_dp,
	&m68000_device::and_b_dais_dd_dp,
	&m68000_device::and_b_adr16_dd_dp,
	&m68000_device::and_b_adr32_dd_dp,
	&m68000_device::and_b_dpc_dd_dp,
	&m68000_device::and_b_dpci_dd_dp,
	&m68000_device::and_b_imm8_dd_dp,
	&m68000_device::and_w_ds_dd_dp,
	&m68000_device::and_w_ais_dd_dp,
	&m68000_device::and_w_aips_dd_dp,
	&m68000_device::and_w_pais_dd_dp,
	&m68000_device::and_w_das_dd_dp,
	&m68000_device::and_w_dais_dd_dp,
	&m68000_device::and_w_adr16_dd_dp,
	&m68000_device::and_w_adr32_dd_dp,
	&m68000_device::and_w_dpc_dd_dp,
	&m68000_device::and_w_dpci_dd_dp,
	&m68000_device::and_w_imm16_dd_dp,
	&m68000_device::and_l_ds_dd_dp,
	&m68000_device::and_l_ais_dd_dp,
	&m68000_device::and_l_aips_dd_dp,
	&m68000_device::and_l_pais_dd_dp,
	&m68000_device::and_l_das_dd_dp,
	&m68000_device::and_l_dais_dd_dp,
	&m68000_device::and_l_adr16_dd_dp,
	&m68000_device::and_l_adr32_dd_dp,
	&m68000_device::and_l_dpc_dd_dp,
	&m68000_device::and_l_dpci_dd_dp,
	&m68000_device::and_l_imm32_dd_dp,
	&m68000_device::mulu_w_ds_dd_dp,
	&m68000_device::mulu_w_ais_dd_dp,
	&m68000_device::mulu_w_aips_dd_dp,
	&m68000_device::mulu_w_pais_dd_dp,
	&m68000_device::mulu_w_das_dd_dp,
	&m68000_device::mulu_w_dais_dd_dp,
	&m68000_device::mulu_w_adr16_dd_dp,
	&m68000_device::mulu_w_adr32_dd_dp,
	&m68000_device::mulu_w_dpc_dd_dp,
	&m68000_device::mulu_w_dpci_dd_dp,
	&m68000_device::mulu_w_imm16_dd_dp,
	&m68000_device::abcd_ds_dd_dp,
	&m68000_device::abcd_pais_paid_dp,
	&m68000_device::and_b_dd_ais_dp,
	&m68000_device::and_b_dd_aips_dp,
	&m68000_device::and_b_dd_pais_dp,
	&m68000_device::and_b_dd_das_dp,
	&m68000_device::and_b_dd_dais_dp,
	&m68000_device::and_b_dd_adr16_dp,
	&m68000_device::and_b_dd_adr32_dp,
	&m68000_device::exg_dd_ds_dp,
	&m68000_device::exg_ad_as_dp,
	&m68000_device::and_w_dd_ais_dp,
	&m68000_device::and_w_dd_aips_dp,
	&m68000_device::and_w_dd_pais_dp,
	&m68000_device::and_w_dd_das_dp,
	&m68000_device::and_w_dd_dais_dp,
	&m68000_device::and_w_dd_adr16_dp,
	&m68000_device::and_w_dd_adr32_dp,
	&m68000_device::exg_dd_as_dp,
	&m68000_device::and_l_dd_ais_dp,
	&m68000_device::and_l_dd_aips_dp,
	&m68000_device::and_l_dd_pais_dp,
	&m68000_device::and_l_dd_das_dp,
	&m68000_device::and_l_dd_dais_dp,
	&m68000_device::and_l_dd_adr16_dp,
	&m68000_device::and_l_dd_adr32_dp,
	&m68000_device::muls_w_ds_dd_dp,
	&m68000_device::muls_w_ais_dd_dp,
	&m68000_device::muls_w_aips_dd_dp,
	&m68000_device::muls_w_pais_dd_dp,
	&m68000_device::muls_w_das_dd_dp,
	&m68000_device::muls_w_dais_dd_dp,
	&m68000_device::muls_w_adr16_dd_dp,
	&m68000_device::muls_w_adr32_dd_dp,
	&m68000_device::muls_w_dpc_dd_dp,
	&m68000_device::muls_w_dpci_dd_dp,
	&m68000_device::muls_w_imm16_dd_dp,
	&m68000_device::add_b_ds_dd_dp,
	&m68000_device::add_b_ais_dd_dp,
	&m68000_device::add_b_aips_dd_dp,
	&m68000_device::add_b_pais_dd_dp,
	&m68000_device::add_b_das_dd_dp,
	&m68000_device::add_b_dais_dd_dp,
	&m68000_device::add_b_adr16_dd_dp,
	&m68000_device::add_b_adr32_dd_dp,
	&m68000_device::add_b_dpc_dd_dp,
	&m68000_device::add_b_dpci_dd_dp,
	&m68000_device::add_b_imm8_dd_dp,
	&m68000_device::add_w_ds_dd_dp,
	&m68000_device::add_w_as_dd_dp,
	&m68000_device::add_w_ais_dd_dp,
	&m68000_device::add_w_aips_dd_dp,
	&m68000_device::add_w_pais_dd_dp,
	&m68000_device::add_w_das_dd_dp,
	&m68000_device::add_w_dais_dd_dp,
	&m68000_device::add_w_adr16_dd_dp,
	&m68000_device::add_w_adr32_dd_dp,
	&m68000_device::add_w_dpc_dd_dp,
	&m68000_device::add_w_dpci_dd_dp,
	&m68000_device::add_w_imm16_dd_dp,
	&m68000_device::add_l_ds_dd_dp,
	&m68000_device::add_l_as_dd_dp,
	&m68000_device::add_l_ais_dd_dp,
	&m68000_device::add_l_aips_dd_dp,
	&m68000_device::add_l_pais_dd_dp,
	&m68000_device::add_l_das_dd_dp,
	&m68000_device::add_l_dais_dd_dp,
	&m68000_device::add_l_adr16_dd_dp,
	&m68000_device::add_l_adr32_dd_dp,
	&m68000_device::add_l_dpc_dd_dp,
	&m68000_device::add_l_dpci_dd_dp,
	&m68000_device::add_l_imm32_dd_dp,
	&m68000_device::adda_w_ds_ad_dp,
	&m68000_device::adda_w_as_ad_dp,
	&m68000_device::adda_w_ais_ad_dp,
	&m68000_device::adda_w_aips_ad_dp,
	&m68000_device::adda_w_pais_ad_dp,
	&m68000_device::adda_w_das_ad_dp,
	&m68000_device::adda_w_dais_ad_dp,
	&m68000_device::adda_w_adr16_ad_dp,
	&m68000_device::adda_w_adr32_ad_dp,
	&m68000_device::adda_w_dpc_ad_dp,
	&m68000_device::adda_w_dpci_ad_dp,
	&m68000_device::adda_w_imm16_ad_dp,
	&m68000_device::addx_b_ds_dd_dp,
	&m68000_device::addx_b_pais_paid_dp,
	&m68000_device::add_b_dd_ais_dp,
	&m68000_device::add_b_dd_aips_dp,
	&m68000_device::add_b_dd_pais_dp,
	&m68000_device::add_b_dd_das_dp,
	&m68000_device::add_b_dd_dais_dp,
	&m68000_device::add_b_dd_adr16_dp,
	&m68000_device::add_b_dd_adr32_dp,
	&m68000_device::addx_w_ds_dd_dp,
	&m68000_device::addx_w_pais_paid_dp,
	&m68000_device::add_w_dd_ais_dp,
	&m68000_device::add_w_dd_aips_dp,
	&m68000_device::add_w_dd_pais_dp,
	&m68000_device::add_w_dd_das_dp,
	&m68000_device::add_w_dd_dais_dp,
	&m68000_device::add_w_dd_adr16_dp,
	&m68000_device::add_w_dd_adr32_dp,
	&m68000_device::addx_l_ds_dd_dp,
	&m68000_device::addx_l_pais_paid_dp,
	&m68000_device::add_l_dd_ais_dp,
	&m68000_device::add_l_dd_aips_dp,
	&m68000_device::add_l_dd_pais_dp,
	&m68000_device::add_l_dd_das_dp,
	&m68000_device::add_l_dd_dais_dp,
	&m68000_device::add_l_dd_adr16_dp,
	&m68000_device::add_l_dd_adr32_dp,
	&m68000_device::adda_l_ds_ad_dp,
	&m68000_device::adda_l_as_ad_dp,
	&m68000_device::adda_l_ais_ad_dp,
	&m68000_device::adda_l_aips_ad_dp,
	&m68000_device::adda_l_pais_ad_dp,
	&m68000_device::adda_l_das_ad_dp,
	&m68000_device::adda_l_dais_ad_dp,
	&m68000_device::adda_l_adr16_ad_dp,
	&m68000_device::adda_l_adr32_ad_dp,
	&m68000_device::adda_l_dpc_ad_dp,
	&m68000_device::adda_l_dpci_ad_dp,
	&m68000_device::adda_l_imm32_ad_dp,
	&m68000_device::asr_b_imm3_ds_dp,
	&m68000_device::lsr_b_imm3_ds_dp,
	&m68000_device::roxr_b_imm3_ds_dp,
	&m68000_device::ror_b_imm3_ds_dp,
	&m68000_device::asr_b_dd_ds_dp,
	&m68000_device::lsr_b_dd_ds_dp,
	&m68000_device::roxr_b_dd_ds_dp,
	&m68000_device::ror_b_dd_ds_dp,
	&m68000_device::asr_w_imm3_ds_dp,
	&m68000_device::lsr_w_imm3_ds_dp,
	&m68000_device::roxr_w_imm3_ds_dp,
	&m68000_device::ror_w_imm3_ds_dp,
	&m68000_device::asr_w_dd_ds_dp,
	&m68000_device::lsr_w_dd_ds_dp,
	&m68000_device::roxr_w_dd_ds_dp,
	&m68000_device::ror_w_dd_ds_dp,
	&m68000_device::asr_l_imm3_ds_dp,
	&m68000_device::lsr_l_imm3_ds_dp,
	&m68000_device::roxr_l_imm3_ds_dp,
	&m68000_device::ror_l_imm3_ds_dp,
	&m68000_device::asr_l_dd_ds_dp,
	&m68000_device::lsr_l_dd_ds_dp,
	&m68000_device::roxr_l_dd_ds_dp,
	&m68000_device::ror_l_dd_ds_dp,
	&m68000_device::asr_ais_dp,
	&m68000_device::asr_aips_dp,
	&m68000_device::asr_pais_dp,
	&m68000_device::asr_das_dp,
	&m68000_device::asr_dais_dp,
	&m68000_device::asr_adr16_dp,
	&m68000_device::asr_adr32_dp,
	&m68000_device::asl_b_imm3_ds_dp,
	&m68000_device::lsl_b_imm3_ds_dp,
	&m68000_device::roxl_b_imm3_ds_dp,
	&m68000_device::rol_b_imm3_ds_dp,
	&m68000_device::asl_b_dd_ds_dp,
	&m68000_device::lsl_b_dd_ds_dp,
	&m68000_device::roxl_b_dd_ds_dp,
	&m68000_device::rol_b_dd_ds_dp,
	&m68000_device::asl_w_imm3_ds_dp,
	&m68000_device::lsl_w_imm3_ds_dp,
	&m68000_device::roxl_w_imm3_ds_dp,
	&m68000_device::rol_w_imm3_ds_dp,
	&m68000_device::asl_w_dd_ds_dp,
	&m68000_device::lsl_w_dd_ds_dp,
	&m68000_device::roxl_w_dd_ds_dp,
	&m68000_device::rol_w_dd_ds_dp,
	&m68000_device::asl_l_imm3_ds_dp,
	&m68000_device::lsl_l_imm3_ds_dp,
	&m68000_device::roxl_l_imm3_ds_dp,
	&m68000_device::rol_l_imm3_ds_dp,
	&m68000_device::asl_l_dd_ds_dp,
	&m68000_device::lsl_l_dd_ds_dp,
	&m68000_device::roxl_l_dd_ds_dp,
	&m68000_device::rol_l_dd_ds_dp,
	&m68000_device::asl_ais_dp,
	&m68000_device::asl_aips_dp,
	&m68000_device::asl_pais_dp,
	&m68000_device::asl_das_dp,
	&m68000_device::asl_dais_dp,
	&m68000_device::asl_adr16_dp,
	&m68000_device::asl_adr32_dp,
	&m68000_device::lsr_ais_dp,
	&m68000_device::lsr_aips_dp,
	&m68000_device::lsr_pais_dp,
	&m68000_device::lsr_das_dp,
	&m68000_device::lsr_dais_dp,
	&m68000_device::lsr_adr16_dp,
	&m68000_device::lsr_adr32_dp,
	&m68000_device::lsl_ais_dp,
	&m68000_device::lsl_aips_dp,
	&m68000_device::lsl_pais_dp,
	&m68000_device::lsl_das_dp,
	&m68000_device::lsl_dais_dp,
	&m68000_device::lsl_adr16_dp,
	&m68000_device::lsl_adr32_dp,
	&m68000_device::roxr_ais_dp,
	&m68000_device::roxr_aips_dp,
	&m68000_device::roxr_pais_dp,
	&m68000_device::roxr_das_dp,
	&m68000_device::roxr_dais_dp,
	&m68000_device::roxr_adr16_dp,
	&m68000_device::roxr_adr32_dp,
	&m68000_device::roxl_ais_dp,
	&m68000_device::roxl_aips_dp,
	&m68000_device::roxl_pais_dp,
	&m68000_device::roxl_das_dp,
	&m68000_device::roxl_dais_dp,
	&m68000_device::roxl_adr16_dp,
	&m68000_device::roxl_adr32_dp,
	&m68000_device::ror_ais_dp,
	&m68000_device::ror_aips_dp,
	&m68000_device::ror_pais_dp,
	&m68000_device::ror_das_dp,
	&m68000_device::ror_dais_dp,
	&m68000_device::ror_adr16_dp,
	&m68000_device::ror_adr32_dp,
	&m68000_device::rol_ais_dp,
	&m68000_device::rol_aips_dp,
	&m68000_device::rol_pais_dp,
	&m68000_device::rol_das_dp,
	&m68000_device::rol_dais_dp,
	&m68000_device::rol_adr16_dp,
	&m68000_device::rol_adr32_dp,
};
