From: Valentine Fatiev <valentinef@nvidia.com>
Subject: [PATCH] BACKPORT: drivers/net/ethernet/mellanox/mlx5/core/devlink.c

Change-Id: I779901dd4ab8144d6bb8952a3d61f7af3bc72fdf
---
 .../net/ethernet/mellanox/mlx5/core/devlink.c | 476 +++++++++++++++++-
 1 file changed, 469 insertions(+), 7 deletions(-)

--- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
@@ -13,15 +13,59 @@
 #include "sf/sf.h"
 #include "en/tc_ct.h"
 
+#ifdef HAVE_DEVLINK_DRIVERINIT_VAL
+static unsigned int esw_offloads_num_big_groups = ESW_OFFLOADS_DEFAULT_NUM_GROUPS;
+#else
+unsigned int esw_offloads_num_big_groups = ESW_OFFLOADS_DEFAULT_NUM_GROUPS;
+#endif
+module_param_named(num_of_groups, esw_offloads_num_big_groups,
+		   uint, 0644);
+MODULE_PARM_DESC(num_of_groups,
+		 "Eswitch offloads number of big groups in FDB table. Valid range 1 - 1024. Default 15");
+
+#ifdef HAVE_DEVLINK_HAS_FLASH_UPDATE
 static int mlx5_devlink_flash_update(struct devlink *devlink,
+#ifdef HAVE_FLASH_UPDATE_GET_3_PARAMS
 				     struct devlink_flash_update_params *params,
+#else
+				     const char *file_name,
+				     const char *component,
+#endif
 				     struct netlink_ext_ack *extack)
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 
+#ifdef HAVE_DEVLINK_FLASH_UPDATE_PARAMS_HAS_STRUCT_FW
 	return mlx5_firmware_flash(dev, params->fw, extack);
+#else
+	const struct firmware *fw;
+	int err;
+#ifdef HAVE_FLASH_UPDATE_GET_3_PARAMS
+	if (params->component)
+#else
+	if (component)
+#endif
+		return -EOPNOTSUPP;
+
+	err = request_firmware_direct(&fw,
+#ifdef HAVE_FLASH_UPDATE_GET_3_PARAMS
+			params->file_name,
+#else
+			file_name,
+#endif
+			&dev->pdev->dev);
+	if (err)
+		return err;
+
+	err = mlx5_firmware_flash(dev, fw, extack);
+	release_firmware(fw);
+
+	return err;
+#endif /* HAVE_DEVLINK_FLASH_UPDATE_PARAMS_HAS_STRUCT_FW */
 }
+#endif
 
+#if defined(HAVE_DEVLINK_HAS_INFO_GET) && defined(HAVE_DEVLINK_INFO_VERSION_FIXED_PUT)
 static u8 mlx5_fw_ver_major(u32 version)
 {
 	return (version >> 24) & 0xff;
@@ -38,7 +82,6 @@ static u16 mlx5_fw_ver_subminor(u32 vers
 }
 
 #define DEVLINK_FW_STRING_LEN 32
-
 static int
 mlx5_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
 		      struct netlink_ext_ack *extack)
@@ -48,6 +91,12 @@ mlx5_devlink_info_get(struct devlink *de
 	u32 running_fw, stored_fw;
 	int err;
 
+#ifdef HAVE_DEVLINK_INFO_DRIVER_NAME_PUT
+	err = devlink_info_driver_name_put(req, KBUILD_MODNAME);
+	if (err)
+		return err;
+#endif
+
 	err = devlink_info_version_fixed_put(req, "fw.psid", dev->board_id);
 	if (err)
 		return err;
@@ -82,7 +131,9 @@ mlx5_devlink_info_get(struct devlink *de
 					       DEVLINK_INFO_VERSION_GENERIC_FW,
 					       version_str);
 }
+#endif
 
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 static int mlx5_devlink_reload_fw_activate(struct devlink *devlink, struct netlink_ext_ack *extack)
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
@@ -103,6 +154,7 @@ static int mlx5_devlink_reload_fw_activa
 		return err;
 
 	err = mlx5_fw_reset_wait_reset_done(dev);
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER 
 	if (err)
 		return err;
 
@@ -110,7 +162,7 @@ static int mlx5_devlink_reload_fw_activa
 	err = mlx5_health_wait_pci_up(dev);
 	if (err)
 		NL_SET_ERR_MSG_MOD(extack, "FW activate aborted, PCI reads fail after reset");
-
+#endif
 	return err;
 }
 
@@ -132,22 +184,46 @@ static int mlx5_devlink_trigger_fw_live_
 
 	return mlx5_fw_reset_set_live_patch(dev);
 }
+#endif
 
-static int mlx5_devlink_reload_down(struct devlink *devlink, bool netns_change,
+#ifdef HAVE_DEVLINK_HAS_RELOAD_UP_DOWN
+static int mlx5_devlink_reload_down(struct devlink *devlink,
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
+				    bool netns_change,
 				    enum devlink_reload_action action,
 				    enum devlink_reload_limit limit,
-				    struct netlink_ext_ack *extack)
+#elif defined(HAVE_DEVLINK_RELOAD_DOWN_HAS_3_PARAMS)
+			     	    bool netns_change,
+#endif
+ 				    struct netlink_ext_ack *extack)
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 	struct pci_dev *pdev = dev->pdev;
+#ifndef HAVE_DEVL_RESOURCE_REGISTER
+	bool sf_dev_allocated;
+#endif
 	int ret = 0;
 
+#if defined(HAVE_LIGHT_SFS)
 	if (mlx5_dev_is_lightweight(dev)) {
 		if (action != DEVLINK_RELOAD_ACTION_DRIVER_REINIT)
 			return -EOPNOTSUPP;
 		mlx5_unload_one_light(dev);
 		return 0;
 	}
+#endif
+
+#ifndef HAVE_DEVL_RESOURCE_REGISTER
+	sf_dev_allocated = mlx5_sf_dev_allocated(dev);
+	if (sf_dev_allocated) {
+		/* Reload results in deleting SF device which further results in
+		 * unregistering devlink instance while holding devlink_mutext.
+		 * Hence, do not support reload.
+		 */
+		NL_SET_ERR_MSG_MOD(extack, "reload is unsupported when SFs are allocated");
+		return -EOPNOTSUPP;
+	}
+#endif
 
 	if (mlx5_lag_is_active(dev)) {
 		NL_SET_ERR_MSG_MOD(extack, "reload is unsupported in Lag mode");
@@ -159,11 +235,13 @@ static int mlx5_devlink_reload_down(stru
 		return -EOPNOTSUPP;
 	}
 
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 	if (action == DEVLINK_RELOAD_ACTION_FW_ACTIVATE &&
 	    !dev->priv.fw_reset) {
 		NL_SET_ERR_MSG_MOD(extack, "FW activate is unsupported for this function");
 		return -EOPNOTSUPP;
 	}
+#endif
 
 	if (mlx5_eswitch_mode_is_blocked(dev)) {
 		NL_SET_ERR_MSG_MOD(extack, "reload is unsupported if IPSec rules are configured");
@@ -173,9 +251,14 @@ static int mlx5_devlink_reload_down(stru
 	if (mlx5_core_is_pf(dev) && pci_num_vf(pdev))
 		NL_SET_ERR_MSG_MOD(extack, "reload while VFs are present is unfavorable");
 
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 	switch (action) {
 	case DEVLINK_RELOAD_ACTION_DRIVER_REINIT:
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 		mlx5_unload_one_devl_locked(dev, false);
+#else
+		mlx5_unload_one(dev, false);
+#endif
 		break;
 	case DEVLINK_RELOAD_ACTION_FW_ACTIVATE:
 		if (limit == DEVLINK_RELOAD_LIMIT_NO_RESET)
@@ -188,32 +271,55 @@ static int mlx5_devlink_reload_down(stru
 		WARN_ON(1);
 		ret = -EOPNOTSUPP;
 	}
+#else /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
+	mlx5_unload_one(dev, false);
+#endif /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
 
 	return ret;
 }
 
-static int mlx5_devlink_reload_up(struct devlink *devlink, enum devlink_reload_action action,
+static int mlx5_devlink_reload_up(struct devlink *devlink,
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
+				  enum devlink_reload_action action,
 				  enum devlink_reload_limit limit, u32 *actions_performed,
+#endif
 				  struct netlink_ext_ack *extack)
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 	int ret = 0;
 
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 	*actions_performed = BIT(action);
 	switch (action) {
 	case DEVLINK_RELOAD_ACTION_DRIVER_REINIT:
+#if defined(HAVE_LIGHT_SFS)
 		if (mlx5_dev_is_lightweight(dev)) {
+#ifdef HAVE_DEVLINK_HEALTH_REPORT_SUPPORT
 			mlx5_fw_reporters_create(dev);
+#endif
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 			return mlx5_init_one_devl_locked(dev);
+#else
+			return mlx5_init_one(dev);
+#endif
 		}
+#endif // HAVE_LIGHT_SFS
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 		ret = mlx5_load_one_devl_locked(dev, false);
+#else
+		ret = mlx5_load_one(dev, false);
+#endif
 		break;
 	case DEVLINK_RELOAD_ACTION_FW_ACTIVATE:
 		if (limit == DEVLINK_RELOAD_LIMIT_NO_RESET)
 			break;
 		/* On fw_activate action, also driver is reloaded and reinit performed */
 		*actions_performed |= BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT);
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 		ret = mlx5_load_one_devl_locked(dev, true);
+#else
+		ret = mlx5_load_one(dev, true);
+#endif
 		if (ret)
 			return ret;
 		ret = mlx5_fw_reset_verify_fw_complete(dev, extack);
@@ -224,9 +330,47 @@ static int mlx5_devlink_reload_up(struct
 		ret = -EOPNOTSUPP;
 	}
 
+#else /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION*/
+	ret = mlx5_load_one(dev, false);
+#endif /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
 	return ret;
 }
+#endif /* HAVE_DEVLINK_HAS_RELOAD_UP_DOWN */
+
+#if defined(HAVE_DEVLINK_HAS_RELOAD)
+static int load_one_and_check(struct mlx5_core_dev *dev,
+                             struct netlink_ext_ack *extack)
+{
+       int err;
+
+       err = mlx5_load_one(dev, false);
+       if (err == -EUSERS)
+               NL_SET_ERR_MSG_MOD(extack, "IRQs for requested CPU affinity are not available");
+       return err;
+}
+
+static int mlx5_devlink_reload(struct devlink *devlink,
+                              struct netlink_ext_ack *extack)
+{
+       struct mlx5_core_dev *dev = devlink_priv(devlink);
+	bool sf_dev_allocated;
+
+	sf_dev_allocated = mlx5_sf_dev_allocated(dev);
+	if (sf_dev_allocated) {
+		/* Reload results in deleting SF device which further results in
+		 * unregistering devlink instance while holding devlink_mutext.
+		 * Hence, do not support reload.
+		 */
+		NL_SET_ERR_MSG_MOD(extack, "reload is unsupported when SFs are allocated");
+		return -EOPNOTSUPP;
+	}
+
+       mlx5_unload_one(dev, false);
+       return load_one_and_check(dev, extack);
+}
+#endif
 
+#ifdef HAVE_DEVLINK_TRAP_SUPPORT
 static struct mlx5_devlink_trap *mlx5_find_trap_by_id(struct mlx5_core_dev *dev, int trap_id)
 {
 	struct mlx5_devlink_trap *dl_trap;
@@ -279,8 +423,12 @@ static void mlx5_devlink_trap_fini(struc
 
 static int mlx5_devlink_trap_action_set(struct devlink *devlink,
 					const struct devlink_trap *trap,
+#ifdef HAVE_DEVLINK_TRAP_ACTION_SET_4_ARGS
 					enum devlink_trap_action action,
 					struct netlink_ext_ack *extack)
+#else
+					enum devlink_trap_action action)
+#endif
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 	struct mlx5_devlink_trap_event_ctx trap_event_ctx;
@@ -289,7 +437,9 @@ static int mlx5_devlink_trap_action_set(
 	int err;
 
 	if (is_mdev_switchdev_mode(dev)) {
+#ifdef HAVE_DEVLINK_TRAP_ACTION_SET_4_ARGS
 		NL_SET_ERR_MSG_MOD(extack, "Devlink traps can't be set in switchdev mode");
+#endif
 		return -EOPNOTSUPP;
 	}
 
@@ -316,6 +466,7 @@ static int mlx5_devlink_trap_action_set(
 
 	return trap_event_ctx.err;
 }
+#endif /* HAVE_DEVLINK_TRAP_SUPPORT */
 
 static const struct devlink_ops mlx5_devlink_ops = {
 #ifdef CONFIG_MLX5_ESWITCH
@@ -325,6 +476,7 @@ static const struct devlink_ops mlx5_dev
 	.eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
 	.eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
 	.eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
+#ifdef HAVE_DEVLINK_HAS_RATE_FUNCTIONS
 	.rate_leaf_tx_share_set = mlx5_esw_devlink_rate_leaf_tx_share_set,
 	.rate_leaf_tx_max_set = mlx5_esw_devlink_rate_leaf_tx_max_set,
 	/* To build on base kernel. */
@@ -336,21 +488,59 @@ static const struct devlink_ops mlx5_dev
 	.rate_node_del = mlx5_esw_devlink_rate_node_del,
 	.rate_leaf_parent_set = mlx5_esw_devlink_rate_parent_set,
 #endif
+#ifndef HAVE_DEVLINK_PORT_OPS
+#ifdef HAVE_DEVLINK_HAS_PORT_FUNCTION_HW_ADDR_GET
+	.port_function_hw_addr_get = mlx5_devlink_port_fn_hw_addr_get,
+	.port_function_hw_addr_set = mlx5_devlink_port_fn_hw_addr_set,
+#endif
+#ifdef HAVE_DEVLINK_HAS_PORT_FN_ROCE_MIG
+ 	.port_fn_roce_get = mlx5_devlink_port_fn_roce_get,
+ 	.port_fn_roce_set = mlx5_devlink_port_fn_roce_set,
+ 	.port_fn_migratable_get = mlx5_devlink_port_fn_migratable_get,
+ 	.port_fn_migratable_set = mlx5_devlink_port_fn_migratable_set,
+#endif
+#endif /* HAVE_DEVLINK_PORT_OPS */
+#endif /* CONFIG_MLX5_ESWITCH */
 #ifdef CONFIG_MLX5_SF_MANAGER
+#if defined(HAVE_DEVLINK_PORT_ATTRS_PCI_SF_SET_GET_4_PARAMS) || defined(HAVE_DEVLINK_PORT_ATTRS_PCI_SF_SET_GET_5_PARAMS)
 	.port_new = mlx5_devlink_sf_port_new,
+#ifndef HAVE_NDO_PORT_DEL_IN_DEVLINK_PORT
+	.port_del = mlx5_devlink_sf_port_del,
 #endif
+#endif /* defined(HAVE_DEVLINK_PORT_ATTRS_PCI_SF_SET_GET_4_PARAMS) || defined(HAVE_DEVLINK_PORT_ATTRS_PCI_SF_SET_GET_5_PARAMS) */
+#endif /* CONFIG_MLX5_SF_MANAGER */
+#if defined(CONFIG_MLX5_SF_MANAGER) && \
+    defined(HAVE_DEVLINK_HAS_PORT_FUNCTION_STATE_GET) && \
+    !defined(HAVE_DEVLINK_PORT_OPS)
+ 	.port_fn_state_get = mlx5_devlink_sf_port_fn_state_get,
+ 	.port_fn_state_set = mlx5_devlink_sf_port_fn_state_set,
+#endif
+#ifdef HAVE_DEVLINK_HAS_FLASH_UPDATE
 	.flash_update = mlx5_devlink_flash_update,
+#endif /* HAVE_DEVLINK_HAS_FLASH_UPDATE */
+#if defined(HAVE_DEVLINK_HAS_INFO_GET) && defined(HAVE_DEVLINK_INFO_VERSION_FIXED_PUT)
 	.info_get = mlx5_devlink_info_get,
+#endif /* HAVE_DEVLINK_HAS_INFO_GET && HAVE_DEVLINK_INFO_VERSION_FIXED_PUT */
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 	.reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
 			  BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE),
 	.reload_limits = BIT(DEVLINK_RELOAD_LIMIT_NO_RESET),
+#endif
+#ifdef HAVE_DEVLINK_HAS_RELOAD_UP_DOWN
 	.reload_down = mlx5_devlink_reload_down,
 	.reload_up = mlx5_devlink_reload_up,
+#endif /* HAVE_DEVLINK_HAS_RELOAD_UP_DOWN */
+#ifdef HAVE_DEVLINK_HAS_RELOAD
+	.reload = mlx5_devlink_reload,
+#endif
+#ifdef HAVE_DEVLINK_TRAP_SUPPORT
 	.trap_init = mlx5_devlink_trap_init,
 	.trap_fini = mlx5_devlink_trap_fini,
 	.trap_action_set = mlx5_devlink_trap_action_set,
+#endif /* HAVE_DEVLINK_TRAP_SUPPORT */
 };
 
+#ifdef HAVE_DEVLINK_TRAP_SUPPORT
 void mlx5_devlink_trap_report(struct mlx5_core_dev *dev, int trap_id, struct sk_buff *skb,
 			      struct devlink_port *dl_port)
 {
@@ -368,7 +558,11 @@ void mlx5_devlink_trap_report(struct mlx
 			      dl_trap->trap.action);
 		return;
 	}
+#ifdef HAVE_DEVLINK_TRAP_REPORT_5_ARGS
 	devlink_trap_report(devlink, skb, dl_trap->item, dl_port, NULL);
+#else
+	devlink_trap_report(devlink, skb, dl_trap->item, dl_port);
+#endif
 }
 
 int mlx5_devlink_trap_get_num_active(struct mlx5_core_dev *dev)
@@ -398,11 +592,16 @@ int mlx5_devlink_traps_get_action(struct
 	*action = dl_trap->trap.action;
 	return 0;
 }
+#endif /* HAVE_DEVLINK_TRAP_SUPPORT */
 
 struct devlink *mlx5_devlink_alloc(struct device *dev)
 {
+#ifdef HAVE_DEVLINK_ALLOC_GET_3_PARAMS
 	return devlink_alloc(&mlx5_devlink_ops, sizeof(struct mlx5_core_dev),
 			     dev);
+#else
+	return devlink_alloc(&mlx5_devlink_ops, sizeof(struct mlx5_core_dev));
+#endif
 }
 
 void mlx5_devlink_free(struct devlink *devlink)
@@ -410,6 +609,8 @@ void mlx5_devlink_free(struct devlink *d
 	devlink_free(devlink);
 }
 
+#if defined(HAVE_DEVLINK_PARAMS_PUBLISHED) || defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS)
+#ifdef HAVE_DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE
 static int mlx5_devlink_enable_roce_validate(struct devlink *devlink, u32 id,
 					     union devlink_param_value val,
 					     struct netlink_ext_ack *extack)
@@ -429,6 +630,7 @@ static int mlx5_devlink_enable_roce_vali
 
 	return 0;
 }
+#endif
 
 #ifdef CONFIG_MLX5_ESWITCH
 static int mlx5_devlink_large_group_num_validate(struct devlink *devlink, u32 id,
@@ -448,13 +650,16 @@ static int mlx5_devlink_large_group_num_
 
 #endif
 
+#ifdef HAVE_DEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE
 static int mlx5_devlink_eq_depth_validate(struct devlink *devlink, u32 id,
 					  union devlink_param_value val,
 					  struct netlink_ext_ack *extack)
 {
 	return (val.vu32 >= 64 && val.vu32 <= 4096) ? 0 : -EINVAL;
 }
+#endif
 
+#if defined(HAVE_DEVLINK_PARAM_REGISTER) || defined(HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET)
 static int
 mlx5_devlink_hairpin_num_queues_validate(struct devlink *devlink, u32 id,
 					 union devlink_param_value val,
@@ -477,9 +682,13 @@ mlx5_devlink_hairpin_queue_size_validate
 	}
 
 	if (val32 > BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))) {
+#ifdef NL_SET_ERR_MSG_FMT_MOD
 		NL_SET_ERR_MSG_FMT_MOD(
 			extack, "Maximum hairpin queue size is %lu",
 			BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets)));
+#else
+		NL_SET_ERR_MSG_MOD(extack, "Value exceeds maximum hairpin queue size");
+#endif
 		return -EINVAL;
 	}
 
@@ -500,18 +709,32 @@ static void mlx5_devlink_hairpin_params_
 	do_div(link_speed64, 50000);
 
 	value.vu32 = link_speed64;
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(
+#else
+	devlink_param_driverinit_value_set(
+#endif
 		devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, value);
 
 	value.vu32 =
 		BIT(min_t(u32, 16 - MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(dev),
 			  MLX5_CAP_GEN(dev, log_max_hairpin_num_packets)));
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(
+#else
+	devlink_param_driverinit_value_set(
+#endif
 		devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, value);
 }
+#endif
 
 static int mlx5_devlink_ct_max_offloaded_conns_set(struct devlink *devlink, u32 id,
+#ifdef HAVE_DEVLINK_PARAM_SET_FUNCTION_POINTER_HAS_EXTACK
+						   struct devlink_param_gset_ctx *ctx,
+						   struct netlink_ext_ack *extack)
+#else
 						   struct devlink_param_gset_ctx *ctx)
+#endif
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 
@@ -535,8 +758,10 @@ static const struct devlink_param mlx5_d
 			     mlx5_devlink_ct_action_on_nat_conns_get,
 			     mlx5_devlink_ct_action_on_nat_conns_set,
 			     NULL),
+#ifdef HAVE_DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE
 	DEVLINK_PARAM_GENERIC(ENABLE_ROCE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
 			      NULL, NULL, mlx5_devlink_enable_roce_validate),
+#endif
 	DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_CT_MAX_OFFLOADED_CONNS,
 			     "ct_max_offloaded_conns", DEVLINK_PARAM_TYPE_U32,
 			     BIT(DEVLINK_PARAM_CMODE_RUNTIME),
@@ -550,39 +775,66 @@ static const struct devlink_param mlx5_d
 			     NULL, NULL,
 			     mlx5_devlink_large_group_num_validate),
 #endif
+#ifdef HAVE_DEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE
 	DEVLINK_PARAM_GENERIC(IO_EQ_SIZE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
 			      NULL, NULL, mlx5_devlink_eq_depth_validate),
 	DEVLINK_PARAM_GENERIC(EVENT_EQ_SIZE, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
 			      NULL, NULL, mlx5_devlink_eq_depth_validate),
+#endif
 };
 
 static void mlx5_devlink_set_params_init_values(struct devlink *devlink)
 {
+#ifdef HAVE_DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
+#endif
 	union devlink_param_value value;
 
+#ifdef HAVE_DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE
 	value.vbool = MLX5_CAP_GEN(dev, roce) && !mlx5_dev_is_lightweight(dev);
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(devlink,
+#else
+	devlink_param_driverinit_value_set(devlink,
+#endif
 					DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
 					value);
+#endif
 
 #ifdef CONFIG_MLX5_ESWITCH
-	value.vu32 = ESW_OFFLOADS_DEFAULT_NUM_GROUPS;
+	value.vu32 = esw_offloads_num_big_groups;
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(devlink,
+#else
+	devlink_param_driverinit_value_set(devlink,
+#endif
 					MLX5_DEVLINK_PARAM_ID_ESW_LARGE_GROUP_NUM,
 					value);
 #endif
 
+#ifdef HAVE_DEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE
 	value.vu32 = MLX5_COMP_EQ_SIZE;
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(devlink,
+#else
+	devlink_param_driverinit_value_set(devlink,
+#endif
 					DEVLINK_PARAM_GENERIC_ID_IO_EQ_SIZE,
 					value);
 
 	value.vu32 = MLX5_NUM_ASYNC_EQE;
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(devlink,
+#else
+	devlink_param_driverinit_value_set(devlink,
+#endif
 					DEVLINK_PARAM_GENERIC_ID_EVENT_EQ_SIZE,
 					value);
+#endif
 }
+#endif /* defined(HAVE_DEVLINK_PARAMS_PUBLISHED) || defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS) */
+
+#if defined(HAVE_DEVLINK_PARAM_REGISTER) || defined(HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET)
 
 static const struct devlink_param mlx5_devlink_eth_params[] = {
 	DEVLINK_PARAM_GENERIC(ENABLE_ETH, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
@@ -606,15 +858,26 @@ static int mlx5_devlink_eth_params_regis
 	if (!mlx5_eth_supported(dev))
 		return 0;
 
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	err = devl_params_register(devlink, mlx5_devlink_eth_params,
+#else
+	err = devlink_params_register(devlink, mlx5_devlink_eth_params,
+#endif
 				   ARRAY_SIZE(mlx5_devlink_eth_params));
 	if (err)
 		return err;
 
 	value.vbool = !mlx5_dev_is_lightweight(dev);
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(devlink,
+#else
+	devlink_param_driverinit_value_set(devlink,
+#endif
 					DEVLINK_PARAM_GENERIC_ID_ENABLE_ETH,
 					value);
+#ifdef HAVE_DEVLINK_PARAM_PUBLISH
+	devlink_param_publish(devlink, &mlx5_devlink_eth_params[0]);
+#endif
 
 	mlx5_devlink_hairpin_params_init_values(devlink);
 
@@ -628,7 +891,15 @@ static void mlx5_devlink_eth_params_unre
 	if (!mlx5_eth_supported(dev))
 		return;
 
+#ifdef HAVE_DEVLINK_PARAM_PUBLISH
+	devlink_param_unpublish(devlink, mlx5_devlink_eth_params);
+#endif
+
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_params_unregister(devlink, mlx5_devlink_eth_params,
+#else
+	devlink_params_unregister(devlink, mlx5_devlink_eth_params,
+#endif
 			       ARRAY_SIZE(mlx5_devlink_eth_params));
 }
 
@@ -658,15 +929,26 @@ static int mlx5_devlink_rdma_params_regi
 	if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND))
 		return 0;
 
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	err = devl_params_register(devlink, mlx5_devlink_rdma_params,
+#else
+	err = devlink_params_register(devlink, mlx5_devlink_rdma_params,
+#endif
 				   ARRAY_SIZE(mlx5_devlink_rdma_params));
 	if (err)
 		return err;
 
 	value.vbool = !mlx5_dev_is_lightweight(dev);
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(devlink,
+#else
+	devlink_param_driverinit_value_set(devlink,
+#endif
 					DEVLINK_PARAM_GENERIC_ID_ENABLE_RDMA,
 					value);
+#ifdef HAVE_DEVLINK_PARAM_PUBLISH
+	devlink_param_publish(devlink, &mlx5_devlink_rdma_params[0]);
+#endif
 	return 0;
 }
 
@@ -675,7 +957,14 @@ static void mlx5_devlink_rdma_params_unr
 	if (!IS_ENABLED(CONFIG_MLX5_INFINIBAND))
 		return;
 
+#ifdef HAVE_DEVLINK_PARAM_PUBLISH
+	devlink_param_unpublish(devlink, &mlx5_devlink_rdma_params[0]);
+#endif
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_params_unregister(devlink, mlx5_devlink_rdma_params,
+#else
+	devlink_params_unregister(devlink, mlx5_devlink_rdma_params,
+#endif
 			       ARRAY_SIZE(mlx5_devlink_rdma_params));
 }
 
@@ -693,15 +982,26 @@ static int mlx5_devlink_vnet_params_regi
 	if (!mlx5_vnet_supported(dev))
 		return 0;
 
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	err = devl_params_register(devlink, mlx5_devlink_vnet_params,
+#else
+	err = devlink_params_register(devlink, mlx5_devlink_vnet_params,
+#endif
 				   ARRAY_SIZE(mlx5_devlink_vnet_params));
 	if (err)
 		return err;
 
 	value.vbool = !mlx5_dev_is_lightweight(dev);
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(devlink,
+#else
+	devlink_param_driverinit_value_set(devlink,
+#endif
 					DEVLINK_PARAM_GENERIC_ID_ENABLE_VNET,
 					value);
+#ifdef HAVE_DEVLINK_PARAM_PUBLISH
+	 devlink_param_publish(devlink, &mlx5_devlink_vnet_params[0]);
+#endif
 	return 0;
 }
 
@@ -712,7 +1012,14 @@ static void mlx5_devlink_vnet_params_unr
 	if (!mlx5_vnet_supported(dev))
 		return;
 
+#ifdef HAVE_DEVLINK_PARAM_PUBLISH
+	 devlink_param_unpublish(devlink, &mlx5_devlink_vnet_params[0]);
+#endif
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_params_unregister(devlink, mlx5_devlink_vnet_params,
+#else
+	devlink_params_unregister(devlink, mlx5_devlink_vnet_params,
+#endif
 			       ARRAY_SIZE(mlx5_devlink_vnet_params));
 }
 
@@ -786,13 +1093,21 @@ static int mlx5_devlink_max_uc_list_para
 	if (!MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list_wr_supported))
 		return 0;
 
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	err = devl_params_register(devlink, mlx5_devlink_max_uc_list_params,
+#else
+	err = devlink_params_register(devlink, mlx5_devlink_max_uc_list_params,
+#endif
 				   ARRAY_SIZE(mlx5_devlink_max_uc_list_params));
 	if (err)
 		return err;
 
 	value.vu32 = 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list);
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_param_driverinit_value_set(devlink,
+#else
+	devlink_param_driverinit_value_set(devlink,
+#endif
 					DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
 					value);
 	return 0;
@@ -806,22 +1121,41 @@ mlx5_devlink_max_uc_list_params_unregist
 	if (!MLX5_CAP_GEN_MAX(dev, log_max_current_uc_list_wr_supported))
 		return;
 
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_params_unregister(devlink, mlx5_devlink_max_uc_list_params,
+#else
+	devlink_params_unregister(devlink, mlx5_devlink_max_uc_list_params,
+#endif
 			       ARRAY_SIZE(mlx5_devlink_max_uc_list_params));
 }
+#endif /* HAVE_DEVLINK_PARAM_PUBLISH */
 
+#ifdef HAVE_DEVLINK_TRAP_SUPPORT
+#ifdef HAVE_DEVLINK_TRAP_GROUPS_REGISTER
 #define MLX5_TRAP_DROP(_id, _group_id)					\
 	DEVLINK_TRAP_GENERIC(DROP, DROP, _id,				\
 			     DEVLINK_TRAP_GROUP_GENERIC_ID_##_group_id, \
 			     DEVLINK_TRAP_METADATA_TYPE_F_IN_PORT)
+#else
+#define MLX5_TRAP_DROP(_id, group)					\
+	DEVLINK_TRAP_GENERIC(DROP, DROP, _id,				\
+			     DEVLINK_TRAP_GROUP_GENERIC(group),         \
+			     DEVLINK_TRAP_METADATA_TYPE_F_IN_PORT)
+#endif
 
 static const struct devlink_trap mlx5_traps_arr[] = {
 	MLX5_TRAP_DROP(INGRESS_VLAN_FILTER, L2_DROPS),
+#ifdef HAVE_DEVLINK_TRAP_DMAC_FILTER
 	MLX5_TRAP_DROP(DMAC_FILTER, L2_DROPS),
+#endif
 };
 
 static const struct devlink_trap_group mlx5_trap_groups_arr[] = {
+#ifdef HAVE_DEVLINK_TRAP_GROUP_GENERIC_2_ARGS
 	DEVLINK_TRAP_GROUP_GENERIC(L2_DROPS, 0),
+#else
+	DEVLINK_TRAP_GROUP_GENERIC(L2_DROPS),
+#endif
 };
 
 int mlx5_devlink_traps_register(struct devlink *devlink)
@@ -829,46 +1163,116 @@ int mlx5_devlink_traps_register(struct d
 	struct mlx5_core_dev *core_dev = devlink_priv(devlink);
 	int err;
 
+#ifdef HAVE_DEVLINK_TRAP_GROUPS_REGISTER
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 	err = devl_trap_groups_register(devlink, mlx5_trap_groups_arr,
 					ARRAY_SIZE(mlx5_trap_groups_arr));
+#else
+	err = devlink_trap_groups_register(devlink, mlx5_trap_groups_arr,
+					   ARRAY_SIZE(mlx5_trap_groups_arr));
+#endif /* HAVE_DEVL_TRAP_GROUPS_REGISTER */
 	if (err)
 		return err;
+#endif /* HAVE_DEVLINK_TRAP_GROUPS_REGISTER */
 
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 	err = devl_traps_register(devlink, mlx5_traps_arr, ARRAY_SIZE(mlx5_traps_arr),
 				  &core_dev->priv);
+#else
+	err = devlink_traps_register(devlink, mlx5_traps_arr, ARRAY_SIZE(mlx5_traps_arr),
+				     &core_dev->priv);
+#endif
+#ifdef HAVE_DEVLINK_TRAP_GROUPS_REGISTER
 	if (err)
 		goto err_trap_group;
 	return 0;
 
 err_trap_group:
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 	devl_trap_groups_unregister(devlink, mlx5_trap_groups_arr,
 				    ARRAY_SIZE(mlx5_trap_groups_arr));
+#else
+	devlink_trap_groups_unregister(devlink, mlx5_trap_groups_arr,
+				       ARRAY_SIZE(mlx5_trap_groups_arr));
+#endif /* HAVE_DEVL_TRAP_GROUPS_REGISTER */
+#endif /* HAVE_DEVLINK_TRAP_GROUPS_REGISTER */
 	return err;
 }
 
 void mlx5_devlink_traps_unregister(struct devlink *devlink)
 {
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 	devl_traps_unregister(devlink, mlx5_traps_arr, ARRAY_SIZE(mlx5_traps_arr));
+#else
+	devlink_traps_unregister(devlink, mlx5_traps_arr, ARRAY_SIZE(mlx5_traps_arr));
+#endif
+#ifdef HAVE_DEVLINK_TRAP_GROUPS_REGISTER
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 	devl_trap_groups_unregister(devlink, mlx5_trap_groups_arr,
 				    ARRAY_SIZE(mlx5_trap_groups_arr));
+#else
+	devlink_trap_groups_unregister(devlink, mlx5_trap_groups_arr,
+				       ARRAY_SIZE(mlx5_trap_groups_arr));
+#endif /* HAVE_DEVL_TRAP_GROUPS_REGISTER */
+#endif /* HAVE_DEVLINK_TRAP_GROUPS_REGISTER */
 }
+#endif /* HAVE_DEVLINK_TRAP_SUPPORT */
 
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
 int mlx5_devlink_params_register(struct devlink *devlink)
+#else
+int mlx5_devlink_params_register(struct devlink *devlink, struct device *pdev)
+#endif
 {
+#if (!defined(HAVE_DEVLINK_PARAMS_PUBLISHED) && !defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS)) && defined(CONFIG_MLX5_ESWITCH)
+	struct mlx5_core_dev *priv_dev;
+	struct mlx5_eswitch *eswitch;
+#endif
 	int err;
 
+#ifdef HAVE_DEVLINK_SET_FEATURES
+	devlink_set_features(devlink, DEVLINK_F_RELOAD);
+#endif
+
 	/* Here only the driver init params should be registered.
 	 * Runtime params should be registered by the code which
 	 * behaviour they configure.
 	 */
 
+#ifndef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	err = devlink_register(devlink, pdev);
+	if (err)
+		return err;
+#endif
+
+#if defined(HAVE_DEVLINK_PARAMS_PUBLISHED) || defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS)
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	err = devl_params_register(devlink, mlx5_devlink_params,
-				   ARRAY_SIZE(mlx5_devlink_params));
+#else
+	err = devlink_params_register(devlink, mlx5_devlink_params,
+#endif
+				      ARRAY_SIZE(mlx5_devlink_params));
 	if (err)
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
 		return err;
+#else
+		goto params_reg_err;
+#endif
+
+#ifndef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
+	err = mlx5_register_eswitch_params(devlink_priv(devlink));
+	if (err)
+		goto esw_params_reg_err;
+#ifndef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	err = mlx5_register_devlink_fw_params(devlink_priv(devlink));
+	if (err)
+		goto fw_params_reg_err;
+#endif
+#endif
 
 	mlx5_devlink_set_params_init_values(devlink);
 
+#if defined(HAVE_DEVLINK_PARAM_REGISTER) || defined(HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET)
 	err = mlx5_devlink_auxdev_params_register(devlink);
 	if (err)
 		goto auxdev_reg_err;
@@ -876,28 +1280,81 @@ int mlx5_devlink_params_register(struct
 	err = mlx5_devlink_max_uc_list_params_register(devlink);
 	if (err)
 		goto max_uc_list_err;
+#endif /* HAVE_DEVLINK_PARAM_REGISTER */
 
+#ifdef HAVE_DEVLINK_PARAMS_PUBLISHED
+	devlink_params_publish(devlink);
+#endif /* defined(HAVE_DEVLINK_PARAMS_PUBLISHED) && !defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS) */
 	return 0;
 
+#if defined(HAVE_DEVLINK_PARAM_REGISTER) || defined(HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET)
 max_uc_list_err:
 	mlx5_devlink_auxdev_params_unregister(devlink);
 auxdev_reg_err:
+#endif /* HAVE_DEVLINK_PARAM_REGISTER */
+#ifndef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
+#ifndef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	mlx5_unregister_devlink_fw_params(devlink_priv(devlink));
+fw_params_reg_err:
+#endif
+	mlx5_unregister_eswitch_params(devlink_priv(devlink));
+esw_params_reg_err:
+#endif
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_params_unregister(devlink, mlx5_devlink_params,
+#else
+	devlink_params_unregister(devlink, mlx5_devlink_params,
+#endif
 			       ARRAY_SIZE(mlx5_devlink_params));
+#ifndef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+params_reg_err:
+	devlink_unregister(devlink);
+#endif
+#elif defined(CONFIG_MLX5_ESWITCH)
+	priv_dev = devlink_priv(devlink);
+	eswitch = priv_dev->priv.eswitch;
+	if (eswitch && mlx5_esw_vport_match_metadata_supported(eswitch))
+		eswitch->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
+#endif /* HAVE_DEVLINK_PARAMS_PUBLISHED || HAVE_DEVLINK_REGISTER_GET_1_PARAMS */
 	return err;
 }
 
 void mlx5_devlink_params_unregister(struct devlink *devlink)
 {
+#if defined(HAVE_DEVLINK_PARAMS_PUBLISHED) || defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS)
+#ifndef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	devlink_params_unpublish(devlink);
+#endif
+#if defined(HAVE_DEVLINK_PARAM_REGISTER) || defined(HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET)
 	mlx5_devlink_max_uc_list_params_unregister(devlink);
 	mlx5_devlink_auxdev_params_unregister(devlink);
+#endif
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_params_unregister(devlink, mlx5_devlink_params,
+#else
+	devlink_params_unregister(devlink, mlx5_devlink_params,
+#endif
 			       ARRAY_SIZE(mlx5_devlink_params));
+#ifndef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
+#ifndef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	mlx5_unregister_devlink_fw_params(devlink_priv(devlink));
+#endif
+	mlx5_unregister_eswitch_params(devlink_priv(devlink));
+#endif
+#endif /* (HAVE_DEVLINK_PARAMS_PUBLISHED || HAVE_DEVLINK_REGISTER_GET_1_PARAMS */
+#ifndef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	devlink_unregister(devlink);
+#endif
 }
 
 int
 mlx5_devlink_ct_action_on_nat_conns_set(struct devlink *devlink, u32 id,
+#ifdef HAVE_DEVLINK_PARAM_SET_FUNCTION_POINTER_HAS_EXTACK
+					struct devlink_param_gset_ctx *ctx,
+					struct netlink_ext_ack *extack)
+#else
 					struct devlink_param_gset_ctx *ctx)
+#endif
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 
@@ -917,7 +1374,12 @@ mlx5_devlink_ct_action_on_nat_conns_get(
 
 int
 mlx5_devlink_ct_labels_mapping_set(struct devlink *devlink, u32 id,
+#ifdef HAVE_DEVLINK_PARAM_SET_FUNCTION_POINTER_HAS_EXTACK
+				   struct devlink_param_gset_ctx *ctx,
+				   struct netlink_ext_ack *extack)
+#else
 				   struct devlink_param_gset_ctx *ctx)
+#endif
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 
