From: Valentine Fatiev <valentinef@nvidia.com>
Subject: [PATCH] BACKPORT: drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c

Change-Id: If602dfea37251d304529f4e846974997b407697b
---
 .../ethernet/mellanox/mlx5/core/fw_reset.c    | 135 ++++++++++++++++++
 1 file changed, 135 insertions(+)

--- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
@@ -29,8 +29,10 @@ struct mlx5_fw_reset {
 	unsigned long reset_flags;
 	u8 reset_method;
 	struct timer_list timer;
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 	struct completion done;
 	int ret;
+#endif
 };
 
 enum {
@@ -54,12 +56,22 @@ static void mlx5_set_fw_rst_ack(struct m
 	iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing);
 }
 
+#if defined(HAVE_DEVLINK_PARAMS_PUBLISHED) || defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS)
 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id,
+#ifdef HAVE_DEVLINK_PARAM_SET_FUNCTION_POINTER_HAS_EXTACK
+						     struct devlink_param_gset_ctx *ctx,
+						     struct netlink_ext_ack *extack)
+#else
 						     struct devlink_param_gset_ctx *ctx)
+#endif
 {
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 	struct mlx5_fw_reset *fw_reset;
 
+#if !defined(HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET) && defined(HAVE_DEVLINK_PARAM_REGISTER)
+	if (mlx5_dev_is_lightweight(dev))
+		return -EOPNOTSUPP;
+#endif
 	fw_reset = dev->priv.fw_reset;
 
 	if (ctx->val.vbool)
@@ -75,12 +87,17 @@ static int mlx5_fw_reset_enable_remote_d
 	struct mlx5_core_dev *dev = devlink_priv(devlink);
 	struct mlx5_fw_reset *fw_reset;
 
+#if !defined(HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET) && defined(HAVE_DEVLINK_PARAM_REGISTER)
+	if (mlx5_dev_is_lightweight(dev))
+		return -EOPNOTSUPP;
+#endif
 	fw_reset = dev->priv.fw_reset;
 
 	ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
 				   &fw_reset->reset_flags);
 	return 0;
 }
+#endif
 
 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
 			     u8 reset_type_sel, u8 sync_resp, bool sync_start)
@@ -140,6 +157,7 @@ static int mlx5_fw_reset_get_request_inf
 	return mlx5_reg_mfrl_query(dev, NULL, NULL, NULL, reset_method, sync_flow);
 }
 
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
 					     struct netlink_ext_ack *extack)
 {
@@ -218,12 +236,14 @@ int mlx5_fw_reset_verify_fw_complete(str
 	NL_SET_ERR_MSG_MOD(extack, "Sync reset did not complete successfully");
 	return rst_state;
 }
+#endif /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
 
 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
 {
 	return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
 }
 
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded)
 {
 	struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
@@ -233,19 +253,26 @@ static void mlx5_fw_reset_complete_reloa
 	if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
 		complete(&fw_reset->done);
 	} else {
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 		if (!unloaded)
 			mlx5_unload_one(dev, false);
 		if (mlx5_health_wait_pci_up(dev))
 			mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
 		else
+#endif
 			mlx5_load_one(dev, true);
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 		devl_lock(devlink);
+#endif
 		devlink_remote_reload_actions_performed(devlink, 0,
 							BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
 							BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 		devl_unlock(devlink);
+#endif
 	}
 }
+#endif
 
 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
 {
@@ -274,11 +301,32 @@ static void mlx5_sync_reset_reload_work(
 	struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
 						      reset_reload_work);
 	struct mlx5_core_dev *dev = fw_reset->dev;
+#ifndef HAVE_DEVL_TRAP_GROUPS_REGISTER
+	int err;
+#endif
 
 	cancel_delayed_work(&fw_reset->reset_timeout_work);
 	mlx5_sync_reset_clear_reset_requested(dev, false);
 	mlx5_enter_error_state(dev, true);
+#ifndef HAVE_DEVL_TRAP_GROUPS_REGISTER
+	mlx5_unload_one(dev, false);
+	err = mlx5_health_wait_pci_up(dev);
+	if (err) {
+		mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
+#ifndef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
+		return;
+#endif
+	}
+#endif /* HAVE_DEVL_TRAP_GROUPS_REGISTER */
+
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
+#ifndef HAVE_DEVL_TRAP_GROUPS_REGISTER
+	fw_reset->ret = err;
+#endif
 	mlx5_fw_reset_complete_reload(dev, false);
+#else /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
+	mlx5_load_one(dev, true);
+#endif /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
 }
 
 #define MLX5_RESET_POLL_INTERVAL	(HZ / 10)
@@ -514,8 +562,16 @@ static int mlx5_pci_link_toggle(struct m
 		return pcibios_err_to_errno(err);
 
 	/* Check link */
+#ifdef HAVE_PCI_DEV_LINK_ACTIVE_REPORTING
 	if (!bridge->link_active_reporting) {
 		mlx5_core_warn(dev, "No PCI link reporting capability\n");
+#else
+	err = pci_read_config_dword(bridge, cap + PCI_EXP_LNKCAP, &reg32);
+	if (err)
+		return err;
+	if (!(reg32 & PCI_EXP_LNKCAP_DLLLARC)) {
+		mlx5_core_warn(dev, "No PCI link reporting capability (0x%08x)\n", reg32);
+#endif
 		msleep(1000);
 		goto restore;
 	}
@@ -661,9 +717,16 @@ static void mlx5_sync_reset_now_event(st
 	}
 
 	mlx5_enter_error_state(dev, true);
+#ifndef HAVE_DEVL_TRAP_GROUPS_REGISTER
+	mlx5_unload_one(dev, false);
+#endif
 done:
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 	fw_reset->ret = err;
 	mlx5_fw_reset_complete_reload(dev, false);
+#else
+	mlx5_load_one(dev, true);
+#endif
 }
 
 static void mlx5_sync_reset_unload_event(struct work_struct *work)
@@ -690,9 +753,11 @@ static void mlx5_sync_reset_unload_event
 	else
 		mlx5_enter_error_state(dev, true);
 
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 	if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags))
 		mlx5_unload_one_devl_locked(dev, false);
 	else
+#endif
 		mlx5_unload_one(dev, false);
 
 	mlx5_set_fw_rst_ack(dev);
@@ -718,7 +783,9 @@ static void mlx5_sync_reset_unload_event
 	if (!reset_action) {
 		mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n",
 			      rst_state);
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 		fw_reset->ret = -ETIMEDOUT;
+#endif
 		goto done;
 	}
 
@@ -727,12 +794,18 @@ static void mlx5_sync_reset_unload_event
 		err = mlx5_sync_pci_reset(dev, fw_reset->reset_method);
 		if (err) {
 			mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, err %d\n", err);
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 			fw_reset->ret = err;
+#endif
 		}
 	}
 
 done:
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 	mlx5_fw_reset_complete_reload(dev, true);
+#else /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
+	mlx5_load_one(dev, true);
+#endif /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
 }
 
 static void mlx5_sync_reset_abort_event(struct work_struct *work)
@@ -805,6 +878,7 @@ static int fw_reset_event_notifier(struc
 	return NOTIFY_OK;
 }
 
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
 {
 	unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
@@ -823,13 +897,18 @@ int mlx5_fw_reset_wait_reset_done(struct
 	}
 	err = fw_reset->ret;
 	if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
+#ifdef HAVE_DEVL_TRAP_GROUPS_REGISTER
 		mlx5_unload_one_devl_locked(dev, false);
 		mlx5_load_one_devl_locked(dev, true);
+#else
+		mlx5_load_one(dev, true);
+#endif
 	}
 out:
 	clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
 	return err;
 }
+#endif /* HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION */
 
 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
 {
@@ -869,16 +948,48 @@ void mlx5_drain_fw_reset(struct mlx5_cor
 	cancel_delayed_work(&fw_reset->reset_timeout_work);
 }
 
+#if defined(HAVE_DEVLINK_PARAMS_PUBLISHED) || defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS)
 static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
+#ifdef HAVE_DEVLINK_PARAM_GENERIC_ID_ENABLE_REMOTE_DEV_RESET
 	DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME),
 			      mlx5_fw_reset_enable_remote_dev_reset_get,
 			      mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
+#else
+	DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ENABLE_REMOTE_DEV_RESET,
+			     "enable_remote_dev_reset", DEVLINK_PARAM_TYPE_BOOL,
+			     BIT(DEVLINK_PARAM_CMODE_RUNTIME),
+			     mlx5_fw_reset_enable_remote_dev_reset_get,
+			     mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
+#endif
 };
 
+#ifndef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
+int mlx5_register_devlink_fw_params(struct mlx5_core_dev *dev)
+{
+	if (!dev->priv.fw_reset)
+		return 0;
+
+	return devlink_params_register(priv_to_devlink(dev), mlx5_fw_reset_devlink_params,
+				       ARRAY_SIZE(mlx5_fw_reset_devlink_params));
+}
+
+void mlx5_unregister_devlink_fw_params(struct mlx5_core_dev *dev)
+{
+	if (!dev->priv.fw_reset)
+		return;
+
+	devlink_params_unregister(priv_to_devlink(dev), mlx5_fw_reset_devlink_params,
+				  ARRAY_SIZE(mlx5_fw_reset_devlink_params));
+}
+#endif /* !HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET */
+#endif /* HAVE_DEVLINK_PARAMS_PUBLISHED || HAVE_DEVLINK_REGISTER_GET_1_PARAMS */
+
 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
 {
 	struct mlx5_fw_reset *fw_reset;
+#if defined(HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET) || defined(HAVE_DEVLINK_REGISTER_GET_1_PARAMS)
 	int err;
+#endif
 
 	if (!MLX5_CAP_MCAM_REG(dev, mfrl))
 		return 0;
@@ -895,6 +1006,7 @@ int mlx5_fw_reset_init(struct mlx5_core_
 	fw_reset->dev = dev;
 	dev->priv.fw_reset = fw_reset;
 
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	err = devl_params_register(priv_to_devlink(dev),
 				   mlx5_fw_reset_devlink_params,
 				   ARRAY_SIZE(mlx5_fw_reset_devlink_params));
@@ -903,6 +1015,19 @@ int mlx5_fw_reset_init(struct mlx5_core_
 		kfree(fw_reset);
 		return err;
 	}
+#else
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+
+	err = devlink_params_register(priv_to_devlink(dev),
+				      mlx5_fw_reset_devlink_params,
+				      ARRAY_SIZE(mlx5_fw_reset_devlink_params));
+	if (err) {
+		destroy_workqueue(fw_reset->wq);
+		kfree(fw_reset);
+		return err;
+	}
+#endif
+#endif
 
 	INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
 	INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
@@ -912,7 +1037,9 @@ int mlx5_fw_reset_init(struct mlx5_core_
 	INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
 	INIT_DELAYED_WORK(&fw_reset->reset_timeout_work, mlx5_sync_reset_timeout_work);
 
+#ifdef HAVE_DEVLINK_RELOAD_DOWN_SUPPORT_RELOAD_ACTION
 	init_completion(&fw_reset->done);
+#endif
 	return 0;
 }
 
@@ -923,9 +1050,17 @@ void mlx5_fw_reset_cleanup(struct mlx5_c
 	if (!fw_reset)
 		return;
 
+#ifdef HAVE_DEVL_PARAM_DRIVERINIT_VALUE_GET
 	devl_params_unregister(priv_to_devlink(dev),
 			       mlx5_fw_reset_devlink_params,
 			       ARRAY_SIZE(mlx5_fw_reset_devlink_params));
+#else
+#ifdef HAVE_DEVLINK_REGISTER_GET_1_PARAMS
+	devlink_params_unregister(priv_to_devlink(dev),
+				  mlx5_fw_reset_devlink_params,
+				  ARRAY_SIZE(mlx5_fw_reset_devlink_params));
+#endif
+#endif
 	destroy_workqueue(fw_reset->wq);
 	kfree(dev->priv.fw_reset);
 }
