From: Valentine Fatiev <valentinef@nvidia.com>
Subject: [PATCH] BACKPORT: drivers/infiniband/hw/mlx5/umr.c

Change-Id: I06bf4471b17d82fb5f0907c06cb6738a661a30ae
---
 drivers/infiniband/hw/mlx5/umr.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

--- a/drivers/infiniband/hw/mlx5/umr.c
+++ b/drivers/infiniband/hw/mlx5/umr.c
@@ -468,7 +468,9 @@ static void *mlx5r_umr_alloc_xlt(size_t
 	size_t size;
 	void *res = NULL;
 
+#ifdef HAVE_STATIC_ASSERT
 	static_assert(PAGE_SIZE % MLX5_UMR_FLEX_ALIGNMENT == 0);
+#endif
 
 	/*
 	 * MLX5_IB_UPD_XLT_ATOMIC doesn't signal an atomic context just that the
@@ -675,7 +677,17 @@ _mlx5r_umr_update_mr_pas(struct mlx5_ib_
 	mlx5r_umr_set_update_xlt_data_seg(&wqe.data_seg, &sg);
 
 	curr_entry = entry;
+#ifdef rdma_umem_for_each_dma_block
 	rdma_umem_for_each_dma_block(mr->umem, &biter, BIT(mr->page_shift)) {
+#elif defined(HAVE_SG_APPEND_TABLE)
+	rdma_for_each_block(mr->umem->sgt_append.sgt.sgl, &biter,
+			    mr->umem->sgt_append.sgt.nents,
+			    BIT(mr->page_shift)) {
+#else
+	rdma_for_each_block(mr->umem->sg_head.sgl, &biter,
+			    mr->umem->nmap,
+			    BIT(mr->page_shift)) {
+#endif
 		if (curr_entry == entry + sg.length) {
 			dma_sync_single_for_device(ddev, sg.addr, sg.length,
 						   DMA_TO_DEVICE);
