From: Valentine Fatiev <valentinef@nvidia.com>
Subject: [PATCH] BACKPORT: drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

Change-Id: I687b3957740c4cfb1a91ddce8b78da2b9e53f9bd
---
 .../ethernet/mellanox/mlx5/core/en_stats.h    | 54 ++++++++++++++++++-
 1 file changed, 52 insertions(+), 2 deletions(-)

--- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.h
@@ -33,6 +33,10 @@
 #ifndef __MLX5_EN_STATS_H__
 #define __MLX5_EN_STATS_H__
 
+#ifdef HAVE_BASECODE_EXTRAS
+#include <uapi/linux/ethtool.h>
+#endif
+
 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
 	(*(u64 *)((char *)ptr + dsc[i].offset))
 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
@@ -114,9 +118,11 @@ void mlx5e_stats_update_ndo_stats(struct
 
 void mlx5e_stats_pause_get(struct mlx5e_priv *priv,
 			   struct ethtool_pause_stats *pause_stats);
+#ifdef HAVE_NDO_GET_FEC_STATS
 void mlx5e_stats_fec_get(struct mlx5e_priv *priv,
 			 struct ethtool_fec_stats *fec_stats);
-
+#endif
+#ifdef HAVE_NDO_ETH_PHY_STATS
 void mlx5e_stats_eth_phy_get(struct mlx5e_priv *priv,
 			     struct ethtool_eth_phy_stats *phy_stats);
 void mlx5e_stats_eth_mac_get(struct mlx5e_priv *priv,
@@ -126,8 +132,11 @@ void mlx5e_stats_eth_ctrl_get(struct mlx
 void mlx5e_stats_rmon_get(struct mlx5e_priv *priv,
 			  struct ethtool_rmon_stats *rmon,
 			  const struct ethtool_rmon_hist_range **ranges);
+#endif
+#ifdef HAVE_NDO_LINK_EXT_STATS
 void mlx5e_get_link_ext_stats(struct net_device *dev,
 			      struct ethtool_link_ext_stats *stats);
+#endif
 
 /* Concrete NIC Stats */
 
@@ -160,15 +169,17 @@ struct mlx5e_sw_stats {
 	u64 rx_csum_complete_tail;
 	u64 rx_csum_complete_tail_slow;
 	u64 rx_csum_unnecessary_inner;
+#ifdef HAVE_XDP_SUPPORT
 	u64 rx_xdp_drop;
 	u64 rx_xdp_redirect;
 	u64 rx_xdp_tx_xmit;
+	u64 rx_xdp_tx_nops;
 	u64 rx_xdp_tx_mpwqe;
 	u64 rx_xdp_tx_inlnw;
-	u64 rx_xdp_tx_nops;
 	u64 rx_xdp_tx_full;
 	u64 rx_xdp_tx_err;
 	u64 rx_xdp_tx_cqe;
+#endif
 	u64 tx_csum_none;
 	u64 tx_csum_partial;
 	u64 tx_csum_partial_inner;
@@ -179,6 +190,12 @@ struct mlx5e_sw_stats {
 	u64 tx_cqes;
 	u64 tx_queue_wake;
 	u64 tx_cqe_err;
+#ifdef CONFIG_COMPAT_LRO_ENABLED_IPOIB
+	u64 rx_sw_lro_aggregated;
+	u64 rx_sw_lro_flushed;
+	u64 rx_sw_lro_no_desc;
+#endif
+#ifdef HAVE_XDP_SUPPORT
 	u64 tx_xdp_xmit;
 	u64 tx_xdp_mpwqe;
 	u64 tx_xdp_inlnw;
@@ -186,12 +203,27 @@ struct mlx5e_sw_stats {
 	u64 tx_xdp_full;
 	u64 tx_xdp_err;
 	u64 tx_xdp_cqes;
+#endif
+#ifdef HAVE_BASECODE_EXTRAS
+	u64 tx_cqe_compress_blks;
+	u64 tx_cqe_compress_pkts;
+#endif
 	u64 rx_wqe_err;
 	u64 rx_mpwqe_filler_cqes;
 	u64 rx_mpwqe_filler_strides;
 	u64 rx_oversize_pkts_sw_drop;
 	u64 rx_buff_alloc_err;
 	u64 rx_cqe_compress_blks;
+#ifndef HAVE_PAGE_POOL_DEFRAG_PAGE
+	u64 rx_cache_reuse;
+	u64 rx_cache_full;
+	u64 rx_cache_empty;
+	u64 rx_cache_busy;
+	u64 rx_cache_ext;
+	u64 rx_cache_rdc;
+	u64 rx_cache_alloc;
+	u64 rx_cache_waive;
+#endif
 	u64 rx_cqe_compress_pkts;
 	u64 rx_congst_umr;
 #ifdef CONFIG_MLX5_EN_ARFS
@@ -355,8 +387,10 @@ struct mlx5e_rq_stats {
 	u64 mcast_packets;
 	u64 ecn_mark;
 	u64 removed_vlan_packets;
+#ifdef HAVE_XDP_SUPPORT
 	u64 xdp_drop;
 	u64 xdp_redirect;
+#endif
 	u64 wqe_err;
 	u64 mpwqe_filler_cqes;
 	u64 mpwqe_filler_strides;
@@ -364,6 +398,16 @@ struct mlx5e_rq_stats {
 	u64 buff_alloc_err;
 	u64 cqe_compress_blks;
 	u64 cqe_compress_pkts;
+#ifndef HAVE_PAGE_POOL_DEFRAG_PAGE
+	u64 cache_reuse;
+	u64 cache_full;
+	u64 cache_empty;
+	u64 cache_busy;
+	u64 cache_ext;
+	u64 cache_rdc;
+	u64 cache_alloc;
+	u64 cache_waive;
+#endif
 	u64 congst_umr;
 #ifdef CONFIG_MLX5_EN_ARFS
 	u64 arfs_add;
@@ -435,10 +479,15 @@ struct mlx5e_sq_stats {
 	u64 recover;
 	/* dirtied @completion */
 	u64 cqes ____cacheline_aligned_in_smp;
+#ifdef HAVE_BASECODE_EXTRAS
+	u64 cqe_compress_blks;
+	u64 cqe_compress_pkts;
+#endif
 	u64 wake;
 	u64 cqe_err;
 };
 
+#ifdef HAVE_XDP_SUPPORT
 struct mlx5e_xdpsq_stats {
 	u64 xmit;
 	u64 mpwqe;
@@ -449,6 +498,7 @@ struct mlx5e_xdpsq_stats {
 	/* dirtied @completion */
 	u64 cqes ____cacheline_aligned_in_smp;
 };
+#endif
 
 struct mlx5e_ch_stats {
 	u64 events;
