[
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32b",
    "arguments": [
      "uint32_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32B"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32cb",
    "arguments": [
      "uint32_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32CB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32cd",
    "arguments": [
      "uint32_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Xm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32CX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32ch",
    "arguments": [
      "uint32_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32CH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32cw",
    "arguments": [
      "uint32_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32CW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32d",
    "arguments": [
      "uint32_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Xm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32X"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32h",
    "arguments": [
      "uint32_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32H"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__crc32w",
    "arguments": [
      "uint32_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Wn"
      },
      "b": {
        "register": "Wm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CRC32W"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaba_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabal_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabaq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_high_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UABDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdl_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabdq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabds_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabs_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vabsq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_p64",
    "arguments": [
      "poly64x1_t a",
      "poly64x1_t b"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vadd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddhn_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_high_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddl_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlv_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddlvq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDLV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_p128",
    "arguments": [
      "poly128_t a",
      "poly128_t b"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EOR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddv_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP",
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddvq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UADDW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaddw_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaesdq_u8",
    "arguments": [
      "uint8x16_t data",
      "uint8x16_t key"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Vd.16B"
      },
      "key": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AESD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaeseq_u8",
    "arguments": [
      "uint8x16_t data",
      "uint8x16_t key"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Vd.16B"
      },
      "key": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AESE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaesimcq_u8",
    "arguments": [
      "uint8x16_t data"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AESIMC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaesmcq_u8",
    "arguments": [
      "uint8x16_t data"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "data": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AESMC"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vand_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "AND"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vandq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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        "AND"
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    "SIMD_ISA": "Neon",
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        "AND"
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    "SIMD_ISA": "Neon",
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        "AND"
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        "AND"
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        "BCAX"
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        "BCAX"
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        "BCAX"
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        "BCAX"
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        "BCAX"
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        "BCAX"
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        "BCAX"
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        "BCAX"
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        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_s8",
    "arguments": [
      "uint8x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "uint64x1_t c"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbsl_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
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      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
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      "c": {
        "register": "Vm.8B"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_f16",
    "arguments": [
      "uint16x8_t a",
      "float16x8_t b",
      "float16x8_t c"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
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      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_f32",
    "arguments": [
      "uint32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_f64",
    "arguments": [
      "uint64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_p16",
    "arguments": [
      "uint16x8_t a",
      "poly16x8_t b",
      "poly16x8_t c"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b",
      "poly64x2_t c"
    ],
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      "value": "poly64x2_t"
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      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_p8",
    "arguments": [
      "uint8x16_t a",
      "poly8x16_t b",
      "poly8x16_t c"
    ],
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      "value": "poly8x16_t"
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      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
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      "c": {
        "register": "Vm.16B"
      }
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    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
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      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
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      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_s32",
    "arguments": [
      "uint32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_s64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b",
      "int64x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
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      "c": {
        "register": "Vm.16B"
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    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_s8",
    "arguments": [
      "uint8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
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      "value": "int8x16_t"
    },
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      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
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      "c": {
        "register": "Vm.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
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      "c": {
        "register": "Vm.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
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        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "uint64x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
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  {
    "SIMD_ISA": "Neon",
    "name": "vbslq_u8",
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      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "BSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcadd_rot270_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H "
      },
      "b": {
        "register": "Vm.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcadd_rot270_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S "
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcadd_rot90_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H "
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcadd_rot90_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S "
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot270_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H "
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot270_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S "
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot270_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D "
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot90_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H "
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot90_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S "
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaddq_rot90_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D "
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcage_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcage_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcage_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaged_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcageh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcageq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcageq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcageq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcages_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagt_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagt_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagt_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagtd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagth_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagtq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagtq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagtq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcagts_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcale_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcale_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcale_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaled_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaleh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaleq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaleq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaleq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcales_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalt_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalt_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalt_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaltd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalth_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaltq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaltq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcaltq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcalts_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FACGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_p64",
    "arguments": [
      "poly64x1_t a",
      "poly64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a",
      "uint16x4_t b"
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t a",
      "uint32x2_t b"
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      "value": "uint32x2_t"
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        "register": "Vn.2S"
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      "b": {
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      "A32",
      "A64"
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_u64",
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      "uint64x1_t a",
      "uint64x1_t b"
    ],
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceq_u8",
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      "uint8x8_t a",
      "uint8x8_t b"
    ],
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      "value": "uint8x8_t"
    },
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
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      [
        "CMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float64_t a",
      "float64_t b"
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      "value": "uint64_t"
    },
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        "register": "Dn"
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        "register": "Dm"
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      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int64_t b"
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      "value": "uint64_t"
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        "register": "Dn"
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        "register": "Dm"
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      [
        "CMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint64_t a",
      "uint64_t b"
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      "value": "uint64_t"
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        "register": "Dn"
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        "register": "Dm"
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      [
        "CMEQ"
      ]
    ]
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    "SIMD_ISA": "Neon",
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      "float16_t a",
      "float16_t b"
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      "value": "uint16_t"
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        "register": "Hn"
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        "register": "Hm"
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      [
        "FCMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x8_t b"
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      "value": "uint16x8_t"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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      "A64"
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      [
        "FCMEQ"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a",
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      "A32",
      "A64"
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      [
        "FCMEQ"
      ]
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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      [
        "FCMEQ"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "poly64x2_t b"
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        "register": "Vn.2D"
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        "CMEQ"
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        "CMEQ"
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      "int16x8_t b"
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        "CMEQ"
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        "CMEQ"
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        "CMEQ"
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      "float32_t b"
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        "register": "Sn"
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        "register": "Sm"
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        "FCMEQ"
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        "FCMEQ"
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        "FCMEQ"
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        "FCMEQ"
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    "SIMD_ISA": "Neon",
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        "CMEQ"
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        "register": "Vn.8B"
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        "CMEQ"
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        "CMEQ"
      ]
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    "SIMD_ISA": "Neon",
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  {
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      ]
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  {
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        "CMEQ"
      ]
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  {
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        "CMEQ"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t a"
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        "CMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint64x1_t a"
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        "register": "Dn"
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        "CMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t a"
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        "register": "Vn.8B"
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        "CMEQ"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float64_t a"
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        "register": "Dn"
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        "FCMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int64_t a"
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      "value": "uint64_t"
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        "register": "Dn"
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        "CMEQ"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64_t a"
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      "value": "uint64_t"
    },
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        "register": "Dn"
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    ],
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      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16_t a"
    ],
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      "value": "uint16_t"
    },
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        "register": "Hn"
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    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
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      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vceqzs_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMEQ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcge_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcged_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcged_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcged_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgeq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcges_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
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      "A64"
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      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x2_t a"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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    },
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      "A64"
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      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_s64",
    "arguments": [
      "int64x1_t a"
    ],
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      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
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      "A64"
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      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgez_s8",
    "arguments": [
      "int8x8_t a"
    ],
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      "value": "uint8x8_t"
    },
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      "a": {
        "register": "Vn.8B"
      }
    },
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      "A64"
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      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float64_t a"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      }
    },
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      "A64"
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      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezd_s64",
    "arguments": [
      "int64_t a"
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      }
    },
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      "A64"
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      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezh_f16",
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      "float16_t a"
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      "value": "uint16_t"
    },
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      "a": {
        "register": "Hn"
      }
    },
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      "A64"
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      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16x8_t a"
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "A64"
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      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a"
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      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
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    },
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      "A64"
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      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_f64",
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      "float64x2_t a"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
      }
    },
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      "A64"
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      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_s16",
    "arguments": [
      "int16x8_t a"
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
      }
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      "A64"
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      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_s32",
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      "int32x4_t a"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
      }
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      "A64"
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      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgezq_s64",
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      "int64x2_t a"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "A64"
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      [
        "CMGE"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "int8x16_t a"
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      "value": "uint8x16_t"
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      "a": {
        "register": "Vn.16B"
      }
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      "A64"
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      [
        "CMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float32_t a"
    ],
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      "value": "uint32_t"
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      "a": {
        "register": "Sn"
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      "A64"
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      [
        "FCMGE"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x4_t a",
      "float16x4_t b"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float32x2_t a",
      "float32x2_t b"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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        "register": "Vm.2S"
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      "v7",
      "A32",
      "A64"
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      [
        "FCMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcgt_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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      "A64"
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      [
        "FCMGT"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "int16x4_t a",
      "int16x4_t b"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A32",
      "A64"
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      [
        "CMGT"
      ]
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    "SIMD_ISA": "Neon",
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      "int32x2_t b"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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      [
        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int64x1_t a",
      "int64x1_t b"
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      "value": "uint64x1_t"
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        "register": "Dn"
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      "b": {
        "register": "Dm"
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      [
        "CMGT"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a",
      "int8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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      "A32",
      "A64"
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      [
        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a",
      "uint16x4_t b"
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A32",
      "A64"
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        "CMHI"
      ]
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    "SIMD_ISA": "Neon",
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      "uint32x2_t a",
      "uint32x2_t b"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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      [
        "CMHI"
      ]
    ]
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    "SIMD_ISA": "Neon",
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      "uint64x1_t a",
      "uint64x1_t b"
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dn"
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        "register": "Dm"
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      [
        "CMHI"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t a",
      "uint8x8_t b"
    ],
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
    ],
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      [
        "CMHI"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float64_t a",
      "float64_t b"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
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        "register": "Dm"
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    ],
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      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int64_t a",
      "int64_t b"
    ],
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      "value": "uint64_t"
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        "register": "Dn"
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      "b": {
        "register": "Dm"
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    },
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    ],
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      [
        "CMGT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "uint64_t a",
      "uint64_t b"
    ],
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      "value": "uint64_t"
    },
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        "register": "Dn"
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      "b": {
        "register": "Dm"
      }
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      [
        "CMHI"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float16_t a",
      "float16_t b"
    ],
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      "value": "uint16_t"
    },
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        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
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      "A64"
    ],
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      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
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      "value": "uint16x8_t"
    },
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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      "A64"
    ],
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      [
        "FCMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a",
      "float32x4_t b"
    ],
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      "value": "uint32x4_t"
    },
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        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
    ],
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      [
        "FCMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
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      "value": "uint64x2_t"
    },
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        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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    ],
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      [
        "FCMGT"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
      }
    },
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      "A32",
      "A64"
    ],
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      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_s32",
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      "int32x4_t a",
      "int32x4_t b"
    ],
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      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
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      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgts_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcgtz_f16",
    "arguments": [
      "float16x4_t a"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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    },
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      "A32",
      "A64"
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      [
        "FCMGT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "float32x2_t a"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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        "FCMGT"
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  {
    "SIMD_ISA": "Neon",
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      "float64x1_t a"
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dn"
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        "FCMGT"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.4H"
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        "CMGT"
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  {
    "SIMD_ISA": "Neon",
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      "a": {
        "register": "Vn.2S"
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      "A64"
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      [
        "CMGT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "int64x1_t a"
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      "value": "uint64x1_t"
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        "register": "Dn"
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        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a"
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "A64"
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        "CMGT"
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  {
    "SIMD_ISA": "Neon",
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      "float64_t a"
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      "value": "uint64_t"
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        "register": "Dn"
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        "FCMGT"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Dn"
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        "CMGT"
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  {
    "SIMD_ISA": "Neon",
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      "float16_t a"
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      "value": "uint16_t"
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        "register": "Hn"
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        "FCMGT"
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  {
    "SIMD_ISA": "Neon",
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      "float16x8_t a"
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      "a": {
        "register": "Vn.8H"
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      "A64"
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        "FCMGT"
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    "SIMD_ISA": "Neon",
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      "float32x4_t a"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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        "FCMGT"
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  {
    "SIMD_ISA": "Neon",
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      "float64x2_t a"
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      "a": {
        "register": "Vn.2D"
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        "FCMGT"
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      "a": {
        "register": "Vn.8H"
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      "A64"
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      [
        "CMGT"
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    "SIMD_ISA": "Neon",
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      "int32x4_t a"
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      "a": {
        "register": "Vn.4S"
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        "CMGT"
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    "SIMD_ISA": "Neon",
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      "int64x2_t a"
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        "register": "Vn.2D"
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        "CMGT"
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        "register": "Vn.16B"
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        "CMGT"
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      "float32_t a"
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      "value": "uint32_t"
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        "register": "Sn"
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        "FCMGT"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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        "FCMGE"
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      "float32x2_t b"
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        "register": "Vn.2S"
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        "register": "Vm.2S"
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      "A64"
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        "FCMGE"
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        "register": "Dn"
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        "register": "Dm"
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        "FCMGE"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A64"
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        "CMGE"
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        "register": "Vn.2S"
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        "register": "Vm.2S"
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      "A64"
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        "register": "Dn"
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        "register": "Dm"
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        "CMGE"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "register": "Vn.2S"
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        "register": "Dn"
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        "register": "Dm"
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        "CMHS"
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    "SIMD_ISA": "Neon",
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      "uint8x8_t b"
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        "register": "Vn.8B"
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        "register": "Vm.8B"
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        "register": "Dn"
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        "register": "Dm"
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        "FCMGE"
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    "SIMD_ISA": "Neon",
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      "int64_t b"
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        "register": "Dn"
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        "register": "Dm"
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        "CMGE"
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    "SIMD_ISA": "Neon",
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        "register": "Dn"
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        "register": "Dm"
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        "CMHS"
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      "float16_t b"
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      "value": "uint16_t"
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        "register": "Hn"
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        "register": "Hm"
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        "FCMGE"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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        "FCMGE"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "FCMGE"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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        "CMGE"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "CMGE"
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  },
  {
    "SIMD_ISA": "Neon",
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      "int8x16_t b"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A32",
      "A64"
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        "CMGE"
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  {
    "SIMD_ISA": "Neon",
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      "uint16x8_t a",
      "uint16x8_t b"
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
      }
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      "A32",
      "A64"
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      [
        "CMHS"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcleq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcles_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_f16",
    "arguments": [
      "float16x4_t a"
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    "return_type": {
      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_f32",
    "arguments": [
      "float32x2_t a"
    ],
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      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_f64",
    "arguments": [
      "float64x1_t a"
    ],
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      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
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      "A64"
    ],
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      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_s16",
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      "int16x4_t a"
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x2_t a"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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    },
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      "A64"
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      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_s64",
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      "int64x1_t a"
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
      }
    },
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      "A64"
    ],
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      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclez_s8",
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      "int8x8_t a"
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      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
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      "A64"
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      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezd_f64",
    "arguments": [
      "float64_t a"
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      }
    },
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      "A64"
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      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezd_s64",
    "arguments": [
      "int64_t a"
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      "value": "uint64_t"
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      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezh_f16",
    "arguments": [
      "float16_t a"
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      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
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      "A64"
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      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_f16",
    "arguments": [
      "float16x8_t a"
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "A32",
      "A64"
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      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_f32",
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      "float32x4_t a"
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      "value": "uint32x4_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
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      "A64"
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      [
        "FCMLE"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_f64",
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      "float64x2_t a"
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      "value": "uint64x2_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
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      "A64"
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      [
        "FCMLE"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_s16",
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      "int16x8_t a"
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
      }
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      "A64"
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      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_s32",
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      "int32x4_t a"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
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      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_s64",
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      "int64x2_t a"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
      }
    },
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      "A64"
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      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezq_s8",
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      "int8x16_t a"
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      "value": "uint8x16_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
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      [
        "CMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclezs_f32",
    "arguments": [
      "float32_t a"
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      "value": "uint32_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
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      [
        "FCMLE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int16x4_t a"
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      "value": "int16x4_t"
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      "a": {
        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_s32",
    "arguments": [
      "int32x2_t a"
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      "value": "int32x2_t"
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      "a": {
        "register": "Vn.2S"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_s8",
    "arguments": [
      "int8x8_t a"
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      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_u16",
    "arguments": [
      "uint16x4_t a"
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    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLS"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcls_u32",
    "arguments": [
      "uint32x2_t a"
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      "value": "int32x2_t"
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      "a": {
        "register": "Vn.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcls_u8",
    "arguments": [
      "uint8x8_t a"
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      "value": "int8x8_t"
    },
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      "a": {
        "register": "Vn.8B"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_s16",
    "arguments": [
      "int16x8_t a"
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      "value": "int16x8_t"
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      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_s32",
    "arguments": [
      "int32x4_t a"
    ],
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      "value": "int32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_s8",
    "arguments": [
      "int8x16_t a"
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    "return_type": {
      "value": "int8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_u16",
    "arguments": [
      "uint16x8_t a"
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    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_u32",
    "arguments": [
      "uint32x4_t a"
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      "value": "int32x4_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclsq_u8",
    "arguments": [
      "uint8x16_t a"
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      "value": "int8x16_t"
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      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLS"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclt_f16",
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      "float16x4_t a",
      "float16x4_t b"
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      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
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      "value": "uint32x2_t"
    },
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
      }
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      "A32",
      "A64"
    ],
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      [
        "FCMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclt_f64",
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      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
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      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclt_s32",
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      "int32x2_t a",
      "int32x2_t b"
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      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclt_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMGT"
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  {
    "SIMD_ISA": "Neon",
    "name": "vclt_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
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    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclt_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
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      "A64"
    ],
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      [
        "CMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
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      "A64"
    ],
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      [
        "CMHI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclth_f16",
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      "float16_t a",
      "float16_t b"
    ],
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      "value": "uint16_t"
    },
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      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
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      "A64"
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      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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        "FCMGT"
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    "SIMD_ISA": "Neon",
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      "float32x4_t a",
      "float32x4_t b"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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        "FCMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float64x2_t a",
      "float64x2_t b"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      "A64"
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      [
        "FCMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int32x4_t a",
      "int32x4_t b"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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        "CMGT"
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  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_s64",
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      "int64x2_t a",
      "int64x2_t b"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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        "CMGT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int8x16_t a",
      "int8x16_t b"
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      "value": "uint8x16_t"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "A32",
      "A64"
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      [
        "CMGT"
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  {
    "SIMD_ISA": "Neon",
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      "uint16x8_t a",
      "uint16x8_t b"
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
      }
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      "A32",
      "A64"
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        "CMHI"
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  {
    "SIMD_ISA": "Neon",
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      "uint32x4_t a",
      "uint32x4_t b"
    ],
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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        "CMHI"
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  {
    "SIMD_ISA": "Neon",
    "name": "vcltq_u64",
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      "uint64x2_t a",
      "uint64x2_t b"
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      "value": "uint64x2_t"
    },
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      "A64"
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      [
        "CMHI"
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  {
    "SIMD_ISA": "Neon",
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      "uint8x16_t a",
      "uint8x16_t b"
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      "value": "uint8x16_t"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "A32",
      "A64"
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      [
        "CMHI"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclts_f32",
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      "float32_t a",
      "float32_t b"
    ],
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      "value": "uint32_t"
    },
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      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMGT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltz_f16",
    "arguments": [
      "float16x4_t a"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "A32",
      "A64"
    ],
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      [
        "FCMLT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float32x2_t a"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "A64"
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      [
        "FCMLT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float64x1_t a"
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
      }
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      [
        "FCMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int16x4_t a"
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      "a": {
        "register": "Vn.4H"
      }
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      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x2_t a"
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        "register": "Vn.2S"
      }
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        "CMLT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "int64x1_t a"
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dn"
      }
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      "A64"
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      [
        "CMLT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a"
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      "value": "uint8x8_t"
    },
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      "a": {
        "register": "Vn.8B"
      }
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        "CMLT"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcltzd_f64",
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      "float64_t a"
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dn"
      }
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        "FCMLT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int64_t a"
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      "value": "uint64_t"
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      "a": {
        "register": "Dn"
      }
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        "CMLT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16_t a"
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      "value": "uint16_t"
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        "register": "Hn"
      }
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        "FCMLT"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcltzq_f16",
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "A64"
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      [
        "FCMLT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a"
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      "a": {
        "register": "Vn.4S"
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        "FCMLT"
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  },
  {
    "SIMD_ISA": "Neon",
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      "float64x2_t a"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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        "FCMLT"
      ]
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    "SIMD_ISA": "Neon",
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      "int16x8_t a"
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
      }
    },
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        "CMLT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int32x4_t a"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
      }
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        "CMLT"
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  {
    "SIMD_ISA": "Neon",
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      "int64x2_t a"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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        "CMLT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int8x16_t a"
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        "register": "Vn.16B"
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        "CMLT"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float32_t a"
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      "value": "uint32_t"
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      "a": {
        "register": "Sn"
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        "FCMLT"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int16x4_t a"
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      "value": "int16x4_t"
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        "register": "Vn.4H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclz_s32",
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      "int32x2_t a"
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        "register": "Vn.2S"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclz_s8",
    "arguments": [
      "int8x8_t a"
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        "register": "Vn.8B"
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      "A32",
      "A64"
    ],
    "instructions": [
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        "CLZ"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclz_u16",
    "arguments": [
      "uint16x4_t a"
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        "register": "Vn.4H"
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      "A32",
      "A64"
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        "CLZ"
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    "SIMD_ISA": "Neon",
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      "uint32x2_t a"
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        "register": "Vn.2S"
      }
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      "A32",
      "A64"
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    "instructions": [
      [
        "CLZ"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vclz_u8",
    "arguments": [
      "uint8x8_t a"
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclzq_s16",
    "arguments": [
      "int16x8_t a"
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      "value": "int16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclzq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclzq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CLZ"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vclzq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
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      "float16x8_t b"
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      "A64"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot180_f32",
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      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b"
    ],
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      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.4S"
      }
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      "A32",
      "A64"
    ],
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      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float64x2_t r",
      "float64x2_t a",
      "float64x2_t b"
    ],
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      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
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        "register": "Vd.2D"
      }
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      "A64"
    ],
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      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
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      "value": "float16x8_t"
    },
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      "a": {},
      "b": {},
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        "minimum": 0,
        "maximum": 1
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        "register": "Vd.8H"
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x2_t b",
      "const int lane"
    ],
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      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
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        "minimum": 0,
        "maximum": 0
      },
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        "register": "Vd.4S"
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    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
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      "value": "float16x8_t"
    },
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      "a": {},
      "b": {},
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        "minimum": 0,
        "maximum": 3
      },
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        "register": "Vd.8H"
      }
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      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b",
      "const int lane"
    ],
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      "value": "float32x4_t"
    },
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        "maximum": 1
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        "register": "Vd.4S"
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      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b"
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      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {},
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        "register": "Vd.8H"
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      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b"
    ],
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      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.4S"
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      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot270_f64",
    "arguments": [
      "float64x2_t r",
      "float64x2_t a",
      "float64x2_t b"
    ],
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      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.2D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
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      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x2_t b",
      "const int lane"
    ],
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      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
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        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
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      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
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        "register": "Vd.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b",
      "const int lane"
    ],
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      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_f64",
    "arguments": [
      "float64x2_t r",
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_lane_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_lane_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x2_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_laneq_f16",
    "arguments": [
      "float16x8_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcmlaq_rot90_laneq_f32",
    "arguments": [
      "float32x4_t r",
      "float32x4_t a",
      "float32x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcnt_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcnt_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcnt_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcntq_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcntq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcntq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CNT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_f16",
    "arguments": [
      "float16x4_t low",
      "float16x4_t high"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.4H"
      },
      "low": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_f32",
    "arguments": [
      "float32x2_t low",
      "float32x2_t high"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.2S"
      },
      "low": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_f64",
    "arguments": [
      "float64x1_t low",
      "float64x1_t high"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.1D"
      },
      "low": {
        "register": "Vn.1D"
      }
    },
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    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_p16",
    "arguments": [
      "poly16x4_t low",
      "poly16x4_t high"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.4H"
      },
      "low": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
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        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_p64",
    "arguments": [
      "poly64x1_t low",
      "poly64x1_t high"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.1D"
      },
      "low": {
        "register": "Vn.1D"
      }
    },
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      "A64"
    ],
    "instructions": [
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        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_p8",
    "arguments": [
      "poly8x8_t low",
      "poly8x8_t high"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.8B"
      },
      "low": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
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        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_s16",
    "arguments": [
      "int16x4_t low",
      "int16x4_t high"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.4H"
      },
      "low": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_s32",
    "arguments": [
      "int32x2_t low",
      "int32x2_t high"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.2S"
      },
      "low": {
        "register": "Vn.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_s64",
    "arguments": [
      "int64x1_t low",
      "int64x1_t high"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.1D"
      },
      "low": {
        "register": "Vn.1D"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_s8",
    "arguments": [
      "int8x8_t low",
      "int8x8_t high"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.8B"
      },
      "low": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_u16",
    "arguments": [
      "uint16x4_t low",
      "uint16x4_t high"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.4H"
      },
      "low": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_u32",
    "arguments": [
      "uint32x2_t low",
      "uint32x2_t high"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.2S"
      },
      "low": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_u64",
    "arguments": [
      "uint64x1_t low",
      "uint64x1_t high"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.1D"
      },
      "low": {
        "register": "Vn.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcombine_u8",
    "arguments": [
      "uint8x8_t low",
      "uint8x8_t high"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "high": {
        "register": "Vm.8B"
      },
      "low": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP",
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_f32",
    "arguments": [
      "float32x2_t a",
      "const int lane1",
      "float32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_f64",
    "arguments": [
      "float64x1_t a",
      "const int lane1",
      "float64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_p16",
    "arguments": [
      "poly16x4_t a",
      "const int lane1",
      "poly16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_p64",
    "arguments": [
      "poly64x1_t a",
      "const int lane1",
      "poly64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_p8",
    "arguments": [
      "poly8x8_t a",
      "const int lane1",
      "poly8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_s16",
    "arguments": [
      "int16x4_t a",
      "const int lane1",
      "int16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_s32",
    "arguments": [
      "int32x2_t a",
      "const int lane1",
      "int32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_s64",
    "arguments": [
      "int64x1_t a",
      "const int lane1",
      "int64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_s8",
    "arguments": [
      "int8x8_t a",
      "const int lane1",
      "int8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "const int lane1",
      "uint16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "const int lane1",
      "uint32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_u64",
    "arguments": [
      "uint64x1_t a",
      "const int lane1",
      "uint64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.1D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_lane_u8",
    "arguments": [
      "uint8x8_t a",
      "const int lane1",
      "uint8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "const int lane1",
      "float32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "const int lane1",
      "float64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_p16",
    "arguments": [
      "poly16x4_t a",
      "const int lane1",
      "poly16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_p64",
    "arguments": [
      "poly64x1_t a",
      "const int lane1",
      "poly64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_p8",
    "arguments": [
      "poly8x8_t a",
      "const int lane1",
      "poly8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "const int lane1",
      "int16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "const int lane1",
      "int32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_s64",
    "arguments": [
      "int64x1_t a",
      "const int lane1",
      "int64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_s8",
    "arguments": [
      "int8x8_t a",
      "const int lane1",
      "int8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "const int lane1",
      "uint16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "const int lane1",
      "uint32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_u64",
    "arguments": [
      "uint64x1_t a",
      "const int lane1",
      "uint64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "UNUSED"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 0
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopy_laneq_u8",
    "arguments": [
      "uint8x8_t a",
      "const int lane1",
      "uint8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "const int lane1",
      "float32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "const int lane1",
      "float64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
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      "b": {
        "register": "Vn.1D"
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        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_p16",
    "arguments": [
      "poly16x8_t a",
      "const int lane1",
      "poly16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
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      "a": {
        "register": "Vd.8H"
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      "b": {
        "register": "Vn.4H"
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        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_p64",
    "arguments": [
      "poly64x2_t a",
      "const int lane1",
      "poly64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
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      "b": {
        "register": "Vn.1D"
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        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_p8",
    "arguments": [
      "poly8x16_t a",
      "const int lane1",
      "poly8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
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      "b": {
        "register": "Vn.8B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "const int lane1",
      "int16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.4H"
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      "lane1": {
        "minimum": 0,
        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "const int lane1",
      "int32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
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      "b": {
        "register": "Vn.2S"
      },
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        "minimum": 0,
        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_s64",
    "arguments": [
      "int64x2_t a",
      "const int lane1",
      "int64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.1D"
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      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_s8",
    "arguments": [
      "int8x16_t a",
      "const int lane1",
      "int8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.8B"
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      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "const int lane1",
      "uint16x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.4H"
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      "lane1": {
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        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
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    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "const int lane1",
      "uint32x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
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      "b": {
        "register": "Vn.2S"
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        "maximum": 3
      },
      "lane2": {
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        "maximum": 1
      }
    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_u64",
    "arguments": [
      "uint64x2_t a",
      "const int lane1",
      "uint64x1_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.1D"
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      "lane1": {
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        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 0
      }
    },
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    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_lane_u8",
    "arguments": [
      "uint8x16_t a",
      "const int lane1",
      "uint8x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.8B"
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        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "const int lane1",
      "float32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
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      "b": {
        "register": "Vn.4S"
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        "maximum": 3
      },
      "lane2": {
        "minimum": 0,
        "maximum": 3
      }
    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "const int lane1",
      "float64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
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      "b": {
        "register": "Vn.2D"
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        "maximum": 1
      },
      "lane2": {
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        "maximum": 1
      }
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_p16",
    "arguments": [
      "poly16x8_t a",
      "const int lane1",
      "poly16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
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      "b": {
        "register": "Vn.8H"
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        "maximum": 7
      },
      "lane2": {
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        "maximum": 7
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    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_p64",
    "arguments": [
      "poly64x2_t a",
      "const int lane1",
      "poly64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
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      "b": {
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        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
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      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_p8",
    "arguments": [
      "poly8x16_t a",
      "const int lane1",
      "poly8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
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        "register": "Vd.16B"
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      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
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        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "const int lane1",
      "int16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
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        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "const int lane1",
      "int32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
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      "lane1": {
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        "maximum": 3
      },
      "lane2": {
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        "maximum": 3
      }
    },
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    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_s64",
    "arguments": [
      "int64x2_t a",
      "const int lane1",
      "int64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
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      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
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        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_s8",
    "arguments": [
      "int8x16_t a",
      "const int lane1",
      "int8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "const int lane1",
      "uint16x8_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane1": {
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        "maximum": 7
      },
      "lane2": {
        "minimum": 0,
        "maximum": 7
      }
    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "const int lane1",
      "uint32x4_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
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        "maximum": 3
      },
      "lane2": {
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        "maximum": 3
      }
    },
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_u64",
    "arguments": [
      "uint64x2_t a",
      "const int lane1",
      "uint64x2_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane1": {
        "minimum": 0,
        "maximum": 1
      },
      "lane2": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcopyq_laneq_u8",
    "arguments": [
      "uint8x16_t a",
      "const int lane1",
      "uint8x16_t b",
      "const int lane2"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "lane1": {
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        "maximum": 15
      },
      "lane2": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
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    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_f16",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_f32",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_f64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_p16",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_p64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_p8",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_s16",
    "arguments": [
      "uint64_t a"
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    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_s32",
    "arguments": [
      "uint64_t a"
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    "return_type": {
      "value": "int32x2_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_s64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_s8",
    "arguments": [
      "uint64_t a"
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    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_u16",
    "arguments": [
      "uint64_t a"
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    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_u32",
    "arguments": [
      "uint64_t a"
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    "return_type": {
      "value": "uint32x2_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_u64",
    "arguments": [
      "uint64_t a"
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      "value": "uint64x1_t"
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    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcreate_u8",
    "arguments": [
      "uint64_t a"
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      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Xn"
      }
    },
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "INS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float32x4_t a"
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      "value": "float16x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
    },
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      "v7",
      "A32",
      "A64"
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        "FCVTN"
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  {
    "SIMD_ISA": "Neon",
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      "int16x4_t a"
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      "value": "float16x4_t"
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      "a": {
        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f16_u16",
    "arguments": [
      "uint16x4_t a"
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    "return_type": {
      "value": "float16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
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      [
        "UCVTF"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_f32_f16",
    "arguments": [
      "float16x4_t a"
    ],
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      "value": "float32x4_t"
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      "a": {
        "register": "Vn.4H"
      }
    },
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      "A32",
      "A64"
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      [
        "FCVTL"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "float64x2_t a"
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      "value": "float32x2_t"
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      "a": {
        "register": "Vn.2D"
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    },
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      "A64"
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        "FCVTN"
      ]
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  },
  {
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      "int32x2_t a"
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      "value": "float32x2_t"
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        "register": "Vn.2S"
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      "A32",
      "A64"
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        "SCVTF"
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  {
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      "uint32x2_t a"
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      "value": "float32x2_t"
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        "register": "Vn.2S"
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      "A32",
      "A64"
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        "UCVTF"
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    "SIMD_ISA": "Neon",
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      "float32x2_t a"
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      "value": "float64x2_t"
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        "register": "Vn.2S"
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        "FCVTL"
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  {
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      "int64x1_t a"
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      "value": "float64x1_t"
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        "register": "Dn"
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        "SCVTF"
      ]
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  },
  {
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      "uint64x1_t a"
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      "value": "float64x1_t"
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        "register": "Dn"
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        "UCVTF"
      ]
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    "SIMD_ISA": "Neon",
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      "float16x4_t r",
      "float32x4_t a"
    ],
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      "value": "float16x8_t"
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        "register": "Vn.4S"
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      "r": {
        "register": "Vd.4H"
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        "FCVTN2"
      ]
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      "float16x8_t a"
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        "register": "Vn.8H"
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        "FCVTL2"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x2_t r",
      "float64x2_t a"
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      "value": "float32x4_t"
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        "register": "Vn.2D"
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        "register": "Vd.2S"
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        "FCVTN2"
      ]
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  {
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      "value": "float64x2_t"
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        "register": "Vn.4S"
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        "FCVTL2"
      ]
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    "SIMD_ISA": "Neon",
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    ],
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        "register": "Vn.4H"
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        "minimum": 1,
        "maximum": 16
      }
    },
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      "A64"
    ],
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        "SCVTF"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "float16x4_t"
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        "register": "Vn.4H"
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        "minimum": 1,
        "maximum": 16
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      "A64"
    ],
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        "UCVTF"
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    ]
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  {
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        "register": "Vn.2S"
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        "minimum": 1,
        "maximum": 32
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      "A32",
      "A64"
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      "value": "float32x2_t"
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        "register": "Vn.2S"
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        "minimum": 1,
        "maximum": 32
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      "A64"
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        "UCVTF"
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    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "float64x1_t"
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        "register": "Dn"
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        "minimum": 1,
        "maximum": 64
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        "SCVTF"
      ]
    ]
  },
  {
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        "register": "Dn"
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        "minimum": 1,
        "maximum": 64
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    },
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    ],
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        "UCVTF"
      ]
    ]
  },
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    ],
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        "register": "Vn.4H"
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        "minimum": 1,
        "maximum": 16
      }
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      "A64"
    ],
    "instructions": [
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        "FCVTZS"
      ]
    ]
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  {
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        "register": "Vn.2S"
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        "minimum": 1,
        "maximum": 32
      }
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      "A32",
      "A64"
    ],
    "instructions": [
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        "FCVTZS"
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    ]
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    "SIMD_ISA": "Neon",
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        "register": "Dn"
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        "minimum": 1,
        "maximum": 64
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        "FCVTZS"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    ],
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    },
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        "register": "Vn.4H"
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        "minimum": 1,
        "maximum": 16
      }
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      "A64"
    ],
    "instructions": [
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        "FCVTZU"
      ]
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  {
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    ],
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      "value": "uint32x2_t"
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        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
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      "A32",
      "A64"
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    "instructions": [
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        "FCVTZU"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_s16_f16",
    "arguments": [
      "float16x4_t a"
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    },
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        "register": "Vn.4H"
      }
    },
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      "A64"
    ],
    "instructions": [
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        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_s32_f32",
    "arguments": [
      "float32x2_t a"
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      "value": "int32x2_t"
    },
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        "register": "Vn.2S"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
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        "FCVTZS"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_s64_f64",
    "arguments": [
      "float64x1_t a"
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      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
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        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_u16_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_u32_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvt_u64_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvta_s16_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTAS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvta_s32_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTAS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvta_s64_f64",
    "arguments": [
      "float64x1_t a"
    ],
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      "value": "int64x1_t"
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        "FCVTAS"
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    "SIMD_ISA": "Neon",
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      "value": "uint16x4_t"
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        "FCVTAU"
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        "FCVTAS"
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  {
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        "FCVTAU"
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        "FCVTAS"
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        "FCVTAS"
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        "FCVTAS"
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        "register": "Hn"
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        "FCVTAU"
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        "register": "Hn"
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        "register": "Hn"
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        "register": "Hn"
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        "register": "Hn"
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        "register": "Hn"
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        "register": "Hn"
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        "register": "Hn"
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        "maximum": 16
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        "register": "Hn"
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        "maximum": 16
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        "register": "Hn"
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      "A64"
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        "register": "Hn"
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        "maximum": 16
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        "register": "Hn"
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        "register": "Hn"
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        "maximum": 16
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        "register": "Hn"
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        "maximum": 16
      }
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  {
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      "value": "uint16_t"
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        "register": "Hn"
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        "maximum": 16
      }
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    ],
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        "FCVTZU"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "uint32_t"
    },
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        "register": "Hn"
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        "maximum": 16
      }
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    ],
    "instructions": [
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        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtq_s16_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtq_s32_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtq_s64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtq_u16_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtq_u32_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtq_u64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_f32_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_f32_u32",
    "arguments": [
      "uint32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_n_f32_s32",
    "arguments": [
      "int32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_n_f32_u32",
    "arguments": [
      "uint32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UCVTF"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_n_s32_f32",
    "arguments": [
      "float32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_n_u32_f32",
    "arguments": [
      "float32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_s32_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvts_u32_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTZU"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtx_f32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTXN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtx_high_f32_f64",
    "arguments": [
      "float32x2_t r",
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTXN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vcvtxd_f32_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FCVTXN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdiv_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdiv_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdiv_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdivh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdivq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdivq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdivq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FDIV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_lane_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "int8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_lane_u32",
    "arguments": [
      "uint32x2_t r",
      "uint8x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_laneq_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "int8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_laneq_u32",
    "arguments": [
      "uint32x2_t r",
      "uint8x8_t a",
      "uint8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdot_u32",
    "arguments": [
      "uint32x2_t r",
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_lane_s32",
    "arguments": [
      "int32x4_t r",
      "int8x16_t a",
      "int8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_lane_u32",
    "arguments": [
      "uint32x4_t r",
      "uint8x16_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_laneq_s32",
    "arguments": [
      "int32x4_t r",
      "int8x16_t a",
      "int8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_laneq_u32",
    "arguments": [
      "uint32x4_t r",
      "uint8x16_t a",
      "uint8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_s32",
    "arguments": [
      "int32x4_t r",
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdotq_u32",
    "arguments": [
      "uint32x4_t r",
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdup_lane_f16",
    "arguments": [
      "float16x4_t vec",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "vec": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vdup_lane_f32",
    "arguments": [
      "float32x2_t vec",
      "const int lane"
    ],
    "return_type": {
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        "EOR"
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  {
    "SIMD_ISA": "Neon",
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      [
        "EOR"
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  {
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      [
        "EOR"
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  {
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      [
        "EOR"
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      [
        "EOR"
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        "EOR"
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        "EOR"
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      [
        "EOR"
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      [
        "EOR"
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        "EOR"
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        "EOR"
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    "SIMD_ISA": "Neon",
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float32x2_t a",
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        "maximum": 1
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "float64x1_t a",
      "float64x1_t b",
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        "maximum": 0
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    },
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      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b",
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        "maximum": 3
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_p64",
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      "poly64x1_t b",
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        "maximum": 0
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_p8",
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      "poly8x8_t a",
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        "maximum": 7
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_s16",
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      "int16x4_t a",
      "int16x4_t b",
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        "maximum": 3
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
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        "maximum": 1
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b",
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        "maximum": 0
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    },
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      "A32",
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
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    },
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      "A32",
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
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        "maximum": 3
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      "A32",
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
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        "maximum": 1
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
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        "maximum": 0
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vext_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
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        "maximum": 7
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      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_f16",
    "arguments": [
      "float16x8_t a",
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        "register": "Vn.16B"
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        "maximum": 7
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_f32",
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      "float32x4_t a",
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        "maximum": 3
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_f64",
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      "float64x2_t a",
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    },
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_p16",
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_p64",
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        "maximum": 1
      }
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      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_p8",
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        "maximum": 15
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_s16",
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      "int16x8_t a",
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        "register": "Vm.16B"
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        "maximum": 7
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_s32",
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      "int32x4_t a",
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        "register": "Vm.16B"
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        "maximum": 3
      }
    },
    "Architectures": [
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      "A32",
      "A64"
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    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_s64",
    "arguments": [
      "int64x2_t a",
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      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 1
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vextq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "EXT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x4_t c"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Da"
      },
      "b": {
        "register": "Dn"
      },
      "c": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_lane_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_lane_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_laneq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_n_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H "
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32_t n"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfma_n_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64_t n"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Da"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmad_lane_f64",
    "arguments": [
      "float64_t a",
      "float64_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmad_laneq_f64",
    "arguments": [
      "float64_t a",
      "float64_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmah_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16_t c"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Ha"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmah_lane_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmah_laneq_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x8_t c"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "c": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_lane_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_laneq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_n_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H "
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32_t n"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmaq_n_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64_t n"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "register": "Vm.D[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmas_lane_f32",
    "arguments": [
      "float32_t a",
      "float32_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmas_laneq_f32",
    "arguments": [
      "float32_t a",
      "float32_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_lane_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_lane_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_laneq_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_laneq_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlal_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_lane_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_lane_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_laneq_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_laneq_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlalq_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_lane_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_lane_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_laneq_high_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_laneq_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlsl_low_f16",
    "arguments": [
      "float32x2_t r",
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_lane_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_lane_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x4_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_laneq_high_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_laneq_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmlslq_low_f16",
    "arguments": [
      "float32x4_t r",
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x4_t c"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Da"
      },
      "b": {
        "register": "Dn"
      },
      "c": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_lane_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_lane_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_laneq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_n_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H "
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32_t n"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfms_n_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64_t n"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Da"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsd_lane_f64",
    "arguments": [
      "float64_t a",
      "float64_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsd_laneq_f64",
    "arguments": [
      "float64_t a",
      "float64_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16_t c"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Ha"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsh_lane_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsh_laneq_f16",
    "arguments": [
      "float16_t a",
      "float16_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x8_t c"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "c": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_lane_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_laneq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_n_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H "
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32_t n"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmsq_n_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64_t n"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "register": "Vm.D[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmss_lane_f32",
    "arguments": [
      "float32_t a",
      "float32_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vfmss_laneq_f32",
    "arguments": [
      "float32_t a",
      "float32_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vget_high_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
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      "A64"
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        "DUP"
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    "SIMD_ISA": "Neon",
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      "int16x8_t a"
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      "value": "int16x4_t"
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        "register": "Vn.8H"
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      "A64"
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        "DUP"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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        "register": "Vn.2D"
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        "DUP"
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        "register": "Vn.16B"
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      "A64"
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        "DUP"
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        "register": "Vn.8H"
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        "DUP"
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        "register": "Vn.4S"
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      "A64"
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        "DUP"
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        "register": "Vn.2D"
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      "A64"
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        "DUP"
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        "register": "Vn.16B"
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      "A64"
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      [
        "DUP"
      ]
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      "value": "float16_t"
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        "register": "Vn.4H"
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      "A32",
      "A64"
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      [
        "DUP"
      ]
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      "value": "float32_t"
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        "register": "Vn.2S"
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      "A64"
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        "DUP"
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        "register": "Vn.1D"
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        "DUP"
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      "A64"
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        "UMOV"
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      "A64"
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      "value": "int64_t"
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        "register": "Vn.1D"
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      "A64"
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      "value": "uint64_t"
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        "register": "Vn.1D"
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        "register": "Vn.8B"
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      "A64"
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        "register": "Vn.2D"
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      "A64"
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        "register": "Vn.16B"
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      "A64"
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        "register": "Vn.8H"
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      "A64"
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        "register": "Vn.2D"
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      "A64"
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      "A64"
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        "register": "Vn.8H"
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      "A32",
      "A64"
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      ]
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  {
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      "uint32x4_t a"
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      "value": "uint32x2_t"
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        "register": "Vn.4S"
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      "A32",
      "A64"
    ],
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        "DUP"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vget_low_u64",
    "arguments": [
      "uint64x2_t a"
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      "value": "uint64x1_t"
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        "register": "Vn.2D"
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      "A32",
      "A64"
    ],
    "instructions": [
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        "DUP"
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    ]
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        "register": "Vn.16B"
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      "A32",
      "A64"
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        "DUP"
      ]
    ]
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    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_f16",
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      "const int lane"
    ],
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      "value": "float16_t"
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        "minimum": 0,
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        "register": "Vn.8H"
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      "A32",
      "A64"
    ],
    "instructions": [
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        "DUP"
      ]
    ]
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    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_f32",
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      "const int lane"
    ],
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      "value": "float32_t"
    },
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        "maximum": 3
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        "register": "Vn.4S"
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      "A32",
      "A64"
    ],
    "instructions": [
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        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_f64",
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      "const int lane"
    ],
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      "value": "float64_t"
    },
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        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2D"
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    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_p16",
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      "poly16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16_t"
    },
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        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vn.8H"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_p64",
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      "poly64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64_t"
    },
    "Arguments_Preparation": {
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        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_p8",
    "arguments": [
      "poly8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_s16",
    "arguments": [
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_s32",
    "arguments": [
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_s64",
    "arguments": [
      "int64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_s8",
    "arguments": [
      "int8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_u16",
    "arguments": [
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_u32",
    "arguments": [
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_u64",
    "arguments": [
      "uint64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vgetq_lane_u8",
    "arguments": [
      "uint8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhadd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsub_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vhsubq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UHSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f16_x2",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f16_x3",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f16_x4",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f32_x2",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f32_x3",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f32_x4",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f64_x2",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f64_x3",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_f64_x4",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x1_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p16_x2",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p16_x3",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p16_x4",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p64_x2",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p64_x3",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p64_x4",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p8_x2",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p8_x3",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_p8_x4",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s16_x2",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s16_x3",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s16_x4",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s32_x2",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s32_x3",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s32_x4",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s64_x2",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s64_x3",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s64_x4",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s8_x2",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s8_x3",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_s8_x4",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u16_x2",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u16_x3",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u16_x4",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u32_x2",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u32_x3",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u32_x4",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u64_x2",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u64_x3",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u64_x4",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u8_x2",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u8_x3",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1_u8_x4",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f16_x2",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f16_x3",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f16_x4",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f32_x2",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f32_x3",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f32_x4",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f64_x2",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f64_x3",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_f64_x4",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x16_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x16_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x8_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x16_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p16_x2",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p16_x3",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p16_x4",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p64_x2",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p64_x3",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p64_x4",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p8_x2",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p8_x3",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_p8_x4",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s16_x2",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s16_x3",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s16_x4",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s32_x2",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s32_x3",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s32_x4",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s64_x2",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s64_x3",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s64_x4",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s8_x2",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s8_x3",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_s8_x4",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u16_x2",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u16_x3",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u16_x4",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u32_x2",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u32_x3",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u32_x4",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u64_x2",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u64_x3",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u64_x4",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u8_x2",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u8_x3",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld1q_u8_x4",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
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      "value": "int64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
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        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x2_t"
    },
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      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vld2_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x2_t"
    },
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      "ptr": {
        "register": "Xn"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x4x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.4H"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x2x2_t src",
      "const int lane"
    ],
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      "value": "float32x2x2_t"
    },
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      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.2S"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x1x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1x2_t"
    },
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      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.1D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x4x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4x2_t"
    },
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      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x1x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x8x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x4x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x2x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x1x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x8x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x4x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x2x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x1x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x8x2_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld2q_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
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        "LD2R"
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    "SIMD_ISA": "Neon",
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      "value": "float64x2x2_t"
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        "register": "Xn"
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        "LD2R"
      ]
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      "value": "poly16x8x2_t"
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        "register": "Xn"
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        "LD2R"
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      "value": "poly64x2x2_t"
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        "register": "Xn"
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        "LD2R"
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        "LD2R"
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        "register": "Xn"
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        "LD2R"
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        "register": "Xn"
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        "register": "Xn"
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        "LD2R"
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        "LD2R"
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        "register": "Xn"
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        "LD2R"
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        "register": "Xn"
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        "LD2R"
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        "register": "Xn"
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        "LD2R"
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        "register": "Xn"
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        "LD2R"
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        "LD2"
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        "LD2"
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        "LD2"
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        "LD2"
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        "register": "Vt2.2D"
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        "LD2"
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        "LD2"
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        "register": "Vt2.16B"
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        "LD2"
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        "register": "Vt2.8H"
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        "register": "Xn"
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        "register": "Vt2.2D"
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        "LD2"
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        "register": "Xn"
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        "register": "Vt2.16B"
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        "LD2"
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        "register": "Xn"
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        "register": "Vt2.8H"
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      "A32",
      "A64"
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        "LD2"
      ]
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    "SIMD_ISA": "Neon",
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      "value": "uint32x4x2_t"
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        "minimum": 0,
        "maximum": 3
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        "register": "Xn"
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        "register": "Vt2.4S"
      }
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      "A64"
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        "LD2"
      ]
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    "SIMD_ISA": "Neon",
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      "uint64x2x2_t src",
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      "value": "uint64x2x2_t"
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        "register": "Xn"
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        "register": "Vt2.2D"
      }
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        "LD2"
      ]
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  {
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    "arguments": [
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      "uint8x16x2_t src",
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    ],
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      "value": "uint8x16x2_t"
    },
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        "minimum": 0,
        "maximum": 15
      },
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        "register": "Xn"
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      "src": {
        "register": "Vt2.16B"
      }
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    ],
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        "LD2"
      ]
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    ],
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    },
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      "ptr": {
        "register": "Xn"
      }
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      "A32",
      "A64"
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        "LD2"
      ]
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      "ptr": {
        "register": "Xn"
      }
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    ],
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        "LD2"
      ]
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  {
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        "register": "Xn"
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      "A64"
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        "LD2"
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      "value": "int16x8x2_t"
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        "register": "Xn"
      }
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      "A32",
      "A64"
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        "LD2"
      ]
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      "value": "int32x4x2_t"
    },
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      "ptr": {
        "register": "Xn"
      }
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      "A32",
      "A64"
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        "LD2"
      ]
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    "SIMD_ISA": "Neon",
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      "ptr": {
        "register": "Xn"
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        "LD2"
      ]
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  {
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      "ptr": {
        "register": "Xn"
      }
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      "A32",
      "A64"
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        "LD2"
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      "uint16_t const * ptr"
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      "value": "uint16x8x2_t"
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      "ptr": {
        "register": "Xn"
      }
    },
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      "A32",
      "A64"
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    "instructions": [
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        "LD2"
      ]
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    "SIMD_ISA": "Neon",
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      "value": "uint32x4x2_t"
    },
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      "ptr": {
        "register": "Xn"
      }
    },
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      "A32",
      "A64"
    ],
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        "LD2"
      ]
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    "SIMD_ISA": "Neon",
    "name": "vld2q_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x2_t"
    },
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      "ptr": {
        "register": "Xn"
      }
    },
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        "LD2"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x1x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x1x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x1x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x1x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x16x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x16x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x8x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x4x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x2x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x16x3_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16x3_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld3q_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x3_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x1x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x1x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x1x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x1x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x1x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_dup_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4R"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_f16",
    "arguments": [
      "float16_t const * ptr"
    ],
    "return_type": {
      "value": "float16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_f32",
    "arguments": [
      "float32_t const * ptr"
    ],
    "return_type": {
      "value": "float32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_f64",
    "arguments": [
      "float64_t const * ptr"
    ],
    "return_type": {
      "value": "float64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_f16",
    "arguments": [
      "float16_t const * ptr",
      "float16x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_f32",
    "arguments": [
      "float32_t const * ptr",
      "float32x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_f64",
    "arguments": [
      "float64_t const * ptr",
      "float64x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_p16",
    "arguments": [
      "poly16_t const * ptr",
      "poly16x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_p64",
    "arguments": [
      "poly64_t const * ptr",
      "poly64x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_p8",
    "arguments": [
      "poly8_t const * ptr",
      "poly8x16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_s16",
    "arguments": [
      "int16_t const * ptr",
      "int16x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_s32",
    "arguments": [
      "int32_t const * ptr",
      "int32x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_s64",
    "arguments": [
      "int64_t const * ptr",
      "int64x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_s8",
    "arguments": [
      "int8_t const * ptr",
      "int8x16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_u16",
    "arguments": [
      "uint16_t const * ptr",
      "uint16x8x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_u32",
    "arguments": [
      "uint32_t const * ptr",
      "uint32x4x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_u64",
    "arguments": [
      "uint64_t const * ptr",
      "uint64x2x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_lane_u8",
    "arguments": [
      "uint8_t const * ptr",
      "uint8x16x4_t src",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16x4_t"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "src": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_p16",
    "arguments": [
      "poly16_t const * ptr"
    ],
    "return_type": {
      "value": "poly16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_p64",
    "arguments": [
      "poly64_t const * ptr"
    ],
    "return_type": {
      "value": "poly64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_p8",
    "arguments": [
      "poly8_t const * ptr"
    ],
    "return_type": {
      "value": "poly8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_s16",
    "arguments": [
      "int16_t const * ptr"
    ],
    "return_type": {
      "value": "int16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_s32",
    "arguments": [
      "int32_t const * ptr"
    ],
    "return_type": {
      "value": "int32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_s64",
    "arguments": [
      "int64_t const * ptr"
    ],
    "return_type": {
      "value": "int64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_s8",
    "arguments": [
      "int8_t const * ptr"
    ],
    "return_type": {
      "value": "int8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_u16",
    "arguments": [
      "uint16_t const * ptr"
    ],
    "return_type": {
      "value": "uint16x8x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_u32",
    "arguments": [
      "uint32_t const * ptr"
    ],
    "return_type": {
      "value": "uint32x4x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_u64",
    "arguments": [
      "uint64_t const * ptr"
    ],
    "return_type": {
      "value": "uint64x2x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vld4q_u8",
    "arguments": [
      "uint8_t const * ptr"
    ],
    "return_type": {
      "value": "uint8x16x4_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LD4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vldrq_p128",
    "arguments": [
      "poly128_t const * ptr"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "LDR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmax_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnm_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnm_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnm_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNM"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmv_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmv_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmvq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmvq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxnmvq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmaxq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAX"
      ]
    ]
  },
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      "A64"
    ],
    "instructions": [
      [
        "FMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
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      "value": "float64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int16x8_t a",
      "int16x8_t b"
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      "value": "int16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_s32",
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      "int32x4_t a",
      "int32x4_t b"
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      "value": "int32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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    },
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x16_t a",
      "int8x16_t b"
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      "value": "int8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
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    "return_type": {
      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "UMIN"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_u32",
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      "uint32x4_t a",
      "uint32x4_t b"
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      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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      [
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "UMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_f16",
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      "float16x4_t a"
    ],
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      "value": "float16_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
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      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_f32",
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      "float32x2_t a"
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    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
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      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_s16",
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      "int16x4_t a"
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      "value": "int16_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_s32",
    "arguments": [
      "int32x2_t a"
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      "value": "int32_t"
    },
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      "a": {
        "register": "Vn.2S"
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      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_s8",
    "arguments": [
      "int8x8_t a"
    ],
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      "value": "int8_t"
    },
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      "a": {
        "register": "Vn.8B"
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      "A64"
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    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_u16",
    "arguments": [
      "uint16x4_t a"
    ],
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      "value": "uint16_t"
    },
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      "a": {
        "register": "Vn.4H"
      }
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      "A64"
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    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
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      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
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    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminv_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
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      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
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      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
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      "a": {
        "register": "Vn.2D"
      }
    },
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      "A64"
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      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int16x8_t a"
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      "value": "int16_t"
    },
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      "a": {
        "register": "Vn.8H"
      }
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      "A64"
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      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x4_t a"
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      "value": "int32_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_s8",
    "arguments": [
      "int8x16_t a"
    ],
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      "value": "int8_t"
    },
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      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
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      [
        "SMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
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      "value": "uint32_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vminvq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {}
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
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      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {}
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmla_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_lane_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_lane_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_laneq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_laneq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_n_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_n_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_lane_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_lane_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_laneq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_laneq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_n_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_n_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlal_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {}
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {}
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlaq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b",
      "float64x1_t c"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {}
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {}
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b",
      "float32_t c"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmls_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_lane_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_lane_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_laneq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_laneq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_n_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_n_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_lane_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_lane_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_laneq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_laneq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_n_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_n_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b",
      "int8x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b",
      "uint16x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b",
      "uint32x2_t c"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsl_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b",
      "uint8x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8B"
      },
      "c": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b",
      "float64x2_t c"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {}
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {},
      "b": {},
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {}
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b",
      "float32_t c"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "N/A"
      },
      "b": {
        "register": "N/A"
      },
      "c": {
        "register": "N/A"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RESULT[I]"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "int8x16_t c"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "uint16x8_t c"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmlsq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "uint8x16_t c"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "c": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MLS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmmlaq_s32",
    "arguments": [
      "int32x4_t r",
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmmlaq_u32",
    "arguments": [
      "uint32x4_t r",
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_f16",
    "arguments": [
      "float16_t value"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_f32",
    "arguments": [
      "float32_t value"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_f64",
    "arguments": [
      "float64_t value"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_p16",
    "arguments": [
      "poly16_t value"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_p8",
    "arguments": [
      "poly8_t value"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_s16",
    "arguments": [
      "int16_t value"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_s32",
    "arguments": [
      "int32_t value"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_s64",
    "arguments": [
      "int64_t value"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_s8",
    "arguments": [
      "int8_t value"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_u16",
    "arguments": [
      "uint16_t value"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_u32",
    "arguments": [
      "uint32_t value"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_u64",
    "arguments": [
      "uint64_t value"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmov_n_u8",
    "arguments": [
      "uint8_t value"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_high_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USHLL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovl_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USHLL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovn_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "XTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_f16",
    "arguments": [
      "float16_t value"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_f32",
    "arguments": [
      "float32_t value"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_f64",
    "arguments": [
      "float64_t value"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_p16",
    "arguments": [
      "poly16_t value"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_p8",
    "arguments": [
      "poly8_t value"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_s16",
    "arguments": [
      "int16_t value"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_s32",
    "arguments": [
      "int32_t value"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_s64",
    "arguments": [
      "int64_t value"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_s8",
    "arguments": [
      "int8_t value"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_u16",
    "arguments": [
      "uint16_t value"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_u32",
    "arguments": [
      "uint32_t value"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_u64",
    "arguments": [
      "uint64_t value"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmovq_n_u8",
    "arguments": [
      "uint8_t value"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "value": {
        "register": "rn"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "DUP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_f16",
    "arguments": [
      "float16x4_t a",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_f32",
    "arguments": [
      "float32x2_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_f64",
    "arguments": [
      "float64x1_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Vm.D[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmul_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmuld_lane_f64",
    "arguments": [
      "float64_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmuld_laneq_f64",
    "arguments": [
      "float64_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulh_lane_f16",
    "arguments": [
      "float16_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulh_laneq_f16",
    "arguments": [
      "float16_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "PMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_high_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_lane_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_laneq_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_laneq_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_p64",
    "arguments": [
      "poly64_t a",
      "poly64_t b"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.1D"
      },
      "b": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmull_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_f16",
    "arguments": [
      "float16x8_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_lane_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_laneq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_f16",
    "arguments": [
      "float16x8_t a",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_f32",
    "arguments": [
      "float32x4_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_f64",
    "arguments": [
      "float64x2_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.D[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "PMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmuls_lane_f32",
    "arguments": [
      "float32_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmuls_laneq_f32",
    "arguments": [
      "float32_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMUL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_lane_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_lane_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_lane_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_laneq_f16",
    "arguments": [
      "float16x4_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_laneq_f32",
    "arguments": [
      "float32x2_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_laneq_f64",
    "arguments": [
      "float64x1_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulx_n_f16",
    "arguments": [
      "float16x4_t a",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxd_lane_f64",
    "arguments": [
      "float64_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxd_laneq_f64",
    "arguments": [
      "float64_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxh_lane_f16",
    "arguments": [
      "float16_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxh_laneq_f16",
    "arguments": [
      "float16_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_lane_f16",
    "arguments": [
      "float16x8_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_lane_f32",
    "arguments": [
      "float32x4_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_lane_f64",
    "arguments": [
      "float64x2_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vm.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_laneq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_laneq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_laneq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxq_n_f16",
    "arguments": [
      "float16x8_t a",
      "float16_t n"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxs_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxs_lane_f32",
    "arguments": [
      "float32_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmulxs_laneq_f32",
    "arguments": [
      "float32_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMULX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vmvn_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MVN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a"
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      "value": "uint16x4_t"
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        "register": "Vn.8B"
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      "A32",
      "A64"
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      [
        "MVN"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t a"
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        "register": "Vn.8B"
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      "A32",
      "A64"
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      [
        "MVN"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.8B"
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      "A64"
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      [
        "MVN"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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      "A32",
      "A64"
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        "MVN"
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        "register": "Vn.16B"
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      "A64"
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        "MVN"
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        "register": "Vn.16B"
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      "A64"
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        "MVN"
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        "MVN"
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        "register": "Vn.16B"
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        "MVN"
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        "register": "Vn.16B"
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        "MVN"
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        "register": "Vn.16B"
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      "A32",
      "A64"
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        "MVN"
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        "register": "Vn.4H"
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      "A64"
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        "FNEG"
      ]
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        "register": "Vn.2S"
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        "FNEG"
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        "register": "Dn"
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        "FNEG"
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        "register": "Vn.4H"
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        "NEG"
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        "ORN"
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        "ORN"
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        "ORN"
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        "register": "Vm.16B"
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        "ORN"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A64"
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    "instructions": [
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        "ORN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorr_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorr_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorr_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorr_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorr_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorr_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorr_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorr_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorrq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorrq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorrq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorrq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorrq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorrq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorrq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vorrq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ORR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadal_s16",
    "arguments": [
      "int32x2_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadal_s32",
    "arguments": [
      "int64x1_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      },
      "b": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadal_s8",
    "arguments": [
      "int16x4_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadal_u16",
    "arguments": [
      "uint32x2_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadal_u32",
    "arguments": [
      "uint64x1_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      },
      "b": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadal_u8",
    "arguments": [
      "uint16x4_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadalq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadalq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadalq_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadalq_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadalq_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadalq_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADALP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddd_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddd_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddl_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddlq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UADDLP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpadds_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FADDP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmax_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnm_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnm_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnmq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnmq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnmq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnmqd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxnms_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxqd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmaxs_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMAXP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmin_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnm_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnm_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnmq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnmq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnmq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnmqd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminnms_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINNMP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpminqd_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vpmins_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FMINP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabs_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabs_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabs_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabs_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsb_s8",
    "arguments": [
      "int8_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsh_s16",
    "arguments": [
      "int16_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabsq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqabss_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQABS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadd_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddb_s8",
    "arguments": [
      "int8_t a",
      "int8_t b"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddb_u8",
    "arguments": [
      "uint8_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddh_u16",
    "arguments": [
      "uint16_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadds_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqadds_u32",
    "arguments": [
      "uint32_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlal_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlalh_lane_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlalh_laneq_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlalh_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlals_lane_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlals_laneq_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlals_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "c": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLAL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_lane_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_lane_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_laneq_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_laneq_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_n_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_n_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsl_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlslh_lane_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlslh_laneq_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlslh_s16",
    "arguments": [
      "int32_t a",
      "int16_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsls_lane_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsls_laneq_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmlsls_s32",
    "arguments": [
      "int64_t a",
      "int32_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Sn"
      },
      "c": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMLSL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulh_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhs_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhs_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulhs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmull_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmullh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmullh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmullh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulls_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulls_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqdmulls_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQDMULL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovn_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovnd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovnd_u64",
    "arguments": [
      "uint64_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovnh_s16",
    "arguments": [
      "int16_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovnh_u16",
    "arguments": [
      "uint16_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovns_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovns_u32",
    "arguments": [
      "uint32_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQXTN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_high_s16",
    "arguments": [
      "uint8x8_t r",
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_high_s32",
    "arguments": [
      "uint16x4_t r",
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_high_s64",
    "arguments": [
      "uint32x2_t r",
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovun_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovund_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovunh_s16",
    "arguments": [
      "int16_t a"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqmovuns_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQXTUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqneg_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqneg_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqneg_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqneg_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegb_s8",
    "arguments": [
      "int8_t a"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegd_s64",
    "arguments": [
      "int64_t a"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegh_s16",
    "arguments": [
      "int16_t a"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegq_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegq_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegq_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqnegs_s32",
    "arguments": [
      "int32_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQNEG"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlah_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahs_lane_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahs_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLAH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlahs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "c": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "int16x4_t c"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "c": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlsh_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "int32x2_t c"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "c": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b",
      "int16_t c"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      },
      "c": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "int16x8_t c"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "c": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "int32x4_t c"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "c": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshs_lane_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshs_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmlshs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b",
      "int32_t c"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      },
      "c": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMLSH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_lane_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_lane_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_laneq_s16",
    "arguments": [
      "int16x4_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_laneq_s32",
    "arguments": [
      "int32x2_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulh_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhh_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhh_laneq_s16",
    "arguments": [
      "int16_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_lane_s16",
    "arguments": [
      "int16x8_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_lane_s32",
    "arguments": [
      "int32x4_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_laneq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_laneq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.H[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.S[0]"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhs_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhs_laneq_s32",
    "arguments": [
      "int32_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrdmulhs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRDMULH"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_u16",
    "arguments": [
      "uint16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_u32",
    "arguments": [
      "uint32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_u64",
    "arguments": [
      "uint64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshl_u8",
    "arguments": [
      "uint8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlb_s8",
    "arguments": [
      "int8_t a",
      "int8_t b"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlb_u8",
    "arguments": [
      "uint8_t a",
      "int8_t b"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshld_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshld_u64",
    "arguments": [
      "uint64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlh_u16",
    "arguments": [
      "uint16_t a",
      "int16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_u16",
    "arguments": [
      "uint16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_u32",
    "arguments": [
      "uint32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_u64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshlq_u8",
    "arguments": [
      "uint8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshls_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshls_u32",
    "arguments": [
      "uint32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_high_n_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_s16",
    "arguments": [
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
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      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
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      "a": {
        "register": "Vn.4S"
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        "minimum": 1,
        "maximum": 16
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
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        "register": "Vn.2D"
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      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_u16",
    "arguments": [
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
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        "register": "Vn.8H"
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      "n": {
        "minimum": 1,
        "maximum": 8
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    },
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      "v7",
      "A32",
      "A64"
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    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_u32",
    "arguments": [
      "uint32x4_t a",
      "const int n"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4S"
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        "maximum": 16
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrn_n_u64",
    "arguments": [
      "uint64x2_t a",
      "const int n"
    ],
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2D"
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        "maximum": 32
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrnd_n_s64",
    "arguments": [
      "int64_t a",
      "const int n"
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      "value": "int32_t"
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        "register": "Dn"
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        "minimum": 1,
        "maximum": 32
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    },
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      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64_t a",
      "const int n"
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      "value": "uint32_t"
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        "register": "Dn"
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      "n": {
        "minimum": 1,
        "maximum": 32
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      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrnh_n_s16",
    "arguments": [
      "int16_t a",
      "const int n"
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      "value": "int8_t"
    },
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        "register": "Hn"
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        "maximum": 8
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      "A64"
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    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16_t a",
      "const int n"
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      "value": "uint8_t"
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        "register": "Hn"
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        "maximum": 8
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      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32_t a",
      "const int n"
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      "value": "int16_t"
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      "a": {
        "register": "Sn"
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        "minimum": 1,
        "maximum": 16
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      "A64"
    ],
    "instructions": [
      [
        "SQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrns_n_u32",
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      "uint32_t a",
      "const int n"
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      "value": "uint16_t"
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        "register": "Sn"
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        "minimum": 1,
        "maximum": 16
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      "A64"
    ],
    "instructions": [
      [
        "UQRSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t r",
      "int16x8_t a",
      "const int n"
    ],
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      "value": "uint8x16_t"
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        "register": "Vn.8H"
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      "n": {
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        "maximum": 8
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        "register": "Vd.8B"
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      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t r",
      "int32x4_t a",
      "const int n"
    ],
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        "register": "Vn.4S"
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        "maximum": 16
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        "register": "Vd.4H"
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      "A64"
    ],
    "instructions": [
      [
        "SQRSHRUN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t r",
      "int64x2_t a",
      "const int n"
    ],
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      "value": "uint32x4_t"
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        "register": "Vn.2D"
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        "maximum": 32
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        "register": "Vd.2S"
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    ],
    "instructions": [
      [
        "SQRSHRUN2"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrun_n_s16",
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      "int16x8_t a",
      "const int n"
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      "value": "uint8x8_t"
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        "register": "Vn.8H"
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        "maximum": 8
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrun_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
    ],
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      "value": "uint16x4_t"
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        "register": "Vn.4S"
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        "maximum": 16
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      "A32",
      "A64"
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        "SQRSHRUN"
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  {
    "SIMD_ISA": "Neon",
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      "int64x2_t a",
      "const int n"
    ],
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      "value": "uint32x2_t"
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        "register": "Vn.2D"
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        "minimum": 1,
        "maximum": 32
      }
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      "A32",
      "A64"
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    "instructions": [
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        "SQRSHRUN"
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrund_n_s64",
    "arguments": [
      "int64_t a",
      "const int n"
    ],
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      "value": "uint32_t"
    },
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      "a": {
        "register": "Dn"
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        "maximum": 32
      }
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    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshrunh_n_s16",
    "arguments": [
      "int16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8_t"
    },
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        "register": "Hn"
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        "maximum": 8
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    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqrshruns_n_s32",
    "arguments": [
      "int32_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16_t"
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      "a": {
        "register": "Sn"
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        "minimum": 1,
        "maximum": 16
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    ],
    "instructions": [
      [
        "SQRSHRUN"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "int16x4_t a",
      "const int n"
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      "value": "int16x4_t"
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        "maximum": 15
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      "A32",
      "A64"
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    "instructions": [
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        "SQSHL"
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  {
    "SIMD_ISA": "Neon",
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      "value": "int32x2_t"
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        "register": "Vn.2S"
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        "maximum": 31
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
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      "a": {
        "register": "Dn"
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      "n": {
        "minimum": 0,
        "maximum": 63
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      "A32",
      "A64"
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    "instructions": [
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        "SQSHL"
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int8x8_t a",
      "const int n"
    ],
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      "value": "int8x8_t"
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        "register": "Vn.8B"
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        "maximum": 7
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      "A32",
      "A64"
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    "instructions": [
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        "SQSHL"
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
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        "register": "Vn.4H"
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      "n": {
        "minimum": 0,
        "maximum": 15
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQSHL"
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
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        "register": "Vn.2S"
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        "maximum": 31
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "value": "uint64x1_t"
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        "register": "Dn"
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        "minimum": 0,
        "maximum": 63
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      "A32",
      "A64"
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        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t a",
      "const int n"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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        "maximum": 7
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      "A32",
      "A64"
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        "UQSHL"
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    "SIMD_ISA": "Neon",
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      "int16x4_t b"
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      "value": "int16x4_t"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A64"
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  {
    "SIMD_ISA": "Neon",
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      "int32x2_t b"
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      "value": "int32x2_t"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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    "instructions": [
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        "SQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_s64",
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      "int64x1_t b"
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      "value": "int64x1_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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      "A32",
      "A64"
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    "instructions": [
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        "SQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "int8x8_t b"
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      "value": "int8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
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        "SQSHL"
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  {
    "SIMD_ISA": "Neon",
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      "int16x4_t b"
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    "return_type": {
      "value": "uint16x4_t"
    },
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t a",
      "int32x2_t b"
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    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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    "instructions": [
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        "UQSHL"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vqshl_u8",
    "arguments": [
      "uint8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
      }
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqshlb_n_s8",
    "arguments": [
      "int8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "n": {
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    "return_type": {
      "value": "uint16x8_t"
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        "register": "Vn.8H"
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      "n": {
        "minimum": 0,
        "maximum": 15
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      "A64"
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        "SQSHLU"
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    ]
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "uint32x4_t"
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        "register": "Vn.4S"
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        "maximum": 31
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        "SQSHLU"
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    "SIMD_ISA": "Neon",
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      "const int n"
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        "register": "Vn.2D"
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        "maximum": 63
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      "A64"
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        "SQSHLU"
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  {
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  {
    "SIMD_ISA": "Neon",
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        "register": "Sn"
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        "SQSHLU"
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  {
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      "int16x8_t a",
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        "register": "Vn.8H"
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        "SQSHRN2"
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  {
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      "int32x4_t a",
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        "register": "Vd.4H"
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        "SQSHRN2"
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  {
    "SIMD_ISA": "Neon",
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      "int32x2_t r",
      "int64x2_t a",
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        "register": "Vn.2D"
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        "register": "Vd.2S"
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        "SQSHRN2"
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  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t r",
      "uint16x8_t a",
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        "register": "Vn.8H"
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        "register": "Vd.8B"
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      [
        "UQSHRN2"
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  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t r",
      "uint32x4_t a",
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        "register": "Vn.4S"
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        "register": "Vd.4H"
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      [
        "UQSHRN2"
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  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t r",
      "uint64x2_t a",
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      "value": "uint32x4_t"
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        "register": "Vn.2D"
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        "register": "Vd.2S"
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        "UQSHRN2"
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t a",
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        "SQSHRN"
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        "SQSHRN"
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    "SIMD_ISA": "Neon",
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      "value": "int32x2_t"
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        "SQSHRN"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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    "SIMD_ISA": "Neon",
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        "register": "Dn"
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        "register": "Sn"
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        "register": "Vn.4H"
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        "register": "Vm.2S"
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      "A64"
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    "SIMD_ISA": "Neon",
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      "int64x1_t b"
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        "register": "Dn"
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        "register": "Dm"
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      "A64"
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        "SQSUB"
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    "SIMD_ISA": "Neon",
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      "int8x8_t b"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A64"
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        "SQSUB"
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  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a",
      "uint16x4_t b"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
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    "instructions": [
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  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsub_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubb_s8",
    "arguments": [
      "int8_t a",
      "int8_t b"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubb_u8",
    "arguments": [
      "uint8_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "uint8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bn"
      },
      "b": {
        "register": "Bm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubh_s16",
    "arguments": [
      "int16_t a",
      "int16_t b"
    ],
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      "value": "int16_t"
    },
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      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubh_u16",
    "arguments": [
      "uint16_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "uint16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubs_s32",
    "arguments": [
      "int32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqsubs_u32",
    "arguments": [
      "uint32_t a",
      "uint32_t b"
    ],
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      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UQSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1_p8",
    "arguments": [
      "poly8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1_s8",
    "arguments": [
      "int8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1_u8",
    "arguments": [
      "uint8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1q_p8",
    "arguments": [
      "poly8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1q_s8",
    "arguments": [
      "int8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl1q_u8",
    "arguments": [
      "uint8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2_p8",
    "arguments": [
      "poly8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2_s8",
    "arguments": [
      "int8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2_u8",
    "arguments": [
      "uint8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2q_p8",
    "arguments": [
      "poly8x16x2_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2q_s8",
    "arguments": [
      "int8x16x2_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl2q_u8",
    "arguments": [
      "uint8x16x2_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl3_p8",
    "arguments": [
      "poly8x16x3_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl3_s8",
    "arguments": [
      "int8x16x3_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl3_u8",
    "arguments": [
      "uint8x16x3_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl3q_p8",
    "arguments": [
      "poly8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl3q_s8",
    "arguments": [
      "int8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl3q_u8",
    "arguments": [
      "uint8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl4_p8",
    "arguments": [
      "poly8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl4_s8",
    "arguments": [
      "int8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl4_u8",
    "arguments": [
      "uint8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl4q_p8",
    "arguments": [
      "poly8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl4q_s8",
    "arguments": [
      "int8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbl4q_u8",
    "arguments": [
      "uint8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx1_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx1_s8",
    "arguments": [
      "int8x8_t a",
      "int8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx1_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x16_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx1q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx1q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx1q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx2_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx2_s8",
    "arguments": [
      "int8x8_t a",
      "int8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx2_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x16x2_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx2q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16x2_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx2q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16x2_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx2q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16x2_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x16x3_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3_s8",
    "arguments": [
      "int8x8_t a",
      "int8x16x3_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x16x3_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx3q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16x3_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4_s8",
    "arguments": [
      "int8x8_t a",
      "int8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x16x4_t t",
      "uint8x8_t idx"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "idx": {
        "register": "Vm.8B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vqtbx4q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16x4_t t",
      "uint8x16_t idx"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "idx": {
        "register": "Vm.16B"
      },
      "t": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "TBX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RADDHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vraddhn_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RADDHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrax1q_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {}
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RAX1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbit_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbit_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbit_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbitq_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbitq_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrbitq_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RBIT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpe_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpe_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpe_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpe_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecped_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpeq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpes_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecps_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecps_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecps_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpsq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpss_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpxd_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpxh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrecpxs_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRECPX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f16_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f32_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_f64_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p16_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p64_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_p8_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s16_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s32_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s64_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_s8_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u16_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u32_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u64_u8",
    "arguments": [
      "uint8x8_t a"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_p16",
    "arguments": [
      "poly16x4_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_p64",
    "arguments": [
      "poly64x1_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_p8",
    "arguments": [
      "poly8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_s16",
    "arguments": [
      "int16x4_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_s32",
    "arguments": [
      "int32x2_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_s64",
    "arguments": [
      "int64x1_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_s8",
    "arguments": [
      "int8x8_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_u16",
    "arguments": [
      "uint16x4_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_u32",
    "arguments": [
      "uint32x2_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpret_u8_u64",
    "arguments": [
      "uint64x1_t a"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f16_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f32_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_f64_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p128_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "poly128_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p16_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p64_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_p8_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s16_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s32_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s64_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_s8_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u16_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u32_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u64_u8",
    "arguments": [
      "uint8x16_t a"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_p128",
    "arguments": [
      "poly128_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.1Q"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_p16",
    "arguments": [
      "poly16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_p64",
    "arguments": [
      "poly64x2_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_p8",
    "arguments": [
      "poly8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_s16",
    "arguments": [
      "int16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_s32",
    "arguments": [
      "int32x4_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_s64",
    "arguments": [
      "int64x2_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_s8",
    "arguments": [
      "int8x16_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_u16",
    "arguments": [
      "uint16x8_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vreinterpretq_u8_u64",
    "arguments": [
      "uint64x2_t a"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "NOP"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16_p8",
    "arguments": [
      "poly8x8_t vec"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16_s8",
    "arguments": [
      "int8x8_t vec"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16_u8",
    "arguments": [
      "uint8x8_t vec"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16q_p8",
    "arguments": [
      "poly8x16_t vec"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16q_s8",
    "arguments": [
      "int8x16_t vec"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev16q_u8",
    "arguments": [
      "uint8x16_t vec"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV16"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32_p16",
    "arguments": [
      "poly16x4_t vec"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32_p8",
    "arguments": [
      "poly8x8_t vec"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32_s16",
    "arguments": [
      "int16x4_t vec"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32_s8",
    "arguments": [
      "int8x8_t vec"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32_u16",
    "arguments": [
      "uint16x4_t vec"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32_u8",
    "arguments": [
      "uint8x8_t vec"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32q_p16",
    "arguments": [
      "poly16x8_t vec"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32q_p8",
    "arguments": [
      "poly8x16_t vec"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32q_s16",
    "arguments": [
      "int16x8_t vec"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32q_s8",
    "arguments": [
      "int8x16_t vec"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32q_u16",
    "arguments": [
      "uint16x8_t vec"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev32q_u8",
    "arguments": [
      "uint8x16_t vec"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV32"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_f16",
    "arguments": [
      "float16x4_t vec"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_f32",
    "arguments": [
      "float32x2_t vec"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_p16",
    "arguments": [
      "poly16x4_t vec"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_p8",
    "arguments": [
      "poly8x8_t vec"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "vec": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "REV64"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrev64_s16",
    "arguments": [
      "int16x4_t vec"
    ],
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      "value": "int16x4_t"
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        "register": "Vn.4H"
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    "SIMD_ISA": "Neon",
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        "register": "Vm.4H"
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        "register": "Vm.8B"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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      "A64"
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        "register": "Vn"
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        "FRINT32X"
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        "register": "Vn"
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        "FRINT32X"
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        "register": "Vn"
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        "register": "Dn"
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        "register": "Vn"
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        "FRINT32Z"
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        "register": "Vn"
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        "register": "Dn"
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        "register": "Vn"
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        "register": "Vn"
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        "register": "Vn"
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        "FRINT64Z"
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    "SIMD_ISA": "Neon",
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      "value": "float64x1_t"
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        "register": "Dn"
      }
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        "FRINT64Z"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "value": "float32x4_t"
    },
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        "register": "Vn"
      }
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        "FRINT64Z"
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  },
  {
    "SIMD_ISA": "Neon",
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndxh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndxq_f16",
    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndxq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrndxq_f64",
    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRINTX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshl_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshl_u16",
    "arguments": [
      "uint16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshl_u32",
    "arguments": [
      "uint32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshl_u64",
    "arguments": [
      "uint64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshl_u8",
    "arguments": [
      "uint8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshld_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshld_u64",
    "arguments": [
      "uint64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_u16",
    "arguments": [
      "uint16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_u32",
    "arguments": [
      "uint32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_u64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshlq_u8",
    "arguments": [
      "uint8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_s16",
    "arguments": [
      "int16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_s32",
    "arguments": [
      "int32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_s64",
    "arguments": [
      "int64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_s8",
    "arguments": [
      "int8x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_u16",
    "arguments": [
      "uint16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_u32",
    "arguments": [
      "uint32x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_u64",
    "arguments": [
      "uint64x1_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshr_n_u8",
    "arguments": [
      "uint8x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrd_n_s64",
    "arguments": [
      "int64_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrd_n_u64",
    "arguments": [
      "uint64_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_high_n_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      },
      "r": {
        "register": "32(Vd)"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSHRN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_s16",
    "arguments": [
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_u16",
    "arguments": [
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_u32",
    "arguments": [
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
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      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrn_n_u64",
    "arguments": [
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSHRN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_s16",
    "arguments": [
      "int16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_s32",
    "arguments": [
      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_s8",
    "arguments": [
      "int8x16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
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      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrshrq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrte_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrte_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrte_f64",
    "arguments": [
      "float64x1_t a"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrte_u32",
    "arguments": [
      "uint32x2_t a"
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    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrted_f64",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "float64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteh_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteq_f16",
    "arguments": [
      "float16x8_t a"
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    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteq_f32",
    "arguments": [
      "float32x4_t a"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteq_f64",
    "arguments": [
      "float64x2_t a"
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    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrteq_u32",
    "arguments": [
      "uint32x4_t a"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtes_f32",
    "arguments": [
      "float32_t a"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTE"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrts_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrts_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrts_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsd_f64",
    "arguments": [
      "float64_t a",
      "float64_t b"
    ],
    "return_type": {
      "value": "float64_t"
    },
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      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtsq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsqrtss_f32",
    "arguments": [
      "float32_t a",
      "float32_t b"
    ],
    "return_type": {
      "value": "float32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sn"
      },
      "b": {
        "register": "Sm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FRSQRTS"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsra_n_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsrad_n_s64",
    "arguments": [
      "int64_t a",
      "int64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsrad_n_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsraq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "URSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vrsubhn_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "RSUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_f16",
    "arguments": [
      "float16_t a",
      "float16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "VnH"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_f32",
    "arguments": [
      "float32_t a",
      "float32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_f64",
    "arguments": [
      "float64_t a",
      "float64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_p16",
    "arguments": [
      "poly16_t a",
      "poly16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_p64",
    "arguments": [
      "poly64_t a",
      "poly64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_p8",
    "arguments": [
      "poly8_t a",
      "poly8x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_s64",
    "arguments": [
      "int64_t a",
      "int64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_s8",
    "arguments": [
      "int8_t a",
      "int8x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_u16",
    "arguments": [
      "uint16_t a",
      "uint16x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_u32",
    "arguments": [
      "uint32_t a",
      "uint32x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_u64",
    "arguments": [
      "uint64_t a",
      "uint64x1_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "v": {
        "register": "Vd.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vset_lane_u8",
    "arguments": [
      "uint8_t a",
      "uint8x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_f16",
    "arguments": [
      "float16_t a",
      "float16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "VnH"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_f32",
    "arguments": [
      "float32_t a",
      "float32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_f64",
    "arguments": [
      "float64_t a",
      "float64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_p16",
    "arguments": [
      "poly16_t a",
      "poly16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_p64",
    "arguments": [
      "poly64_t a",
      "poly64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_p8",
    "arguments": [
      "poly8_t a",
      "poly8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_s16",
    "arguments": [
      "int16_t a",
      "int16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_s32",
    "arguments": [
      "int32_t a",
      "int32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_s64",
    "arguments": [
      "int64_t a",
      "int64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_s8",
    "arguments": [
      "int8_t a",
      "int8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_u16",
    "arguments": [
      "uint16_t a",
      "uint16x8_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "v": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_u32",
    "arguments": [
      "uint32_t a",
      "uint32x4_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "v": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_u64",
    "arguments": [
      "uint64_t a",
      "uint64x2_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "v": {
        "register": "Vd.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsetq_lane_u8",
    "arguments": [
      "uint8_t a",
      "uint8x16_t v",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Rn"
      },
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "v": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "MOV"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1cq_u32",
    "arguments": [
      "uint32x4_t hash_abcd",
      "uint32_t hash_e",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qd"
      },
      "hash_e": {
        "register": "Sn"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1C"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1h_u32",
    "arguments": [
      "uint32_t hash_e"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "hash_e": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1H"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1mq_u32",
    "arguments": [
      "uint32x4_t hash_abcd",
      "uint32_t hash_e",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qd"
      },
      "hash_e": {
        "register": "Sn"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1M"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1pq_u32",
    "arguments": [
      "uint32x4_t hash_abcd",
      "uint32_t hash_e",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qd"
      },
      "hash_e": {
        "register": "Sn"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1P"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1su0q_u32",
    "arguments": [
      "uint32x4_t w0_3",
      "uint32x4_t w4_7",
      "uint32x4_t w8_11"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "w0_3": {
        "register": "Vd.4S"
      },
      "w4_7": {
        "register": "Vn.4S"
      },
      "w8_11": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1SU0"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha1su1q_u32",
    "arguments": [
      "uint32x4_t tw0_3",
      "uint32x4_t w12_15"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "tw0_3": {
        "register": "Vd.4S"
      },
      "w12_15": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA1SU1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha256h2q_u32",
    "arguments": [
      "uint32x4_t hash_efgh",
      "uint32x4_t hash_abcd",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qn"
      },
      "hash_efgh": {
        "register": "Qd"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA256H2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha256hq_u32",
    "arguments": [
      "uint32x4_t hash_abcd",
      "uint32x4_t hash_efgh",
      "uint32x4_t wk"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "hash_abcd": {
        "register": "Qd"
      },
      "hash_efgh": {
        "register": "Qn"
      },
      "wk": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA256H"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha256su0q_u32",
    "arguments": [
      "uint32x4_t w0_3",
      "uint32x4_t w4_7"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "w0_3": {
        "register": "Vd.4S"
      },
      "w4_7": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA256SU0"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha256su1q_u32",
    "arguments": [
      "uint32x4_t tw0_3",
      "uint32x4_t w8_11",
      "uint32x4_t w12_15"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "tw0_3": {
        "register": "Vd.4S"
      },
      "w12_15": {
        "register": "Vm.4S"
      },
      "w8_11": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHA256SU1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha512h2q_u64",
    "arguments": [
      "uint64x2_t sum_ab",
      "uint64x2_t hash_c_",
      "uint64x2_t hash_ab"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "hash_ab": {},
      "hash_c_": {
        "register": "Qn"
      },
      "sum_ab": {
        "register": "Qd"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHA512H2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha512hq_u64",
    "arguments": [
      "uint64x2_t hash_ed",
      "uint64x2_t hash_gf",
      "uint64x2_t kwh_kwh2"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "hash_ed": {
        "register": "Qd"
      },
      "hash_gf": {
        "register": "Qn"
      },
      "kwh_kwh2": {}
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHA512H"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha512su0q_u64",
    "arguments": [
      "uint64x2_t w0_1",
      "uint64x2_t w2_"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "w0_1": {
        "register": "Vd.2D"
      },
      "w2_": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHA512SU0"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsha512su1q_u64",
    "arguments": [
      "uint64x2_t s01_s02",
      "uint64x2_t w14_15",
      "uint64x2_t w9_10"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "s01_s02": {
        "register": "Vd.2D"
      },
      "w14_15": {
        "register": "Vn.2D"
      },
      "w9_10": {}
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SHA512SU1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_s16",
    "arguments": [
      "int16x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_s32",
    "arguments": [
      "int32x2_t a",
      "const int n"
    ],
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      "value": "int32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "n": {
        "minimum": 0,
        "maximum": 31
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_s64",
    "arguments": [
      "int64x1_t a",
      "const int n"
    ],
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      "value": "int64x1_t"
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      "a": {
        "register": "Dn"
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      "n": {
        "minimum": 0,
        "maximum": 63
      }
    },
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      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a",
      "const int n"
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      "value": "int8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "n": {
        "minimum": 0,
        "maximum": 7
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      "A32",
      "A64"
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    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_u16",
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      "uint16x4_t a",
      "const int n"
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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      "n": {
        "minimum": 0,
        "maximum": 15
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_u32",
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      "uint32x2_t a",
      "const int n"
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      "value": "uint32x2_t"
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        "register": "Vn.2S"
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      "n": {
        "minimum": 0,
        "maximum": 31
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      "A32",
      "A64"
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      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_n_u64",
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      "const int n"
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dn"
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        "minimum": 0,
        "maximum": 63
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t a",
      "const int n"
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "n": {
        "minimum": 0,
        "maximum": 7
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int16x4_t a",
      "int16x4_t b"
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      "value": "int16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSHL"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x2_t a",
      "int32x2_t b"
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      "value": "int32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int64x1_t a",
      "int64x1_t b"
    ],
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      "value": "int64x1_t"
    },
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSHL"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a",
      "int8x8_t b"
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      "value": "int8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSHL"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshl_u16",
    "arguments": [
      "uint16x4_t a",
      "int16x4_t b"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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        "USHL"
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  {
    "SIMD_ISA": "Neon",
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      "uint32x2_t a",
      "int32x2_t b"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "A32",
      "A64"
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        "USHL"
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  {
    "SIMD_ISA": "Neon",
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      "int64x1_t b"
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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      "A32",
      "A64"
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      [
        "USHL"
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  {
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      "uint8x8_t a",
      "int8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A32",
      "A64"
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    "instructions": [
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        "USHL"
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    "SIMD_ISA": "Neon",
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      "int64_t a",
      "const int n"
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      "value": "int64_t"
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        "register": "Dn"
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        "minimum": 0,
        "maximum": 63
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        "SHL"
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "uint64_t"
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        "register": "Dn"
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        "minimum": 0,
        "maximum": 63
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    "instructions": [
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        "SHL"
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    ]
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  {
    "SIMD_ISA": "Neon",
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      "int64_t a",
      "int64_t b"
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      "value": "int64_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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    "instructions": [
      [
        "SSHL"
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    ]
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  {
    "SIMD_ISA": "Neon",
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      "int64_t b"
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      "value": "uint64_t"
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      "a": {
        "register": "Dn"
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      "b": {
        "register": "Dm"
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    "instructions": [
      [
        "USHL"
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  },
  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "int32x4_t"
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        "register": "Vn.8H"
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        "maximum": 16
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        "SSHLL2"
      ]
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    "SIMD_ISA": "Neon",
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      "value": "int64x2_t"
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        "register": "Vn.4S"
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        "maximum": 32
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        "SSHLL2"
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  },
  {
    "SIMD_ISA": "Neon",
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      "a": {
        "register": "Vn.16B"
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        "maximum": 8
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        "SSHLL2"
      ]
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "minimum": 0,
        "maximum": 16
      }
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        "USHLL2"
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  },
  {
    "SIMD_ISA": "Neon",
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        "USHLL2"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "maximum": 8
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        "USHLL2"
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  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.4H"
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        "maximum": 16
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      "A32",
      "A64"
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        "SSHLL"
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        "register": "Vn.2S"
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        "maximum": 32
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      "A64"
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        "register": "Vn.8B"
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      "A64"
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    "SIMD_ISA": "Neon",
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        "USHLL"
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  {
    "SIMD_ISA": "Neon",
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        "maximum": 32
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    "instructions": [
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        "USHLL"
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  {
    "SIMD_ISA": "Neon",
    "name": "vshll_n_u8",
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      "const int n"
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      "value": "uint16x8_t"
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        "register": "Vn.8B"
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        "maximum": 8
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      "A32",
      "A64"
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    "instructions": [
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        "USHLL"
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  {
    "SIMD_ISA": "Neon",
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      "value": "int16x8_t"
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        "maximum": 15
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      "A32",
      "A64"
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        "SHL"
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  {
    "SIMD_ISA": "Neon",
    "name": "vshlq_n_s32",
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      "const int n"
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    "return_type": {
      "value": "int32x4_t"
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        "register": "Vn.4S"
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        "maximum": 31
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      "A32",
      "A64"
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    "instructions": [
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        "SHL"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vshlq_n_s64",
    "arguments": [
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      "const int n"
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    "return_type": {
      "value": "int64x2_t"
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    "Arguments_Preparation": {
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        "register": "Vn.2D"
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        "minimum": 0,
        "maximum": 63
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
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        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshlq_n_s8",
    "arguments": [
      "int8x16_t a",
      "const int n"
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    "return_type": {
      "value": "int8x16_t"
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        "register": "Vn.16B"
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      "n": {
        "minimum": 0,
        "maximum": 7
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshlq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
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      "n": {
        "minimum": 0,
        "maximum": 15
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint32x4_t a",
      "const int n"
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      "value": "uint32x4_t"
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        "register": "Vn.4S"
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        "minimum": 0,
        "maximum": 31
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      "A32",
      "A64"
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      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint64x2_t a",
      "const int n"
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      "value": "uint64x2_t"
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        "register": "Vn.2D"
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      "n": {
        "minimum": 0,
        "maximum": 63
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    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint8x16_t a",
      "const int n"
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      "value": "uint8x16_t"
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        "register": "Vn.16B"
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        "minimum": 0,
        "maximum": 7
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      "A32",
      "A64"
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      [
        "SHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
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      "value": "int16x8_t"
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshlq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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      [
        "SSHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int64x2_t a",
      "int64x2_t b"
    ],
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      "value": "int64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      "A32",
      "A64"
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      [
        "SSHL"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x16_t a",
      "int8x16_t b"
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      "value": "int8x16_t"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSHL"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint16x8_t a",
      "int16x8_t b"
    ],
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      "A32",
      "A64"
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    "instructions": [
      [
        "USHL"
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  },
  {
    "SIMD_ISA": "Neon",
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      "uint32x4_t a",
      "int32x4_t b"
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      "value": "uint32x4_t"
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        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A32",
      "A64"
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      [
        "USHL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint64x2_t a",
      "int64x2_t b"
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      "value": "uint64x2_t"
    },
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      "A32",
      "A64"
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      [
        "USHL"
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    ]
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  {
    "SIMD_ISA": "Neon",
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      "uint8x16_t a",
      "int8x16_t b"
    ],
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      "value": "uint8x16_t"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USHL"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int16x4_t a",
      "const int n"
    ],
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      "value": "int16x4_t"
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        "register": "Vn.4H"
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        "maximum": 16
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int32x2_t a",
      "const int n"
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      "value": "int32x2_t"
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        "register": "Vn.2S"
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        "minimum": 1,
        "maximum": 32
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "int64x1_t"
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        "register": "Dn"
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      "n": {
        "minimum": 1,
        "maximum": 64
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      "A32",
      "A64"
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      [
        "SSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "int8x8_t a",
      "const int n"
    ],
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      "value": "int8x8_t"
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        "register": "Vn.8B"
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        "maximum": 8
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      "A32",
      "A64"
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        "SSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint16x4_t a",
      "const int n"
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      "value": "uint16x4_t"
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        "register": "Vn.4H"
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        "maximum": 16
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      "A32",
      "A64"
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    "instructions": [
      [
        "USHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "uint32x2_t"
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        "register": "Vn.2S"
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        "maximum": 32
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      "A32",
      "A64"
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    "instructions": [
      [
        "USHR"
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    ]
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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        "register": "Dn"
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        "minimum": 1,
        "maximum": 64
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      "A32",
      "A64"
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      [
        "USHR"
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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        "minimum": 1,
        "maximum": 8
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      "A32",
      "A64"
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        "USHR"
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    ]
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "int64_t"
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        "register": "Dn"
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        "maximum": 64
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        "SSHR"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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        "register": "Dn"
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        "maximum": 64
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        "USHR"
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  },
  {
    "SIMD_ISA": "Neon",
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      "int8x8_t r",
      "int16x8_t a",
      "const int n"
    ],
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        "register": "Vn.8H"
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        "maximum": 8
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        "register": "Vd.8B"
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    },
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        "SHRN2"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
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      "int16x4_t r",
      "int32x4_t a",
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    ],
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        "register": "Vn.4S"
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        "maximum": 16
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        "register": "Vd.4H"
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        "SHRN2"
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  },
  {
    "SIMD_ISA": "Neon",
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      "int32x2_t r",
      "int64x2_t a",
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        "register": "Vn.2D"
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        "minimum": 1,
        "maximum": 32
      },
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        "register": "Vd.2S"
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        "SHRN2"
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  {
    "SIMD_ISA": "Neon",
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      "uint8x8_t r",
      "uint16x8_t a",
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    ],
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      "value": "uint8x16_t"
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        "register": "Vn.8H"
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        "minimum": 1,
        "maximum": 8
      },
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        "register": "Vd.8B"
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    },
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        "SHRN2"
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  },
  {
    "SIMD_ISA": "Neon",
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      "uint32x4_t a",
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    ],
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      "value": "uint16x8_t"
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        "register": "Vn.4S"
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        "minimum": 1,
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        "register": "Vd.4H"
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        "SHRN2"
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  },
  {
    "SIMD_ISA": "Neon",
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      "uint64x2_t a",
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    ],
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      "value": "uint32x4_t"
    },
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        "register": "Vn.2D"
      },
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        "minimum": 1,
        "maximum": 32
      },
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        "register": "Vd.2S"
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    },
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        "SHRN2"
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  },
  {
    "SIMD_ISA": "Neon",
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      "int16x8_t a",
      "const int n"
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      "value": "int8x8_t"
    },
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        "register": "Vn.8H"
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        "maximum": 8
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      "A32",
      "A64"
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        "SHRN"
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  },
  {
    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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        "maximum": 16
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      "A64"
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        "SHRN"
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  },
  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "int32x2_t"
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        "register": "Vn.2D"
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        "minimum": 1,
        "maximum": 32
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      "A32",
      "A64"
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        "SHRN"
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "uint8x8_t"
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        "register": "Vn.8H"
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        "minimum": 1,
        "maximum": 8
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    },
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      "A32",
      "A64"
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        "SHRN"
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "uint16x4_t"
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        "register": "Vn.4S"
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        "minimum": 1,
        "maximum": 16
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    },
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      "A32",
      "A64"
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        "SHRN"
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  {
    "SIMD_ISA": "Neon",
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      "const int n"
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      "value": "uint32x2_t"
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        "register": "Vn.2D"
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        "minimum": 1,
        "maximum": 32
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      "A32",
      "A64"
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        "SHRN"
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  },
  {
    "SIMD_ISA": "Neon",
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      "int16x8_t a",
      "const int n"
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    "return_type": {
      "value": "int16x8_t"
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        "register": "Vn.8H"
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      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshrq_n_s32",
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      "int32x4_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
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        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshrq_n_s64",
    "arguments": [
      "int64x2_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSHR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vshrq_n_s8",
    "arguments": [
      "int8x16_t a",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
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      "n": {
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  {
    "SIMD_ISA": "Neon",
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      "uint16x8_t a",
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      "value": "uint16x8_t"
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  {
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      "value": "uint32x4_t"
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        "USHR"
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  {
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        "register": "Vn.2D"
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  {
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        "register": "Vn.16B"
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        "USHR"
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      "poly16x4_t b",
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        "SLI"
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      "poly64x1_t b",
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        "SLI"
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        "SM3SS1"
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        "register": "Vd.4S"
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        "SM3TT1A"
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  {
    "SIMD_ISA": "Neon",
    "name": "vsm3tt2aq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c",
      "const int imm2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {},
      "c": {},
      "imm2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3TT2A"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm3tt2bq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "uint32x4_t c",
      "const int imm2"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {},
      "c": {},
      "imm2": {
        "minimum": 0,
        "maximum": 3
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM3TT2B"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsm4ekeyq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
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      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      },
      "b": {}
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SM4EKEY"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
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      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {}
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      "A64"
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      [
        "SM4E"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsqadd_u16",
    "arguments": [
      "uint16x4_t a",
      "int16x4_t b"
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      "value": "uint16x4_t"
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      "a": {
        "register": "Vd.4H"
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      "b": {
        "register": "Vn.4H"
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint32x2_t a",
      "int32x2_t b"
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      "value": "uint32x2_t"
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      "a": {
        "register": "Vd.2S"
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      "b": {
        "register": "Vn.2S"
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqadd_u64",
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      "uint64x1_t a",
      "int64x1_t b"
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      "value": "uint64x1_t"
    },
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      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
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      "A64"
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      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint8x8_t a",
      "int8x8_t b"
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vd.8B"
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      "b": {
        "register": "Vn.8B"
      }
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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      "uint8_t a",
      "int8_t b"
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      "value": "uint8_t"
    },
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      "a": {
        "register": "Bd"
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      "b": {
        "register": "Bn"
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddd_u64",
    "arguments": [
      "uint64_t a",
      "int64_t b"
    ],
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      "value": "uint64_t"
    },
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      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
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    },
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint16_t a",
      "int16_t b"
    ],
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      "value": "uint16_t"
    },
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      "a": {
        "register": "Hd"
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      "b": {
        "register": "Hn"
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddq_u16",
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      "uint16x8_t a",
      "int16x8_t b"
    ],
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      "value": "uint16x8_t"
    },
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      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      }
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddq_u32",
    "arguments": [
      "uint32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
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      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      }
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddq_u64",
    "arguments": [
      "uint64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
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      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      }
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqaddq_u8",
    "arguments": [
      "uint8x16_t a",
      "int8x16_t b"
    ],
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      "value": "uint8x16_t"
    },
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      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqadds_u32",
    "arguments": [
      "uint32_t a",
      "int32_t b"
    ],
    "return_type": {
      "value": "uint32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrt_f16",
    "arguments": [
      "float16x4_t a"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      }
    },
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      "A64"
    ],
    "instructions": [
      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrt_f32",
    "arguments": [
      "float32x2_t a"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
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      "a": {
        "register": "Vn.2S"
      }
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    ],
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      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrt_f64",
    "arguments": [
      "float64x1_t a"
    ],
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      "value": "float64x1_t"
    },
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      "a": {
        "register": "Dn"
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    },
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        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrth_f16",
    "arguments": [
      "float16_t a"
    ],
    "return_type": {
      "value": "float16_t"
    },
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      "a": {
        "register": "Hn"
      }
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      "A64"
    ],
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        "FSQRT"
      ]
    ]
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    "SIMD_ISA": "Neon",
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    "arguments": [
      "float16x8_t a"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
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      "a": {
        "register": "Vn.8H"
      }
    },
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    ],
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      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsqrtq_f32",
    "arguments": [
      "float32x4_t a"
    ],
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      "value": "float32x4_t"
    },
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      "a": {
        "register": "Vn.4S"
      }
    },
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    ],
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      [
        "FSQRT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "float64x2_t a"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      }
    },
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    ],
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        "FSQRT"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_s16",
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      "int16x4_t a",
      "int16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
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        "register": "Vd.4H"
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      "b": {
        "register": "Vn.4H"
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        "minimum": 1,
        "maximum": 16
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "SSRA"
      ]
    ]
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  {
    "SIMD_ISA": "Neon",
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      "int32x2_t a",
      "int32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
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        "register": "Vd.2S"
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      "b": {
        "register": "Vn.2S"
      },
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        "minimum": 1,
        "maximum": 32
      }
    },
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int64x1_t a",
      "int64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
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      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
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      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
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      "A32",
      "A64"
    ],
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        "SSRA"
      ]
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
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        "register": "Vd.8B"
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      "b": {
        "register": "Vn.8B"
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        "maximum": 8
      }
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      "A32",
      "A64"
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        "SSRA"
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    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "const int n"
    ],
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      "value": "uint16x4_t"
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        "register": "Vd.4H"
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      "b": {
        "register": "Vn.4H"
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        "minimum": 1,
        "maximum": 16
      }
    },
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      "A64"
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        "USRA"
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    "SIMD_ISA": "Neon",
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    "arguments": [
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      "uint32x2_t b",
      "const int n"
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      "value": "uint32x2_t"
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        "register": "Vd.2S"
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      "b": {
        "register": "Vn.2S"
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        "minimum": 1,
        "maximum": 32
      }
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      "A32",
      "A64"
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        "USRA"
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  {
    "SIMD_ISA": "Neon",
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    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "const int n"
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      "value": "uint64x1_t"
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      "a": {
        "register": "Dd"
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      "b": {
        "register": "Dn"
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        "minimum": 1,
        "maximum": 64
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    },
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      "A32",
      "A64"
    ],
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        "USRA"
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    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsra_n_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
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        "register": "Vd.8B"
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      "b": {
        "register": "Vn.8B"
      },
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        "minimum": 1,
        "maximum": 8
      }
    },
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      "A32",
      "A64"
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    "instructions": [
      [
        "USRA"
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    ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vsrad_n_s64",
    "arguments": [
      "int64_t a",
      "int64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
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        "register": "Dd"
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      "b": {
        "register": "Dn"
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        "minimum": 1,
        "maximum": 64
      }
    },
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    ],
    "instructions": [
      [
        "SSRA"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsrad_n_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
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        "register": "Dd"
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      "b": {
        "register": "Dn"
      },
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        "minimum": 1,
        "maximum": 64
      }
    },
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    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
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        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
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      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsraq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USRA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_p64",
    "arguments": [
      "poly64x1_t a",
      "poly64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsri_n_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsrid_n_s64",
    "arguments": [
      "int64_t a",
      "int64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsrid_n_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      },
      "n": {
        "minimum": 1,
        "maximum": 16
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      },
      "n": {
        "minimum": 1,
        "maximum": 32
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      },
      "n": {
        "minimum": 1,
        "maximum": 64
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsriq_n_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b",
      "const int n"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      },
      "n": {
        "minimum": 1,
        "maximum": 8
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SRI"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f16_x2",
    "arguments": [
      "float16_t * ptr",
      "float16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f16_x3",
    "arguments": [
      "float16_t * ptr",
      "float16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f16_x4",
    "arguments": [
      "float16_t * ptr",
      "float16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f32_x2",
    "arguments": [
      "float32_t * ptr",
      "float32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f32_x3",
    "arguments": [
      "float32_t * ptr",
      "float32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f32_x4",
    "arguments": [
      "float32_t * ptr",
      "float32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f64_x2",
    "arguments": [
      "float64_t * ptr",
      "float64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f64_x3",
    "arguments": [
      "float64_t * ptr",
      "float64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_f64_x4",
    "arguments": [
      "float64_t * ptr",
      "float64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p16_x2",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p16_x3",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p16_x4",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p64_x2",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p64_x3",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p64_x4",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p8_x2",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p8_x3",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_p8_x4",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s16_x2",
    "arguments": [
      "int16_t * ptr",
      "int16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s16_x3",
    "arguments": [
      "int16_t * ptr",
      "int16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s16_x4",
    "arguments": [
      "int16_t * ptr",
      "int16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s32_x2",
    "arguments": [
      "int32_t * ptr",
      "int32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s32_x3",
    "arguments": [
      "int32_t * ptr",
      "int32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s32_x4",
    "arguments": [
      "int32_t * ptr",
      "int32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s64_x2",
    "arguments": [
      "int64_t * ptr",
      "int64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s64_x3",
    "arguments": [
      "int64_t * ptr",
      "int64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s64_x4",
    "arguments": [
      "int64_t * ptr",
      "int64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s8_x2",
    "arguments": [
      "int8_t * ptr",
      "int8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s8_x3",
    "arguments": [
      "int8_t * ptr",
      "int8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_s8_x4",
    "arguments": [
      "int8_t * ptr",
      "int8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u16_x2",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u16_x3",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u16_x4",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u32_x2",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u32_x3",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u32_x4",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u64_x2",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u64_x3",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u64_x4",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u8_x2",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u8_x3",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1_u8_x4",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f16_x2",
    "arguments": [
      "float16_t * ptr",
      "float16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f16_x3",
    "arguments": [
      "float16_t * ptr",
      "float16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f16_x4",
    "arguments": [
      "float16_t * ptr",
      "float16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f32_x2",
    "arguments": [
      "float32_t * ptr",
      "float32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f32_x3",
    "arguments": [
      "float32_t * ptr",
      "float32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f32_x4",
    "arguments": [
      "float32_t * ptr",
      "float32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f64_x2",
    "arguments": [
      "float64_t * ptr",
      "float64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f64_x3",
    "arguments": [
      "float64_t * ptr",
      "float64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_f64_x4",
    "arguments": [
      "float64_t * ptr",
      "float64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p16_x2",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p16_x3",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p16_x4",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p64_x2",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p64_x3",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p64_x4",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p8_x2",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p8_x3",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_p8_x4",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s16_x2",
    "arguments": [
      "int16_t * ptr",
      "int16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s16_x3",
    "arguments": [
      "int16_t * ptr",
      "int16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s16_x4",
    "arguments": [
      "int16_t * ptr",
      "int16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s32_x2",
    "arguments": [
      "int32_t * ptr",
      "int32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s32_x3",
    "arguments": [
      "int32_t * ptr",
      "int32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s32_x4",
    "arguments": [
      "int32_t * ptr",
      "int32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s64_x2",
    "arguments": [
      "int64_t * ptr",
      "int64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s64_x3",
    "arguments": [
      "int64_t * ptr",
      "int64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s64_x4",
    "arguments": [
      "int64_t * ptr",
      "int64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s8_x2",
    "arguments": [
      "int8_t * ptr",
      "int8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s8_x3",
    "arguments": [
      "int8_t * ptr",
      "int8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_s8_x4",
    "arguments": [
      "int8_t * ptr",
      "int8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u16_x2",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u16_x3",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u16_x4",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u32_x2",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u32_x3",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u32_x4",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u64_x2",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u64_x3",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u64_x4",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u8_x2",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u8_x3",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst1q_u8_x4",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 2
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x2_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst2q_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x2_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt2.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x3_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst3q_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x3_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt3.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST3"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x1x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 0
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x1x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.1D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_f16",
    "arguments": [
      "float16_t * ptr",
      "float16x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_f32",
    "arguments": [
      "float32_t * ptr",
      "float32x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_f64",
    "arguments": [
      "float64_t * ptr",
      "float64x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 7
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_lane_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x4_t val",
      "const int lane"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "lane": {
        "minimum": 0,
        "maximum": 15
      },
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_p16",
    "arguments": [
      "poly16_t * ptr",
      "poly16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_p64",
    "arguments": [
      "poly64_t * ptr",
      "poly64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_p8",
    "arguments": [
      "poly8_t * ptr",
      "poly8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_s16",
    "arguments": [
      "int16_t * ptr",
      "int16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_s32",
    "arguments": [
      "int32_t * ptr",
      "int32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_s64",
    "arguments": [
      "int64_t * ptr",
      "int64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_s8",
    "arguments": [
      "int8_t * ptr",
      "int8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_u16",
    "arguments": [
      "uint16_t * ptr",
      "uint16x8x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_u32",
    "arguments": [
      "uint32_t * ptr",
      "uint32x4x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_u64",
    "arguments": [
      "uint64_t * ptr",
      "uint64x2x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vst4q_u8",
    "arguments": [
      "uint8_t * ptr",
      "uint8x16x4_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Vt4.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ST4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vstrq_p128",
    "arguments": [
      "poly128_t * ptr",
      "poly128_t val"
    ],
    "return_type": {
      "value": "void"
    },
    "Arguments_Preparation": {
      "ptr": {
        "register": "Xn"
      },
      "val": {
        "register": "Qt"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "STR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_f64",
    "arguments": [
      "float64x1_t a",
      "float64x1_t b"
    ],
    "return_type": {
      "value": "float64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_s64",
    "arguments": [
      "int64x1_t a",
      "int64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_u64",
    "arguments": [
      "uint64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "uint64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsub_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubd_s64",
    "arguments": [
      "int64_t a",
      "int64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubd_u64",
    "arguments": [
      "uint64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "uint64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      },
      "b": {
        "register": "Dm"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubh_f16",
    "arguments": [
      "float16_t a",
      "float16_t b"
    ],
    "return_type": {
      "value": "float16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hn"
      },
      "b": {
        "register": "Hm"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_s16",
    "arguments": [
      "int8x8_t r",
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_s32",
    "arguments": [
      "int16x4_t r",
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_s64",
    "arguments": [
      "int32x2_t r",
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_u16",
    "arguments": [
      "uint8x8_t r",
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      },
      "r": {
        "register": "Vd.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_u32",
    "arguments": [
      "uint16x4_t r",
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      },
      "r": {
        "register": "Vd.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_high_u64",
    "arguments": [
      "uint32x2_t r",
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUBHN2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubhn_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUBHN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_high_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBL2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubl_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBL"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FSUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SUB"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_s16",
    "arguments": [
      "int32x4_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_s32",
    "arguments": [
      "int64x2_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_s8",
    "arguments": [
      "int16x8_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SSUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_high_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USUBW2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_s16",
    "arguments": [
      "int32x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_s32",
    "arguments": [
      "int64x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_s8",
    "arguments": [
      "int16x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "SSUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_u16",
    "arguments": [
      "uint32x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_u32",
    "arguments": [
      "uint64x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsubw_u8",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USUBW"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vsudot_lane_s32",
    "arguments": [
      "int32x2_t r",
      "int8x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
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      "uint8x8_t a",
      "uint8x8_t b"
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      "value": "uint8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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      "A64"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float16x8_t a",
      "float16x8_t b"
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      "value": "float16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "float32x4_t a",
      "float32x4_t b"
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      "value": "float32x4_t"
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        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      "A64"
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      [
        "TRN1"
      ]
    ]
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    "SIMD_ISA": "Neon",
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      "float64x2_t b"
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      "value": "float64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      "A64"
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      [
        "TRN1"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "poly16x8_t b"
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      "value": "poly16x8_t"
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      [
        "TRN1"
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  {
    "SIMD_ISA": "Neon",
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      "poly64x2_t b"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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        "TRN1"
      ]
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    "SIMD_ISA": "Neon",
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      "poly8x16_t b"
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      "value": "poly8x16_t"
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        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      [
        "TRN1"
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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      "value": "int16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      [
        "TRN1"
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    "SIMD_ISA": "Neon",
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      "int32x4_t b"
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      "value": "int32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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      [
        "TRN1"
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  {
    "SIMD_ISA": "Neon",
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      "int64x2_t b"
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      "value": "int64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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      "A64"
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      [
        "TRN1"
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      "int8x16_t b"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      [
        "TRN1"
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  {
    "SIMD_ISA": "Neon",
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      "uint16x8_t a",
      "uint16x8_t b"
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      "value": "uint16x8_t"
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      "a": {
        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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      [
        "TRN1"
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    "SIMD_ISA": "Neon",
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      "uint32x4_t a",
      "uint32x4_t b"
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      "value": "uint32x4_t"
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      "a": {
        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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        "TRN1"
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    "SIMD_ISA": "Neon",
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      "uint64x2_t a",
      "uint64x2_t b"
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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        "TRN1"
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    "SIMD_ISA": "Neon",
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      "uint8x16_t b"
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      "value": "uint8x16_t"
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      "a": {
        "register": "Vn.16B"
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      "b": {
        "register": "Vm.16B"
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      [
        "TRN1"
      ]
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      "float16x4_t b"
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      "value": "float16x4_t"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "float32x2_t b"
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      "value": "float32x2_t"
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      "a": {
        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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        "TRN2"
      ]
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    "SIMD_ISA": "Neon",
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      "value": "poly16x4_t"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "poly8x8_t b"
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      "value": "poly8x8_t"
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      "a": {
        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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        "TRN2"
      ]
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      "int16x4_t b"
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      "value": "int16x4_t"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "int32x2_t b"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "int8x8_t b"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "uint32x2_t b"
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        "register": "Vn.2S"
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      "b": {
        "register": "Vm.2S"
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      "uint8x8_t b"
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      "value": "uint8x8_t"
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        "register": "Vn.8B"
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      "b": {
        "register": "Vm.8B"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "value": "float16x8_t"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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    "SIMD_ISA": "Neon",
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      "float32x4_t b"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "value": "float64x2_t"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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      "value": "int16x8_t"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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    "SIMD_ISA": "Neon",
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      "int32x4_t b"
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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    "SIMD_ISA": "Neon",
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      "int64x2_t b"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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    "SIMD_ISA": "Neon",
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      "uint16x8_t b"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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        "TRN2"
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    "SIMD_ISA": "Neon",
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      "uint32x4_t b"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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        "TRN2"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "uint64x2_t b"
    ],
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      "value": "uint64x2_t"
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      "a": {
        "register": "Vn.2D"
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      "b": {
        "register": "Vm.2D"
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    "instructions": [
      [
        "TRN2"
      ]
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  {
    "SIMD_ISA": "Neon",
    "name": "vtrn2q_u8",
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      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
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    ],
    "instructions": [
      [
        "TRN2"
      ]
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  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtrn_f16",
    "arguments": [
      "float16x4_t a",
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      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vtstq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "CMTST"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadd_s16",
    "arguments": [
      "int16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4H"
      },
      "b": {
        "register": "Vn.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadd_s32",
    "arguments": [
      "int32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2S"
      },
      "b": {
        "register": "Vn.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadd_s64",
    "arguments": [
      "int64x1_t a",
      "uint64x1_t b"
    ],
    "return_type": {
      "value": "int64x1_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadd_s8",
    "arguments": [
      "int8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8B"
      },
      "b": {
        "register": "Vn.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddb_s8",
    "arguments": [
      "int8_t a",
      "uint8_t b"
    ],
    "return_type": {
      "value": "int8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Bd"
      },
      "b": {
        "register": "Bn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddd_s64",
    "arguments": [
      "int64_t a",
      "uint64_t b"
    ],
    "return_type": {
      "value": "int64_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dd"
      },
      "b": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddh_s16",
    "arguments": [
      "int16_t a",
      "uint16_t b"
    ],
    "return_type": {
      "value": "int16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Hd"
      },
      "b": {
        "register": "Hn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddq_s16",
    "arguments": [
      "int16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.8H"
      },
      "b": {
        "register": "Vn.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddq_s32",
    "arguments": [
      "int32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.4S"
      },
      "b": {
        "register": "Vn.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddq_s64",
    "arguments": [
      "int64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.2D"
      },
      "b": {
        "register": "Vn.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqaddq_s8",
    "arguments": [
      "int8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vd.16B"
      },
      "b": {
        "register": "Vn.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuqadds_s32",
    "arguments": [
      "int32_t a",
      "uint32_t b"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Sd"
      },
      "b": {
        "register": "Sn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "SUQADD"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdot_lane_s32",
    "arguments": [
      "int32x2_t r",
      "uint8x8_t a",
      "int8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdot_laneq_s32",
    "arguments": [
      "int32x2_t r",
      "uint8x8_t a",
      "int8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdot_s32",
    "arguments": [
      "int32x2_t r",
      "uint8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      },
      "r": {
        "register": "Vd.2S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdotq_lane_s32",
    "arguments": [
      "int32x4_t r",
      "uint8x16_t a",
      "int8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdotq_laneq_s32",
    "arguments": [
      "int32x4_t r",
      "uint8x16_t a",
      "int8x16_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.4B"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusdotq_s32",
    "arguments": [
      "int32x4_t r",
      "uint8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "USDOT"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vusmmlaq_s32",
    "arguments": [
      "int32x4_t r",
      "uint8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      },
      "r": {
        "register": "Vd.4S"
      }
    },
    "Architectures": [
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "USMMLA"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1q_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1q_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1q_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "UZP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp1q_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
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      "value": "poly16x8_t"
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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      "value": "poly64x2_t"
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        "register": "Vn.2D"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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      "value": "poly8x16_t"
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "UZP1"
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  {
    "SIMD_ISA": "Neon",
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      "int16x8_t b"
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        "register": "Vn.8H"
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        "register": "Vm.8H"
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      [
        "UZP1"
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    "SIMD_ISA": "Neon",
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      "value": "int32x4_t"
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        "register": "Vn.4S"
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        "register": "Vm.4S"
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      [
        "UZP1"
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    "SIMD_ISA": "Neon",
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      "int64x2_t b"
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      "value": "int64x2_t"
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        "register": "Vn.2D"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "UZP1"
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  {
    "SIMD_ISA": "Neon",
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      "value": "uint16x8_t"
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        "register": "Vn.8H"
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      "b": {
        "register": "Vm.8H"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.4S"
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      "b": {
        "register": "Vm.4S"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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      "value": "uint64x2_t"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "UZP1"
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    "SIMD_ISA": "Neon",
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      "value": "float16x4_t"
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      "a": {
        "register": "Vn.4H"
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        "register": "Vm.4H"
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        "UZP2"
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    "SIMD_ISA": "Neon",
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        "UZP2"
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    "SIMD_ISA": "Neon",
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    "SIMD_ISA": "Neon",
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        "UZP2"
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    "SIMD_ISA": "Neon",
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      "value": "uint64x2_t"
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        "register": "Vn.2D"
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        "register": "Vm.2D"
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        "UZP2"
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    "SIMD_ISA": "Neon",
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        "register": "Vn.16B"
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        "register": "Vm.16B"
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        "UZP2"
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    "SIMD_ISA": "Neon",
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      "value": "float16x4x2_t"
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        "register": "Vn.4H"
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        "register": "Vm.4H"
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      "A64"
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        "UZP2"
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  {
    "SIMD_ISA": "Neon",
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      "float32x2_t b"
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      "value": "float32x2x2_t"
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        "register": "Vn.2S"
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        "register": "Vm.2S"
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      "A64"
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        "UZP2"
      ]
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  {
    "SIMD_ISA": "Neon",
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      "poly16x4_t b"
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      "value": "poly16x4x2_t"
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        "register": "Vn.4H"
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      "b": {
        "register": "Vm.4H"
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      "A32",
      "A64"
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        "UZP2"
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    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_p8",
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      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzp_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vuzpq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "UZP1",
        "UZP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vxarq_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b",
      "const int imm6"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {},
      "imm6": {
        "minimum": 0,
        "maximum": 63
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "XAR"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip1q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP1"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_p64",
    "arguments": [
      "poly64x2_t a",
      "poly64x2_t b"
    ],
    "return_type": {
      "value": "poly64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_s64",
    "arguments": [
      "int64x2_t a",
      "int64x2_t b"
    ],
    "return_type": {
      "value": "int64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_u64",
    "arguments": [
      "uint64x2_t a",
      "uint64x2_t b"
    ],
    "return_type": {
      "value": "uint64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip2q_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_f16",
    "arguments": [
      "float16x4_t a",
      "float16x4_t b"
    ],
    "return_type": {
      "value": "float16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_p16",
    "arguments": [
      "poly16x4_t a",
      "poly16x4_t b"
    ],
    "return_type": {
      "value": "poly16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_p8",
    "arguments": [
      "poly8x8_t a",
      "poly8x8_t b"
    ],
    "return_type": {
      "value": "poly8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_s16",
    "arguments": [
      "int16x4_t a",
      "int16x4_t b"
    ],
    "return_type": {
      "value": "int16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_s32",
    "arguments": [
      "int32x2_t a",
      "int32x2_t b"
    ],
    "return_type": {
      "value": "int32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_s8",
    "arguments": [
      "int8x8_t a",
      "int8x8_t b"
    ],
    "return_type": {
      "value": "int8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_u16",
    "arguments": [
      "uint16x4_t a",
      "uint16x4_t b"
    ],
    "return_type": {
      "value": "uint16x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4H"
      },
      "b": {
        "register": "Vm.4H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_u32",
    "arguments": [
      "uint32x2_t a",
      "uint32x2_t b"
    ],
    "return_type": {
      "value": "uint32x2x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzip_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b"
    ],
    "return_type": {
      "value": "uint8x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8B"
      },
      "b": {
        "register": "Vm.8B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_f16",
    "arguments": [
      "float16x8_t a",
      "float16x8_t b"
    ],
    "return_type": {
      "value": "float16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_p16",
    "arguments": [
      "poly16x8_t a",
      "poly16x8_t b"
    ],
    "return_type": {
      "value": "poly16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_p8",
    "arguments": [
      "poly8x16_t a",
      "poly8x16_t b"
    ],
    "return_type": {
      "value": "poly8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_s16",
    "arguments": [
      "int16x8_t a",
      "int16x8_t b"
    ],
    "return_type": {
      "value": "int16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_s32",
    "arguments": [
      "int32x4_t a",
      "int32x4_t b"
    ],
    "return_type": {
      "value": "int32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_s8",
    "arguments": [
      "int8x16_t a",
      "int8x16_t b"
    ],
    "return_type": {
      "value": "int8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_u16",
    "arguments": [
      "uint16x8_t a",
      "uint16x8_t b"
    ],
    "return_type": {
      "value": "uint16x8x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm.8H"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_u32",
    "arguments": [
      "uint32x4_t a",
      "uint32x4_t b"
    ],
    "return_type": {
      "value": "uint32x4x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vzipq_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x16_t b"
    ],
    "return_type": {
      "value": "uint8x16x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm.16B"
      }
    },
    "Architectures": [
      "v7",
      "A32",
      "A64"
    ],
    "instructions": [
      [
        "ZIP1",
        "ZIP2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamin_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaminq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vaminq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMIN"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamax_f32",
    "arguments": [
      "float32x2_t a",
      "float32x2_t b"
    ],
    "return_type": {
      "value": "float32x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2S"
      },
      "b": {
        "register": "Vm.2S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamaxq_f32",
    "arguments": [
      "float32x4_t a",
      "float32x4_t b"
    ],
    "return_type": {
      "value": "float32x4_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.4S"
      },
      "b": {
        "register": "Vm.4S"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vamaxq_f64",
    "arguments": [
      "float64x2_t a",
      "float64x2_t b"
    ],
    "return_type": {
      "value": "float64x2_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.2D"
      },
      "b": {
        "register": "Vm.2D"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FAMAX"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_u8",
    "arguments": [
      "uint8x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_u8",
    "arguments": [
      "uint8x16_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_s8",
    "arguments": [
      "int8x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_s8",
    "arguments": [
      "int8x16_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_p8",
    "arguments": [
      "poly8x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_p8",
    "arguments": [
      "poly8x16_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.16B"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_u16",
    "arguments": [
      "uint16x4_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_u16",
    "arguments": [
      "uint16x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_s16",
    "arguments": [
      "int16x4_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_s16",
    "arguments": [
      "int16x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2_lane_p16",
    "arguments": [
      "poly16x4_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti2q_lane_p16",
    "arguments": [
      "poly16x8_t a",
      "uint8x8_t b",
      "const int lane"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Vn.8H"
      },
      "b": {
        "register": "Vm"
      },
      "lane": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI2"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_lane_u8",
    "arguments": [
      "uint8x16_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn.16B"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_laneq_u8",
    "arguments": [
      "uint8x16_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint8x16_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn.16B"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_lane_s8",
    "arguments": [
      "int8x16_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn.16B"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_laneq_s8",
    "arguments": [
      "int8x16_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int8x16_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn.16B"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_lane_p8",
    "arguments": [
      "poly8x16_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn.16B"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 0
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_laneq_p8",
    "arguments": [
      "poly8x16_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly8x16_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn.16B"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.16B"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_lane_u16_x2",
    "arguments": [
      "uint16x8x2_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn1.8H"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_laneq_u16_x2",
    "arguments": [
      "uint16x8x2_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "uint16x8_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn1.8H"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_lane_s16_x2",
    "arguments": [
      "int16x8x2_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn1.8H"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_laneq_s16_x2",
    "arguments": [
      "int16x8x2_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "int16x8_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn1.8H"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_lane_f16_x2",
    "arguments": [
      "float16x8x2_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn1.8H"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_laneq_f16_x2",
    "arguments": [
      "float16x8x2_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "float16x8_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn1.8H"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_lane_p16_x2",
    "arguments": [
      "poly16x8x2_t vn",
      "uint8x8_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn1.8H"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 1
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "vluti4q_laneq_p16_x2",
    "arguments": [
      "poly16x8x2_t vn",
      "uint8x16_t vm",
      "const int index"
    ],
    "return_type": {
      "value": "poly16x8_t"
    },
    "Arguments_Preparation": {
      "vn": {
        "register": "Vn1.8H"
      },
      "vm": {
        "register": "Vm"
      },
      "index": {
        "minimum": 0,
        "maximum": 3
      },
      "r": {
        "register": "Vd.8H"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "LUTI4"
      ]
    ]
  },
  {
    "SIMD_ISA": "Neon",
    "name": "__jcvt",
    "arguments": [
      "float64_t a"
    ],
    "return_type": {
      "value": "int32_t"
    },
    "Arguments_Preparation": {
      "a": {
        "register": "Dn"
      }
    },
    "Architectures": [
      "A64"
    ],
    "instructions": [
      [
        "FJCVTZS"
      ]
    ]
  }
]
